Root/libubb/include/ubb/regs4740.h

1/*
2 * include/ubb/regs4740.h - Jz4740 register definitions (subset)
3 *
4 * Written 2011-2012 by Werner Almesberger
5 * Copyright 2011-2012 Werner Almesberger
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef UBB_REGS4740_H
14#define UBB_REGS4740_H
15
16#include <stdint.h>
17
18#include <ubb/regbase.h>
19
20
21#define _CGU(n) REG(0x0000000+(n))
22#define _INTC(n) REG(0x0001000+(n))
23#define _TCU(n) REG(0x0002000+(n))
24#define _MSC(n) REG(0x0021000+(n))
25#define _DMAC(n) REG(0x3020000+(n))
26#define _LCD(n) REG(0x3050000+(n))
27
28#define CPCCR _CGU(0x0000) /* Clock Control */
29#define CLKGR _CGU(0x0020) /* Clock Gate */
30#define MSCCDR _CGU(0x0068) /* MSC device clock divider */
31
32#define ICMR _INTC(0x04) /* Interrupt controller mask */
33#define ICMSR _INTC(0x08) /* Interrupt controller mask set */
34#define ICMCR _INTC(0x0c) /* Interrupt controller mask clear */
35
36#define TSSR _TCU(0x2c) /* Timer STOP set */
37#define TSCR _TCU(0x3c) /* Timer STOP clear */
38#define TESR _TCU(0x14) /* Timer counter enable set */
39#define TECR _TCU(0x18) /* Timer counter enable clear */
40#define TFR _TCU(0x20) /* Timer flag */
41#define TFSR _TCU(0x24) /* Timer flag set */
42#define TFCR _TCU(0x28) /* Timer flag clear */
43#define TCSR(n) _TCU(0x4c+0x10*(n)) /* Timer control */
44#define TDFR(n) _TCU(0x40+0x10*(n)) /* Timer data full */
45#define TDHR(n) _TCU(0x44+0x10*(n)) /* Timer data half */
46#define TCNT(n) _TCU(0x48+0x10*(n)) /* Timer counter */
47
48/* MSC */
49
50#define MSC_STRPCL _MSC(0x00) /* Start/stop MMC/SD clock */
51#define MSC_STRPCRL_EXIT_MULTIPLE (1 << 7)
52#define MSC_STRPCRL_EXIT_TRANSFER (1 << 6)
53#define MSC_STRPCRL_START_READWAIT (1 << 5)
54#define MSC_STRPCRL_STOP_READWAIT (1 << 4)
55#define MSC_STRPCRL_RESET (1 << 3)
56#define MSC_STRPCRL_START_OP (1 << 2)
57#define MSC_STRPCRL_START_CLOCK (1 << 1)
58#define MSC_STRPCRL_STOP_CLOCK (1 << 0)
59
60#define MSC_STAT _MSC(0x04) /* MSC status */
61#define MSC_STAT_IS_RESETTING (1 << 15)
62#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
63#define MSC_STAT_PRG_DONE (1 << 13)
64#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
65#define MSC_STAT_END_CMD_RES (1 << 11)
66#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) /* almost full */
67#define MSC_STAT_IS_READWAIT (1 << 9)
68#define MSC_STAT_CLK_EN (1 << 8)
69#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
70#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
71#define MSC_STAT_CRC_RES_ERR (1 << 5)
72#define MSC_STAT_CRC_READ_ERROR (1 << 4)
73#define MSC_STAT_CRC_WRITE_ERROR_MASK (3 << MSC_STAT_CRC_WRITE_ERROR_SHIFT)
74#define MSC_STAT_CRC_WRITE_ERROR_SHIFT 2
75#define MSC_STAT_CRC_WRITE_ERROR_ERROR 1 /* error reported */
76#define MSC_STAT_CRC_WRITE_ERROR_NOSTAT 2 /* no CRC status */
77#define MSC_STAT_TIME_OUT_RES (1 << 1)
78#define MSC_STAT_TIME_OUT_READ (1 << 0)
79
80#define MSC_CLKRT _MSC(0x08) /* MSC clock rate */
81#define MSC_CLKRT_MASK 7
82
83#define MSC_CMDAT _MSC(0x0c) /* MMC/SD command and data control */
84#define MSC_CMDAT_IO_ABORT (1 << 11)
85#define MSC_CMDAT_BUS_WIDTH_MASK (3 << MSC_CMDAT_BUS_WIDTH_SHIFT)
86#define MSC_CMDAT_BUS_WIDTH_SHIFT 9
87#define MSC_CMDAT_BUS_WIDTH_1 0
88#define MSC_CMDAT_BUS_WIDTH_4 2
89#define MSC_CMDAT_DMA_EN (1 << 8)
90#define MSC_CMDAT_INIT (1 << 7)
91#define MSC_CMDAT_BUSY (1 << 6)
92#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
93#define MSC_CMDAT_WRITE_READ (1 << 4)
94#define MSC_CMDAT_DATA_EN (1 << 3)
95#define MSC_CMDAT_RESPONSE_FORMAT_MASK (7 << MSC_CMDAT_RESPONSE_FORMAT_SHIFT)
96#define MSC_CMDAT_RESPONSE_FORMAT_SHIFT 0
97#define MSC_CMDAT_RESPONSE_FORMAT_NONE 0
98#define MSC_CMDAT_RESPONSE_FORMAT_R1 1 /* or R1b */
99#define MSC_CMDAT_RESPONSE_FORMAT_R2 2
100#define MSC_CMDAT_RESPONSE_FORMAT_R3 3
101#define MSC_CMDAT_RESPONSE_FORMAT_R4 4
102#define MSC_CMDAT_RESPONSE_FORMAT_R5 5
103#define MSC_CMDAT_RESPONSE_FORMAT_R6 6
104
105#define MSC_RESTO _MSC(0x10) /* MMC/SD response time out */
106#define MSC_RESTO_MASK 0xff /* in MSC_CLK */
107
108#define MSC_RDTO _MSC(0x14) /* MMC/SD read time out */
109#define MSC_RDTO_MASK 0xffff /* in CLK_SRC/256 */
110
111#define MSC_BLKLEN _MSC(0x18) /* MMC/SD block length */
112#define MSC_BLKLEN_MASK 0xfff
113
114#define MSC_NOB _MSC(0x1c) /* MMC/SD number of blocks */
115#define MSC_NOB_MASK 0xffff
116
117#define MSC_SNOB _MSC(0x20) /* MMC/SD successful blocks */
118#define MSC_SNOB_MASK 0xffff
119
120#define MSC_IMASK _MSC(0x24) /* MMC/SD interrupt mask */
121#define MSC_INT_SDIO (1 << 7)
122#define MSC_INT_TXFIFO_WR_REQ (1 << 6)
123#define MSC_INT_RXFIFO_RD_REQ (1 << 5)
124#define MSC_INT_END_CMD_RES (1 << 2)
125#define MSC_INT_PRG_DONE (1 << 1)
126#define MSC_INT_DATA_TRAN_DONE (1 << 0)
127
128#define MSC_IREG _MSC(0x28) /* MMC/SD interrupt */
129
130#define MSC_CMD _MSC(0x2c) /* MMC/SD command index */
131#define MSC_CMD_MASK 0x3f
132
133#define MSC_ARG _MSC(0x30) /* MMC/SD command argument */
134
135#define MSC_RES _MSC(0x34) /* MMC?SD response FIFO */
136#define MSC_RXFIFO_MASK 0xffff /* 8 x 16 bits */
137
138#define MSC_RXFIFO _MSC(0x38) /* MMC/SD receive data FIFO */
139
140#define MSC_TXFIFO _MSC(0x3c) /* MMC/SD transmit data FIFO */
141
142/* DMA */
143
144#define _DMAn(n, r) _DMAC(0x20*(n)+(r))
145
146#define DSA(n) _DMAn(n, 0x00) /* DMA source address */
147
148#define DTA(n) _DMAn(n, 0x04) /* DMA target address */
149
150#define DTC(n) _DMAn(n, 0x08) /* DMA transfer count */
151#define DTC_MASK 0xffffff
152
153#define DRT(n) _DMAn(n, 0x0c) /* DMA request type */
154#define DRT_MASK 0x1f
155#define DRT_AUTO 8 /* external to external */
156#define DRT_UART_TX 20
157#define DRT_UART_RX 21
158#define DRT_SSI_TX 22
159#define DRT_SSI_RX 23
160#define DRT_AIC_TX 24
161#define DRT_AIC_RX 25
162#define DRT_MSC_TX 26
163#define DRT_MSC_RX 27
164#define DRT_TCU 28
165#define DRT_SADC 29
166#define DRT_SLCD 30
167
168#define DCS(n) _DMAn(n, 0x10) /* DMA channel control/status */
169#define DCS_NDES (1 << 31) /* No-Descriptor Transfer */
170#define DCS_CDOA_MASK (0xff << DCS_CDOA_SHIFT)
171                    /* Copy of Descriptor Offset Address */
172#define DCS_CDOA_SHIFT 16
173#define DCS_INV (1 << 6) /* Descriptor invalid error */
174#define DCS_AR (1 << 4) /* Address error */
175#define DCS_TT (1 << 3) /* Transfer terminated */
176#define DCS_HLT (1 << 2) /* DMA halt */
177#define DCS_CT (1 << 1) /* Link DMA transfer end */
178#define DCS_CTE (1 << 0) /* Channel enabled */
179
180#define DCM(n) _DMAn(n, 0x14) /* DMA command */
181#define DCM_SAI (1 << 23) /* Source address increment */
182#define DCM_DAI (1 << 22) /* Destination address increment */
183#define DCM_RDIL_MASK (15 << DCM_RDIL_SHIFT)
184                    /* Request Detection Interval Length */
185#define DCM_RDIL_SHIFT 16
186#define DCM_RDIL_0 0
187#define DCM_RDIL_2 1 /* 2 units, etc. */
188#define DCM_RDIL_4 2
189#define DCM_RDIL_8 3
190#define DCM_RDIL_12 4
191#define DCM_RDIL_16 5
192#define DCM_RDIL_20 6
193#define DCM_RDIL_24 7
194#define DCM_RDIL_28 8
195#define DCM_RDIL_32 9
196#define DCM_RDIL_48 10
197#define DCM_RDIL_60 11
198#define DCM_RDIL_64 12
199#define DCM_RDIL_124 13
200#define DCM_RDIL_128 14
201#define DCM_RDIL_200 15
202#define DCM_SP_MASK (3 << DCM_SP_SHIFT) /* Source port width */
203#define DCM_SP_SHIFT 14
204#define DCM_SP_32 0 /* 32 bit */
205#define DCM_SP_8 1
206#define DCM_SP_16 2
207#define DCM_DP_MASK (3 << DCM_DP_SHIFT) /* Destination port width */
208#define DCM_DP_SHIFT 12
209#define DCM_DP_32 0 /* 32 bit */
210#define DCM_DP_8 1
211#define DCM_DP_16 2
212#define DCM_TSZ_MASK (7 << DCM_TSZ_SHIFT) /* Transfer data size (unit) */
213#define DCM_TSZ_SHIFT 8
214#define DCM_TSZ_32BIT 0
215#define DCM_TSZ_8BIT 1
216#define DCM_TSZ_16BYTE 3
217#define DCM_TSZ_32BYTE 4
218#define DCM_TM (1 << 7) /* Transfer mode (0 single, 1 block) */
219#define DCM_V (1 << 4) /* Descriptor valid */
220#define DCM_VM (1 << 3) /* Descriptor valid mode */
221#define DCM_VIE (1 << 2) /* DMA valid error Interrupt Enable */
222#define DCM_TIE (1 << 1) /* Transfer Interrupt Enable (TIE) */
223#define DCM_LINK (1 << 0) /* Descriptor link enable */
224
225#define DMAC _DMAC(0x300) /* DMA control */
226#define DMAC_PM_MASK (3 << DMAC_PM_SHIFT)
227                    /* Channel priority mode */
228#define DMAC_PM_SHIFT 8
229#define DMAC_PM_012345 0 /* CH0 > CH1 > .. */
230#define DMAC_PM_023145 1
231#define DMAC_PM_201345 2
232#define DMAC_PM_RR 3 /* Round robin */
233#define DMAC_HLT (1 << 3) /* Global halt status */
234#define DMAC_AR (1 << 2) /* Global address error status */
235#define DMAC_DMAE (1 << 0) /* Global DMA transfer enable */
236
237#define DDR _DMAC(0x308) /* DMA doorbell */
238
239#define LCDCTRL _LCD(0x30) /* LCD control */
240
241#endif /* !UBB_REGS4740_H */
242

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