Root/libubb/mmcclk.c

1/*
2 * libubb/mmcclk.c - Calculate MMC bus clock speed
3 *
4 * Written 2013 by Werner Almesberger
5 * Copyright 2013 Werner Almesberger
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13
14#include <ubb/regs4740.h>
15#include <ubb/mmcclk.h>
16
17
18#define MSCCDR_MAX 32
19#define CLKRT_MAX 8
20
21/*
22 * Nominally, the limit is 20 MHz. A clock can be obtained until 84 MHz,
23 * possibly even higher. Beyond 56 MHz, the MMC controller in some Bens
24 * has been observed to fail to complete the operation when attempting
25 * data transmission.
26 *
27 * Some Bens still work fine at 84 MHz.
28 */
29
30#define BUS_SAFE_MHZ 56 /* always works */
31#define BUS_UNSAFE_MHZ 84 /* some devices don't like this */
32
33
34static int calculate_clock(struct mmcclk *dsc)
35{
36    dsc->bus_clk_hz = dsc->sys_clk_hz/(dsc->clkdiv+1.0)/(1 << dsc->clkrt);
37    if (dsc->flags & MMCCLK_FLAG_ALL)
38        return 1;
39    if ((dsc->flags & MMCCLK_FLAG_UNSAFE) &&
40        dsc->bus_clk_hz <= BUS_UNSAFE_MHZ*1000000)
41        return 1;
42    return dsc->bus_clk_hz <= BUS_SAFE_MHZ*1000000;
43}
44
45
46void mmcclk_first(struct mmcclk *dsc, int sys_clk_hz, unsigned flags)
47{
48    if (sys_clk_hz)
49        dsc->sys_clk_hz = sys_clk_hz;
50    else
51        dsc->sys_clk_hz =
52            (CPCCR >> 21) & 1 ? BEN_PLL_CLK_HZ : BEN_PLL_CLK_HZ/2;
53    dsc->flags = flags;
54    dsc->clkdiv = dsc->clkrt = 0;
55    if (calculate_clock(dsc))
56        return;
57    mmcclk_next(dsc);
58}
59
60
61int mmcclk_next(struct mmcclk *dsc)
62{
63    while (1) {
64        if (++dsc->clkdiv == MSCCDR_MAX) {
65            dsc->clkdiv = 0;
66            if (++dsc->clkrt == CLKRT_MAX)
67                return 0;
68        }
69        if (calculate_clock(dsc))
70            return 1;
71    }
72}
73
74
75void mmcclk_start(struct mmcclk *dsc)
76{
77    MSCCDR = dsc->clkdiv; /* set controller clock */
78    CLKGR &= ~(1 << 7); /* enable MSC clock */
79
80    MSC_STRPCL = MSC_STRPCRL_RESET; /* reset the MSC */
81    while (MSC_STAT & MSC_STAT_IS_RESETTING);
82                    /* wait until reset finishes */
83
84    MSC_CLKRT = dsc->clkrt; /* set bus clock */
85    MSC_STRPCL = MSC_STRPCRL_START_CLOCK;
86}
87
88
89void mmcclk_stop(void)
90{
91    MSC_STRPCL = MSC_STRPCRL_STOP_CLOCK;
92}
93

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