Root/ubb-vga/regs4740.h

1/*
2 * regs4740.h - Jz4740 register definitions (subset)
3 *
4 * Written 2011 by Werner Almesberger
5 * Copyright 2011 Werner Almesberger
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef REGS4740_H
14#define REGS4740_H
15
16#include <stdint.h>
17
18
19#define SOC_BASE 0x10000000
20#define REG_WINDOW 0x4000000
21
22#define REG(n) (*(volatile uint32_t *) ((void *) (REG_BASE_PTR)+(n)))
23
24#define REG_PADDR(r) ((unsigned long) \
25                ((void *) &(r)-(void *) (REG_BASE_PTR)+SOC_BASE))
26
27#define _CGU(n) REG(0x0000000+(n))
28#define _INTC(n) REG(0x0001000+(n))
29#define _TCU(n) REG(0x0002000+(n))
30#define _GPIO(n) REG(0x0010000+(n))
31#define _MSC(n) REG(0x0021000+(n))
32#define _DMAC(n) REG(0x3020000+(n))
33#define _LCD(n) REG(0x3050000+(n))
34
35#define CLKGR _CGU(0x0020) /* Clock Gate */
36#define MSCCDR _CGU(0x0068) /* MSC device clock divider */
37
38#define PDPIN _GPIO(0x300) /* port D pin level */
39#define PDDATS _GPIO(0x314) /* port D data set */
40#define PDDATC _GPIO(0x318) /* port D data clear */
41#define PDFUNS _GPIO(0x344) /* port D function set */
42#define PDFUNC _GPIO(0x348) /* port D function clear */
43#define PDDIRS _GPIO(0x364) /* port D direction set */
44#define PDDIRC _GPIO(0x368) /* port D direction clear */
45
46#define ICMR _INTC(0x04) /* Interrupt controller mask */
47#define ICMSR _INTC(0x08) /* Interrupt controller mask set */
48#define ICMCR _INTC(0x0c) /* Interrupt controller mask clear */
49
50#define TSSR _TCU(0x2c) /* Timer STOP set */
51#define TSCR _TCU(0x3c) /* Timer STOP clear */
52#define TESR _TCU(0x14) /* Timer counter enable set */
53#define TECR _TCU(0x18) /* Timer counter enable clear */
54#define TFR _TCU(0x20) /* Timer flag */
55#define TFSR _TCU(0x24) /* Timer flag set */
56#define TFCR _TCU(0x28) /* Timer flag clear */
57#define TCSR(n) _TCU(0x4c+0x10*(n)) /* Timer control */
58#define TDFR(n) _TCU(0x40+0x10*(n)) /* Timer data full */
59#define TDHR(n) _TCU(0x44+0x10*(n)) /* Timer data half */
60#define TCNT(n) _TCU(0x48+0x10*(n)) /* Timer counter */
61
62#define MSC_STRPCL _MSC(0x00) /* Start/stop MMC/SD clock */
63#define MSC_STAT _MSC(0x04) /* MSC status */
64#define MSC_CLKRT _MSC(0x08) /* MSC clock rate */
65#define MSC_CMDAT _MSC(0x0c) /* MMC/SD command and data control */
66#define MSC_RESTO _MSC(0x10) /* MMC/SD response time out */
67#define MSC_BLKLEN _MSC(0x18) /* MMC/SD block length */
68#define MSC_NOB _MSC(0x1c) /* MMC/SD number of blocks */
69#define MSC_SNOB _MSC(0x20) /* MMC/SD successful blocks */
70#define MSC_IMASK _MSC(0x24) /* MMC/SD interrupt mask */
71#define MSC_IREG _MSC(0x28) /* MMC/SD interrupt */
72#define MSC_CMD _MSC(0x2c) /* MMC/SD command index */
73#define MSC_ARG _MSC(0x30) /* MMC/SD command argument */
74#define MSC_RXFIFO _MSC(0x38) /* MMC/SD receive data FIFO */
75#define MSC_TXFIFO _MSC(0x3c) /* MMC/SD transmit data FIFO */
76
77#define _DMAn(n, r) _DMAC(0x20*(n)+(r))
78
79#define DSA(n) _DMAn(n, 0x00) /* DMA source address */
80#define DTA(n) _DMAn(n, 0x04) /* DMA target address */
81#define DTC(n) _DMAn(n, 0x08) /* DMA transfer count */
82#define DRT(n) _DMAn(n, 0x0c) /* DMA request type */
83#define DCS(n) _DMAn(n, 0x10) /* DMA channel control/status */
84#define DCM(n) _DMAn(n, 0x14) /* DMA command */
85#define DMAC _DMAC(0x300) /* DMA control */
86#define DDR _DMAC(0x308) /* DMA doorbell */
87
88#define LCDCTRL _LCD(0x30) /* LCD control */
89
90#endif /* !REGS4740_H */
91

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