Date:2011-01-07 15:52:45 (8 years 9 months ago)
Author:Werner Almesberger
Commit:4387d844dc6d6c1c334c3531fa3dbe338910f594
Message:atusb/fw/include/at86rf230.h: added remaining AT86RF231 values

Files: atusb/fw/include/at86rf230.h (11 diffs)

Change Details

atusb/fw/include/at86rf230.h
8282    REG_CSMA_BE = 0x2f, /* 231 only */
8383
8484    REG_CONT_TX_0 = 0x36,
85    REG_CONT_TX_1 = 0x3d,
85    REG_CONT_TX_1 = 0x3d, /* 230 only */
8686};
8787
8888/* --- TRX_STATUS --- ------------------------------------------------------ */
...... 
180180
181181#define PA_EXT_EN (1 << 8)
182182#define IRQ_2_EXT_EN (1 << 7)
183#define TX_AUTO_CRC_ON_231 (1 << 6) /* 231 */
183#define TX_AUTO_CRC_ON_231 (1 << 6) /* 231 location */
184184
185185#define SPI_CMD_MODE_SHIFT 2
186186#define SPI_CMD_MODE_MASK 3
...... 
195195#define IRQ_MASK_MODE (1 << 1)
196196#define IRQ_POLARITY (1 << 0)
197197
198/* --- PHY_TX_PWR -====----------------------------------------------------- */
198/* --- PHY_TX_PWR ---------------------------------------------------------- */
199199
200#define TX_AUTO_CRC_ON (1 << 7) /* 230 */
200#define TX_AUTO_CRC_ON (1 << 7) /* 230 location */
201201
202202#define TX_PWR_SHIFT 0
203203#define TX_PWR_MASK 0x0f
...... 
206206
207207#define RX_CRC_VALID (1 << 7)
208208
209#define RND_VALUE_SHIFT 5 /* 231 */
210#define RND_VALUE_MASK 3
211
209212#define RSSI_SHIFT 0
210213#define RSSI_MASK 0x1f
211214
...... 
216219#define CCA_MODE_SHIFT 5
217220#define CCA_MODE_MASK 3
218221
222enum {
223    CCA_MODE_CARRIER_OR_ENERGY = 0, /* 231 only */
224    CCA_MODE_ENERGY = 1,
225    CCA_MODE_CARRIER = 2,
226    CCA_MODE_CARRIER_AND_ENERGY = 3
227};
228
219229#define CHANNEL_SHIFT 0
220230#define CHANNEL_MASK 0x1f
221231
...... 
224234#define CCA_ED_THRES_SHIFT 0
225235#define CCA_ED_THRES_MASK 0x0f
226236
237/* --- RX_CTRL (231 only) -------------------------------------------------- */
238
239#define PDT_THRES_SHIFT 0
240#define PDT_THRES_MASK 0x0f
241
242enum {
243    PDT_THRES_DEFAULT = 0x07, /* reset default */
244    PDT_THRES_DIVERSITY = 0x03,
245};
246
247/* --- TRX_CTRL_2 (231 only) ----------------------------------------------- */
248
249#define RX_SAFE_MODE (1 << 7)
250
251#define OQPSK_DATA_RATE_SHIFT 0
252#define OQPSK_DATA_RATE_MASK 3
253
254enum {
255    OQPSK_DATA_RATE_250 = 0, /* reset default */
256    OQPSK_DATA_RATE_500 = 1,
257    OQPSK_DATA_RATE_1000 = 2,
258    OQPSK_DATA_RATE_2000 = 3
259};
260
227261/* --- IRQ_MASK/IRQ_STATUS ------------------------------------------------- */
228262
229263enum {
...... 
231265    IRQ_PLL_UNLOCK = 1 << 1,
232266    IRQ_RX_START = 1 << 2,
233267    IRQ_TRX_END = 1 << 3,
268    IRQ_CCA_ED_DONE = 1 << 4, /* 231 only */
269    IRQ_AMI = 1 << 5, /* 231 only */
234270    IRQ_TRX_UR = 1 << 6,
235271    IRQ_BAT_LOW = 1 << 7
236272};
...... 
256292#define XTAL_MODE_MASK 0x0f
257293
258294enum {
259    XTAL_MODE_OFF = 0x0,
295    XTAL_MODE_OFF = 0x0, /* 230 only */
260296    XTAL_MODE_EXT = 0x4,
261297    XTAL_MODE_INT = 0xf /* reset default */
262298};
...... 
264300#define XTAL_TRIM_SHIFT 4
265301#define XTAL_TRIM_MASK 0x0f
266302
267/* --- XAH_CTRL ------------------------------------------------------------ */
303/* --- RX_SYN (231 only) --------------------------------------------------- */
268304
269#define MAX_FRAME_RETRIES_SHIFT 4
270#define MAX_FRAME_RETRIES_MASK 0x0f
305#define RX_PDT_DIS (1 << 7)
271306
272#define MAX_CSMA_RETRIES_SHIFT 1
273#define MAX_CSMA_RETRIES_MASK 0x07
307#define RX_PDT_LEVEL_SHIFT 0
308#define RX_PDT_LEVEL_MASK 0xf
309
310/* --- XAH_CTRL_1 (231 only) ----------------------------------------------- */
311
312#define AACK_FLTR_RES_FT (1 << 5)
313#define AACK_UPLD_RES_FT (1 << 4)
314#define AACK_ACK_TIME (1 << 2)
315#define AACK_PROM_MODE (1 << 1)
316
317/* --- FTN_CTRL (231 only) ------------------------------------------------- */
318
319#define FTN_START (1 << 7)
274320
275321/* --- PLL_CF -------------------------------------------------------------- */
276322
...... 
280326
281327#define PLL_DCU_START (1 << 7)
282328
329/* --- XAH_CTRL_0 (XAH_CTRL in 230) ---------------------------------------- */
330
331#define MAX_FRAME_RETRIES_SHIFT 4
332#define MAX_FRAME_RETRIES_MASK 0x0f
333
334#define MAX_CSMA_RETRIES_SHIFT 1
335#define MAX_CSMA_RETRIES_MASK 0x07
336
337#define SLOTTED_OPERATION (1 << 0) /* 231 only */
338
283339/* --- CSMA_SEED_1 --------------------------------------------------------- */
284340
285#define MIN_BE_SHIFT 6
286#define MIN_BE_MASK 3
341#define MIN_BE_SHIFT_230 6 /* 230 location */
342#define MIN_BE_MASK_230 3
343
344#define AACK_FVN_MODE_SHIFT 6 /* 231 only */
345#define AACK_FVN_MODE_MASK 3
346
347enum {
348    AACK_FVN_MODE_0 = 0,
349    AACK_FVN_MODE_01 = 1, /* reset default */
350    AACK_FVN_MODE_012 = 2,
351    AACK_FVN_MODE_ANY = 3
352};
287353
288354#define AACK_SET_PD (1 << 5)
289355
...... 
292358#define CSMA_SEED_1_SHIFT 0
293359#define CSMA_SEED_1_MASK 7
294360
361/* --- CSMA_BE ------------------------------------------------------------- */
362
363#define MAX_BE_SHIFT 4
364#define MAX_BE_MASK 0x0f
365
366#define MIN_BE_SHIFT 0 /* 231 location */
367#define MIN_BE_MASK 0x0f
368
295369/* --- REG_CONT_TX_0 ------------------------------------------------------- */
296370
297371#define CONT_TX_MAGIC 0x0f
298372
299/* --- REG_CONT_TX_1 ------------------------------------------------------- */
373/* --- REG_CONT_TX_1 (230 only) -------------------------------------------- */
300374
301375#define CONT_TX_MOD 0x00 /* modulated */
302376#define CONT_TX_M2M 0x10 /* f_CH-2 MHz */

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