Date:2010-09-09 17:35:47 (8 years 11 months ago)
Author:Werner Almesberger
Commit:6e726d1fb90ec8f182984a426ea05b15b5adc3b8
Message:Improved clock stability by using a capacitative divider and found more minor issues.

- atusd/ERRATA: work around the clock instability by replacing the
resistive divider with a capacitative divider
- atusd/ERRATA: a ground plane under the clock circuit would also be good to
have
- atusd/ERRATA: via near pin 1 is too close to the chip if we need to cut
wires (in DIY boards)
- atusd/sim/cdiv.sch: simulation of the capacitative divider
Files: atusd/ERRATA (1 diff)
atusd/sim/cdiv.sch (1 diff)

Change Details

atusd/ERRATA
1717
1818- SPI activity causes the PLL to unlock. Specifically, toggling nSEL does
1919  this.
20
21- work-around on second 20100908 board: replace the resistive divider with
22  a capacitative divider. See sim/cdiv.sch. This is a simple BOM change:
23
24  C7 -> 0 R
25  R3 -> 33 pF
26  R4 -> 220 pF
27
28- considering that the clock input has a Vpp of only 400-500 mV, we should
29  have a ground plane also under as much of the the clock circuit as
30  possible.
31
32- via between pins 1 and 32 is too close to the chip for DIY PCBs
atusd/sim/cdiv.sch
1<Qucs Schematic 0.0.15>
2<Properties>
3  <View=0,-120,870,882,1,0,0>
4  <Grid=10,10,1>
5  <DataSet=cdiv.dat>
6  <DataDisplay=cdiv.dpl>
7  <OpenDisplay=1>
8  <showFrame=0>
9  <FrameText0=Title>
10  <FrameText1=Drawn By:>
11  <FrameText2=Date:>
12  <FrameText3=Revision:>
13</Properties>
14<Symbol>
15</Symbol>
16<Components>
17  <GND * 1 220 400 0 0 0 0>
18  <GND * 1 100 400 0 0 0 0>
19  <Vrect V1 1 100 310 18 -26 0 1 "3.3 V" 1 "31 ns" 1 "31 ns" 1 "1 ns" 0 "1 ns" 0 "0 ns" 0>
20  <.DC DC1 1 120 40 0 36 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
21  <.TR TR1 1 310 40 0 57 0 0 "lin" 1 "0" 1 "1 us" 1 "10000" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
22  <C C1 1 220 350 17 -26 0 1 "220 pF" 1 "" 0 "neutral" 0>
23  <R R1 1 150 200 -26 15 0 0 "50 Ohm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
24  <C C2 1 220 250 17 -26 0 1 " 33 pF" 1 "" 0 "neutral" 0>
25</Components>
26<Wires>
27  <100 340 100 400 "" 0 0 0 "">
28  <220 280 220 320 "Vout" 250 270 17 "">
29  <220 380 220 400 "" 0 0 0 "">
30  <100 200 100 280 "" 0 0 0 "">
31  <100 200 120 200 "" 0 0 0 "">
32  <180 200 220 200 "" 0 0 0 "">
33  <220 200 220 220 "" 0 0 0 "">
34</Wires>
35<Diagrams>
36  <Rect 360 416 414 196 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
37    <"Vout.Vt" #0000ff 0 3 0 0 0>
38  </Rect>
39  <Rect 360 683 421 203 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
40    <"V1.It" #0000ff 0 3 0 0 0>
41  </Rect>
42  <Tab 530 210 300 200 3 #c0c0c0 1 00 1 923 1 1 1 0 1 1 1 0 1 10000 315 0 225 "" "" "">
43    <"Vout.Vt" #0000ff 0 3 1 0 0>
44  </Tab>
45</Diagrams>
46<Paintings>
47</Paintings>

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