Date:2011-01-07 13:16:51 (8 years 9 months ago)
Author:Werner Almesberger
Commit:bd5b008c44baf01201efd8a8dc3b429f2925dd76
Message:atusb/fw/include/at86rf230.h: make one section per register, not one per field

Looked too confusing.
Files: atusb/fw/include/at86rf230.h (9 diffs)

Change Details

atusb/fw/include/at86rf230.h
8585    REG_CONT_TX_1 = 0x3d,
8686};
8787
88/* --- TRX_STATUS [7] ------------------------------------------------------ */
88/* --- TRX_STATUS --- ------------------------------------------------------ */
8989
9090#define CCA_DONE (1 << 7)
91
92/* --- TRX_STATUS [6] ------------------------------------------------------ */
93
9491#define CCA_STATUS (1 << 6)
9592
96/* --- TRX_STATUS [4:0] ---------------------------------------------------- */
97
9893#define TRX_STATUS_SHIFT 0
9994#define TRX_STATUS_MASK 0x1f
10095
...... 
116111    TRX_STATUS_TRANSITION = 0x1f /* ..._IN_PROGRESS */
117112};
118113
119/* --- TRX_STATE [7:5] ----------------------------------------------------- */
114/* --- TRX_STATE ----------------------------------------------------------- */
120115
121116#define TRAC_STATUS_SHIFT 5
122117#define TRAC_STATUS_MASK 7
...... 
130125    TRAC_STATUS_INVALID = 7
131126};
132127
133/* --- TRX_STATE [4:0] ----------------------------------------------------- */
134
135128#define TRX_CMD_SHIFT 0
136129#define TRX_CMD_MASK 7
137130
...... 
147140    TRX_CMD_TX_ARET_ON = 0x19,
148141};
149142
150/* --- TRX_CTRL_0 [7:6] ---------------------------------------------------- */
143/* --- TRX_CTRL_0 ---------------------------------------------------------- */
151144
152145#define PAD_IO_SHIFT 6
153146#define PAD_IO_MASK 3
...... 
159152    PAD_IO_8mA
160153};
161154
162/* --- TRX_CTRL_0 [5:4] ---------------------------------------------------- */
163
164155#define PAD_IO_CLKM_SHIFT 4
165156#define PAD_IO_CLKM_MASK 3
166157
...... 
171162    PAD_IO_CLKM_8mA,
172163};
173164
174/* --- TRX_CTRL_0 [3] ------------------------------------------------------ */
175
176165#define CLKM_SHA_SEL (1 << 3)
177166
178/* --- TRX_CTRL_0 [2:0] ---------------------------------------------------- */
179
180167#define CLKM_CTRL_SHIFT 0
181168#define CLKM_CTRL_MASK 3
182169
...... 
208195#define IRQ_MASK_MODE (1 << 1)
209196#define IRQ_POLARITY (1 << 0)
210197
211/* --- PHY_TX_PWR [7] ------------------------------------------------------ */
198/* --- PHY_TX_PWR -====----------------------------------------------------- */
212199
213200#define TX_AUTO_CRC_ON (1 << 7) /* 230 */
214201
215/* --- PHY_TX_PWR [3:0] ---------------------------------------------------- */
216
217202#define TX_PWR_SHIFT 0
218203#define TX_PWR_MASK 0x0f
219204
220/* --- PHY_RSSI [7] -------------------------------------------------------- */
205/* --- PHY_RSSI ------------------------------------------------------------ */
221206
222207#define RX_CRC_VALID (1 << 7)
223208
224/* --- PHY_RSSI [4:0] ------------------------------------------------------ */
225
226209#define RSSI_SHIFT 0
227210#define RSSI_MASK 0x1f
228211
229/* --- PHY_CC_CCA [7] ------------------------------------------------------ */
212/* --- PHY_CC_CCA ---------------------------------------------------------- */
230213
231214#define CCA_REQUEST (1 << 7)
232215
233/* --- PHY_CC_CCA [6:5] ---------------------------------------------------- */
234
235216#define CCA_MODE_SHIFT 5
236217#define CCA_MODE_MASK 3
237218
238/* --- PHY_CC_CCA [4:0] ---------------------------------------------------- */
239
240219#define CHANNEL_SHIFT 0
241220#define CHANNEL_MASK 0x1f
242221
243/* --- CCA_THRES [3:0] ----------------------------------------------------- */
222/* --- CCA_THRES ----------------------------------------------------------- */
244223
245224#define CCA_ED_THRES_SHIFT 0
246225#define CCA_ED_THRES_MASK 0x0f
...... 
256235    IRQ_BAT_LOW = 1 << 7
257236};
258237
259/* --- VREG_CTRL [7, 6, 3, 2] ---------------------------------------------- */
238/* --- VREG_CTRL ----------------------------------------------------------- */
260239
261240#define AVREG_EXT (1 << 7)
262241#define AVDD_OK (1 << 6)
263242#define DVREG_EXT (1 << 3)
264243#define DVDD_OK (1 << 2)
265244
266/* --- BATMON [5, 4] ------------------------------------------------------- */
245/* --- BATMON -------------------------------------------------------------- */
267246
268247#define BATMON_OK (1 << 5)
269248#define BATMON_HR (1 << 4)
270249
271/* --- BATMON [3:0] -------------------------------------------------------- */
272
273250#define NATMON_VTH_SHIFT 0
274251#define NATMON_VTH_MASK 0x0f
275252
276/* --- XOSC_CTRL [7:4] ----------------------------------------------------- */
253/* --- XOSC_CTRL ----------------------------------------------------------- */
277254
278255#define XTAL_MODE_SHIFT 4
279256#define XTAL_MODE_MASK 0x0f
...... 
284261    XTAL_MODE_INT = 0xf /* reset default */
285262};
286263
287/* --- XOSC_CTRL [3:1] ----------------------------------------------------- */
288
289264#define XTAL_TRIM_SHIFT 4
290265#define XTAL_TRIM_MASK 0x0f
291266
292/* --- XAH_CTRL [7:4] ------------------------------------------------------ */
267/* --- XAH_CTRL ------------------------------------------------------------ */
293268
294269#define MAX_FRAME_RETRIES_SHIFT 4
295270#define MAX_FRAME_RETRIES_MASK 0x0f
271
296272#define MAX_CSMA_RETRIES_SHIFT 1
297273#define MAX_CSMA_RETRIES_MASK 0x07
298274
299/* --- PLL_CF [7] ---------------------------------------------------------- */
275/* --- PLL_CF -------------------------------------------------------------- */
300276
301277#define PLL_CF_START (1 << 7)
302278
303/* --- PLL_DCU [8] --------------------------------------------------------- */
279/* --- PLL_DCU ------------------------------------------------------------- */
304280
305281#define PLL_DCU_START (1 << 7)
306282
307/* --- CSMA_SEED_1 [7:6] --------------------------------------------------- */
283/* --- CSMA_SEED_1 --------------------------------------------------------- */
308284
309285#define MIN_BE_SHIFT 6
310286#define MIN_BE_MASK 3
311287
312/* --- CSMA_SEED_1 [5] ----------------------------------------------------- */
313
314288#define AACK_SET_PD (1 << 5)
315289
316/* --- CSMA_SEED_1 [3] ----------------------------------------------------- */
317
318290#define I_AM_COORD (1 << 3)
319291
320/* --- CSMA_SEED_1 [2:0] --------------------------------------------------- */
321
322292#define CSMA_SEED_1_SHIFT 0
323293#define CSMA_SEED_1_MASK 7
324294
325/* --- REG_CONT_TX_0 [7:0] ------------------------------------------------- */
295/* --- REG_CONT_TX_0 ------------------------------------------------------- */
326296
327297#define CONT_TX_MAGIC 0x0f
328298
329/* --- REG_CONT_TX_1 [7:0] ------------------------------------------------- */
299/* --- REG_CONT_TX_1 ------------------------------------------------------- */
330300
331301#define CONT_TX_MOD 0x00 /* modulated */
332302#define CONT_TX_M2M 0x10 /* f_CH-2 MHz */

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