Date:2011-05-27 23:37:40 (8 years 5 months ago)
Author:Werner Almesberger
Commit:c93f6d945ea17e61a74b466ced916ceb9a4e0497
Message:prod/doc/: added scope screen shots to analysis; show crystal as alt GND for clk

Files: prod/doc/Makefile (2 diffs)
prod/doc/analysis.hmac (5 diffs)
prod/doc/atben-clkm.png (0 diffs)
prod/doc/atben.fig (3 diffs)
prod/doc/atusb-clk.png (0 diffs)
prod/doc/atusb-clkm.png (0 diffs)

Change Details

prod/doc/Makefile
55      atben-A-small.png atusb-A-small.png \
66      atben-B-small.png atusb-B-small.png \
77      atrf-path-small.png
8ORIGINAL=atben-clkm.png atusb-clkm.png atusb-clk.png
89
910DL=http://downloads.qi-hardware.com/people/werner/wpan/tmp
1011
...... 
6162          atrf-path.png
6263        convert -scale 50% $< $@
6364
64upload: $(GENERATED) $(DOWNLOADS)
65upload: $(GENERATED) $(DOWNLOADED) $(ORIGINAL)
6566        rsync -e ssh $^ \
6667            www-data@downloads.qi-hardware.com:werner/wpan/prod/
6768
prod/doc/analysis.hmac
2424
2525<SECTION ref="orientation" title="Component orientation">
2626
27@@@
28
2729
2830<!-- ====================================================================== -->
2931
...... 
4244<P>
4345Voltages should be tested in the following order: USB, then I/O, then
4446digital, and finally analog. The table below gives the permissible
45ranges. Any voltages outside of these ranges indicate a problem.
47ranges. Any voltages outside these ranges indicate a problem.
4648<P>
4749<TABLE frame="border" cellpadding="2">
4850  <TR><TH>Domain<TH>Nominal<TH>Minimum<TH>Maximum
...... 
5153  <TR><TD>Digital<TD>1.8 V<TD>1.7 V<TD>1.9 V
5254  <TR><TD>Analog<TD>1.8 V<TD>1.7 V<TD>1.9 V
5355</TABLE>
54<P>
5556
5657
5758<!-- ---------------------------------------------------------------------- -->
...... 
170171This configures <B>atben</B> as a promiscuous receiver. The reception
171172of any IEEE 802.15.4 frame or pressing Ctrl-C will terminate the command.
172173<P>
173The clock signal (CLKM) is available on the test pad shown here:
174The clock signal (CLKM) is available on the test pad shown on the image
175on the left, and it should look roughly as shown in the screen shot on
176the right:
174177<P>
175<A href="atben-A.png"><IMG src="atben-A-small.png"></A>
178<A href="atben-A.png"><IMG src="atben-A-small.png" align="left"></A>
179&nbsp;
180<IMG src="atben-clkm.png">
176181<P>
177182<TABLE frame="border" cellpadding="2">
178183<TR><TH align="left">Clock<TH align="left">Action
...... 
201206a low-pass filter (CLK):
202207<P>
203208<A href="atusb-A.png"><IMG src="atusb-A-small.png"></A>
209&nbsp;
210<IMG src="atusb-clkm.png">
211&nbsp;
212<IMG src="atusb-clk.png">
213<P>
214The left screen shot shows the clock (CLKM) before the low-pass filter
215while the right screen shows the clock (CLK) after the the low-pass
216filter.
204217<P>
205218<TABLE frame="border" cellpadding="2">
206219<TR><TH align="left">Clock<TH align="left">Action
prod/doc/atben-clkm.png
prod/doc/atben.fig
30302 1 0 3 4 7 55 -1 -1 0.000 0 0 -1 1 0 2
3131    5 1 3.00 60.00 120.00
3232     1800 3735 2835 3735
33# B
33# AB
34342 1 0 3 0 7 55 -1 -1 0.000 0 0 -1 1 0 2
3535    5 1 3.00 60.00 120.00
3636     9225 3825 4725 3825
...... 
38382 1 0 3 4 7 55 -1 -1 0.000 0 0 -1 1 0 2
3939    5 1 3.00 60.00 120.00
4040     1800 4005 2835 4005
41# B
41# AB
42422 4 0 2 0 7 56 -1 15 0.000 0 0 7 0 0 5
4343     5040 4095 4590 4095 4590 3555 5040 3555 5040 4095
44442 2 0 0 0 7 99 -1 20 0.000 0 0 -1 0 0 5
...... 
49494 2 4 50 -1 18 24 0.0000 4 300 1200 1890 4725 CLKM\001
5050# B
51514 1 0 55 -1 18 24 0.0000 4 300 555 5625 1935 I/O\001
52# B
52# AB
53534 0 0 55 -1 18 24 0.0000 4 300 915 9315 3960 GND\001
5454# B
55554 1 0 55 -1 18 24 0.0000 4 390 1410 2880 1935 Analog\001
prod/doc/atusb-clk.png
prod/doc/atusb-clkm.png

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