Version 20100903: - changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be a bad trace. According to simulations, 22 pF should be more than enough. - added wire connecting uSD-side ground plane to ground plane at outer edge, to improve CLK signal return. (Probably unnecessary, too.) - the footprint of the transistor (Q1) is reversed :-( It works after converting the chip from SOT to PLCC. - not an erratum, but with experiments showing power-on reset to be reliable, we can consider removing the hardware reset circuit. This will also simplify the layout. Version 20100908: - SPI activity causes the PLL to unlock. Specifically, toggling nSEL does this.