IEEE 802.15.4 subsystem
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IEEE 802.15.4 subsystem Git Source Tree
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Source at commit 1fb05c221dcff657e49cc766e8ff7baa1d3434fc created 13 years 2 months ago. By Werner Almesberger, misctxrx.c (wait_for_interrupt): let "ignore" control printing more tightly | |
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1 | *** NEEDS UPDATING *** |
2 | |
3 | General |
4 | ======= |
5 | |
6 | Things not done yet |
7 | ------------------- |
8 | |
9 | - document directory hierarchy |
10 | |
11 | - make sure all files have a copyright header or are listed in AUTHORS |
12 | |
13 | - connect all the bits and pieces of the build system |
14 | |
15 | - combine io-parts.h generation |
16 | |
17 | - combine "standard" EP0 commands, such as *_ID and *_BUILD |
18 | |
19 | - implement return to DFU in application's EP0 protocol |
20 | |
21 | - consider removing *_ID and using bcdDevice instead |
22 | |
23 | |
24 | Bugs to fix |
25 | ----------- |
26 | |
27 | - builds fail if .version isn't there yet |
28 | |
29 | |
30 | |
31 | atrf |
32 | ==== |
33 | |
34 | AT86RF230-based IEEE 802.15.4 transceiver. Two variants: one to make a USB |
35 | dongle for use with any Linux host, and one that connects with SPI directly |
36 | inside a Ben. |
37 | |
38 | Update: following Rikard Lindstrom's revelation that we can use the uSD slot |
39 | also just as general GPIOs, the variant that goes inside the Ben can wait a |
40 | bit and the atben board for insertion into the uSD slot is being worked on |
41 | first. We can verify most of the design of a fully integrated board with the |
42 | atben board and the latter will be of greater immediate use. |
43 | |
44 | |
45 | Things done |
46 | ----------- |
47 | |
48 | - verify that the Ben can output an a) 16 MHz clock, and b) with +/- 40 ppm |
49 | |
50 | Done, see ecn/ecn0005.txt. Works fine. |
51 | |
52 | - replace discrete balun and filter with integrated solution, to reduce BOM |
53 | size, maybe cost, insertion loss, and PCB space (see ATRF/ECN0003) |
54 | |
55 | Done for atben. At a first glamce, does not seem to affect performance. |
56 | |
57 | - check if we really need three DC blocking caps in the RF path |
58 | |
59 | Reduced to two in atben without apparent ill effects. |
60 | |
61 | |
62 | Things not done yet |
63 | ------------------- |
64 | |
65 | - examine spectrum around carrier frequency and first harmonic to look for |
66 | obvious distortions. Vary transmit power. |
67 | |
68 | - measure throughput as a function of placement/distance, carrier frequency, |
69 | and transmit power |
70 | |
71 | - atrf-txrx: suppport "extended mode" with IEEE 802.15.4 CSMA-CA for more |
72 | realistic throughput figures |
73 | |
74 | - measure full spectrum (ideally up to 25 GHz, but just 2nd and 3rd harmonic |
75 | will already tell most of the story) with calibrated antenna for FCC/ETSI |
76 | compliance assessment. Vary transmit power. |
77 | |
78 | - use IEEE 802.15.4 stack from linux-zigbee. The linux-zigbee kernel is |
79 | currently at 2.6.35. Once 2.6.36 is released, we should have Ben and |
80 | IEEE 802.15.4 support in the same kernel without further ado. |
81 | |
82 | - change layout of transceiver side of the board for placement inside Ben |
83 | |
84 | - define EMI filters for placement inside Ben |
85 | |
86 | - check USB standard for recommended USB dongle dimensions |
87 | |
88 | - change layout for straight USB dongle |
89 | |
90 | - generate proper BOM |
91 | |
92 | - implement sleep mode |
93 | |
94 | - (atben) verify SPI signal timing, particularly the data clock |
95 | |
96 | |
97 | ccrf |
98 | ==== |
99 | |
100 | Board similar to the atrf, but with the TI/Chipcon CC2520. |
101 | |
102 | Cancelled. The CC2520 falls under US export restrictions, apparently because |
103 | it contains an AES engine. |
104 | |
105 | |
106 | cntr |
107 | ==== |
108 | |
109 | Simple USB-based counter to measure a clock's long-time accuracy with |
110 | arbitrarily high precision, by comparing it to an NTP time reference. |
111 | |
112 | |
113 | Things not done yet |
114 | ------------------- |
115 | |
116 | - measure duty cycle |
117 | |
118 | - use the LED to display activity on clock input and duty cycle |
119 | |
120 | - consider using a comparator and a DAC to allow for programmable logic levels |
121 | |
122 | - evaluate termination resistance |
123 | |
124 | - document circuit design |
125 | |
126 | - record beats between 16 bit counter polls and use them for the estimate |
127 | of lost cycles (2*1 is way too optimistic) |
128 | |
129 | - include system clock resolution in accuracy calculation |
130 | |
131 | - consider running shorter sliding windows to estimate drift |
132 | |
133 | - consider detecting unusual half-periods |
134 | |
135 | - consider using a reversed USB connector, to avoid having to cross D+/D- and, |
136 | worse, VBUS and GND |
137 | |
138 | - test input performance by counting a source that emits a known number of |
139 | cycles |
140 | |
141 | - consider using historical margins to sanity-check the current margin (if any |
142 | old.max < curr.min or old.min > curr.max, we have a problem) and to further |
143 | narrow the effective margin, thus achieving faster convergence. We would have |
144 | to consider temperature drift of the frequency source in this case. |
145 | |
146 | - find out why frequency measurements always seem to start high and then slowly |
147 | drop |
148 |