IEEE 802.15.4 subsystem
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IEEE 802.15.4 subsystem Git Source Tree
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Source at commit 2e5329039c2a4c9d131be003d3db703a938cfdfb created 13 years 6 days ago. By Werner Almesberger, include overview images in PCB and SMT fab packages | |
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1 | Board characteristics: |
2 | |
3 | - stacking: 2 layers, solder mask on front and back, silk screen on front |
4 | - board material: FR4, thickness 0.8 mm (1/32"), 1 oz copper |
5 | - surface finish: TBD, ENIG is preferred |
6 | - via holes: diameter is nominally 10 mil, but any size <= 15 mil can be used |
7 | - mechanical tolerances: <= +/- 0.1 mm on all sides |
8 | |
9 | |
10 | Layer stacking, from top to bottom: |
11 | |
12 | atusb-SilkS_Front.gto Front silk screen |
13 | atusb-Mask_Front.gts Front solder mask |
14 | atusb-Front.gtl Front copper |
15 | atusb-Back.gbl Back copper |
16 | atusb-Mask_Back.gbs Back solder mask |
17 | |
18 | |
19 | Other design files: |
20 | |
21 | atusb-front.png Illustration of the PCB's front side (without holes) |
22 | atusb-back.png idem, for the back side |
23 | atusb-PCB_Edges.gbr Board edges, for routing (Gerber) |
24 | atusb.dxf idem (AutoCAD DXF) |
25 | atusb.drl Excellon drill file |
26 | |
27 | |
28 | Interpretation of files: |
29 | |
30 | - for all coordinates, the origin is the lower left corner of the board |
31 | - do not print component values on silk screen |
32 | - the center (!) of the board edge line marks the true board edge, e.g., |
33 | |
34 | Edge line (5 mil) |
35 | ======= |
36 | ------- - - - - - ---------- |
37 | | | |
38 | PCB outside | | PCB inside |
39 | | | |
40 | ------- - - - - - ---------- |
41 | | |
42 | Volume removed when cutting |
43 | (width depends on tool used) |
44 |