Root/ecn/ecn0005.txt

Source at commit 49e7c83796bc04941e9dbcec69bc0751563ff4d4 created 2 years 2 months ago.
By Werner Almesberger, atusb/: use ""VDD" symbol from kicad-libs
1Correct atusd clock voltage divider
2
3
4According to section 9.6.3 of the data sheet, an external clock supplied
5to the AT86RF230 has a minimum peak-to-peak voltage of 400 mV and a
6maximum of only 500 mV. Furthermore, the signal must be DC-free.
7
8The voltage divider in the 20100903 and 20100908 designs is too sensitive
9to interference and the PLL constantly unlocks, rendering the device
10dysfunctional.
11
12A more robust divider circuit can be obtained with the following
13replacements: C7 -> 0R, R3 -> 33 pF, R4 -> 220 pF. After reworking the
1420100908 boards, they no longer suffer PLL unlocks.
15
16A Qucs simulation of the circuit can be found in ../atusd/sim/cdiv.sim
17
18Frequency measurements yield the following results:
19
20Host Board Error Meas. accuracy
21            (f, ppm) (ppm, nom.)
22------- --------------- --------------- ---------------
23Ben #2 20100908-A +2 99.7
24            +1 99.6
25Ben #1 20100908-A +23 99.7
26            +24 99.9
27Ben #1 20100908-B +24 99.4
28            +24 99.7
29Ben #2 20100908-B +2 99.8
30            +2 99.9
31
32The Ben's 12 MHz crystal has a tolerance of +/- 30 ppm, which is better
33than the +/- 40 ppm required by IEEE 802.15.4.
34
35What remains to be verified is whether this change causes interferences
36that may affect transceiver performance and may also violate emission
37regulations.
38

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