IEEE 802.15.4 subsystem
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Source at commit 695f6c2d57980e688c78cd3978779cfdccc468b7 created 13 years 13 days ago. By Werner Almesberger, atusb: use cptx to copy the version number to the silk screen | |
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1 | PLOT_BRD = pcbnew --plot=ps_a4 --ps-pads-drill-opt=none --fill-all-zones |
2 | CPTX = ../../eda-tools/mlztx/cptx |
3 | |
4 | NAME = atusb |
5 | VERSION = 110214 |
6 | DIR = $(NAME) |
7 | |
8 | .PHONY: all gen generate sch brd xpdf front back clean |
9 | .PHONY: gerber gerbv fab |
10 | |
11 | all: |
12 | @echo "make what ? target: gen sch brd xpdf front back clean" |
13 | @exit 1 |
14 | |
15 | gen generate: |
16 | eeschema --plot=ps `pwd`/$(NAME).sch |
17 | # need scripts |
18 | |
19 | sch: |
20 | eeschema `pwd`/$(NAME).sch |
21 | |
22 | brd: |
23 | pcbnew `pwd`/$(NAME).brd |
24 | |
25 | xpdf: |
26 | xpdf $(NAME).pdf |
27 | |
28 | front: $(NAME)-Front.ps |
29 | lpr $< |
30 | |
31 | back: $(NAME)-Back.ps |
32 | lpr $< |
33 | |
34 | cptx: |
35 | $(CPTX) -i $(NAME).brd 0 47000 48100 21 46811 40591 |
36 | |
37 | # --- DIY production (toner transfer) ----------------------------------------- |
38 | |
39 | # |
40 | # Postscript for production of front/back layer, using the toner transfer |
41 | # method. Note that other artwork transfer methods may require different |
42 | # mirror settings. |
43 | # |
44 | # We use --ps-pads-drill-opt=none to avoid having any hole before drilling, |
45 | # which yields the best results with a CNC drill. For manual drilling, "real" |
46 | # would be preferrable. Do not use "small", for this created holes that are |
47 | # larger (!) than designed. |
48 | # |
49 | |
50 | %-Front.ps: %.brd |
51 | $(PLOT_BRD) -l Front --mirror $< |
52 | |
53 | %-Back.ps: %.brd |
54 | $(PLOT_BRD) -l Back $< |
55 | |
56 | # --- Industrial production --------------------------------------------------- |
57 | |
58 | PCB_FILES = README-PCB $(NAME)-PCB_Edges.dxf $(NAME).drl \ |
59 | $(NAME)-SilkS_Front.gto $(NAME)-Mask_Front.gts \ |
60 | $(NAME)-Front.gtl $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs \ |
61 | $(NAME)-PCB_Edges.gbr |
62 | |
63 | gerber: |
64 | pcbnew --plot=gerber \ |
65 | -l `pcbnew --list-layers $(NAME).brd | tr '\012' ,` \ |
66 | --fill-all-zones $(NAME).brd \ |
67 | --exclude-pcb-edge |
68 | |
69 | fab: gerber |
70 | pcbnew --plot=dxf -l PCB_Edges $(NAME).brd |
71 | pcbnew --drill $(NAME).brd |
72 | tar Ccfz .. $(NAME)-pcb-$(VERSION).tar.gz \ |
73 | $(PCB_FILES:%=$(DIR)/%) |
74 | cd ..; zip -l $(DIR)/$(NAME)-pcb-$(VERSION).zip \ |
75 | $(PCB_FILES:%=$(DIR)/%) |
76 | |
77 | gerbv: |
78 | gerbv $(NAME)-Comments.gbr \ |
79 | $(NAME)-SilkS_Front.gto \ |
80 | $(NAME)-SoldP_Front.gtp \ |
81 | $(NAME)-Front.gtl \ |
82 | $(NAME)-Mask_Front.gts \ |
83 | $(NAME)-Back.gbl |
84 | |
85 | upload: |
86 | qippl $(NAME)-pcb-$(VERSION).tar.gz \ |
87 | $(NAME)-pcb-$(VERSION).zip wpan/fab |
88 | |
89 | # --- Cleanup ----------------------------------------------------------------- |
90 | |
91 | clean: |
92 | rm -f $(NAME)-Front.ps $(NAME)-Back.ps |
93 | rm -f $(NAME).drl $(NAME)-PCB_Edges.gbr $(NAME)-PCB_Edges.dxf |
94 | rm -f $(NAME)-Front.gtl $(NAME)-Mask_Front.gts |
95 | rm -f $(NAME)-SilkS_Front.gto $(NAME)-SoldP_Front.gtp |
96 | rm -f $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs |
97 | rm -f $(NAME)-SilkS_Back.gbo $(NAME)-SoldP_Back.gbp |
98 | rm -f $(NAME)-Comments.gbr |
99 |