Root/atusd/ERRATA

Source at commit 6e726d1fb90ec8f182984a426ea05b15b5adc3b8 created 13 years 6 months ago.
By Werner Almesberger, Improved clock stability by using a capacitative divider and found more minor issues.
1Version 20100903:
2
3- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
4  a bad trace. According to simulations, 22 pF should be more than enough.
5
6- added wire connecting uSD-side ground plane to ground plane at outer edge,
7  to improve CLK signal return. (Probably unnecessary, too.)
8
9- the footprint of the transistor (Q1) is reversed :-( It works after
10  converting the chip from SOT to PLCC.
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12- not an erratum, but with experiments showing power-on reset to be
13  reliable, we can consider removing the hardware reset circuit. This will
14  also simplify the layout.
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16Version 20100908:
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18- SPI activity causes the PLL to unlock. Specifically, toggling nSEL does
19  this.
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21- work-around on second 20100908 board: replace the resistive divider with
22  a capacitative divider. See sim/cdiv.sch. This is a simple BOM change:
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24  C7 -> 0 R
25  R3 -> 33 pF
26  R4 -> 220 pF
27
28- considering that the clock input has a Vpp of only 400-500 mV, we should
29  have a ground plane also under as much of the the clock circuit as
30  possible.
31
32- via between pins 1 and 32 is too close to the chip for DIY PCBs
33

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