Root/atusd/ERRATA

Source at commit 86e556ce92af39a3353e0c6494ba20de59d47d4c created 10 years 20 days ago.
By Werner Almesberger, First part of the board bringup: power and clock.
1- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
2  a bad trace. According to simulations, 22 pF should be more than enough.
3
4- added wire connecting uSD-side ground plane to ground plane at outer edge,
5  to improve CLK signal return. (Probably unnecessary, too.)
6

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