IEEE 802.15.4 subsystem
Sign in or create your account | Project List | Help
IEEE 802.15.4 subsystem Git Source Tree
Root/
Source at commit 9c64024af55259eb27fe2d86aa8e26257c996342 created 7 years 4 months ago. By Stefan Schmidt, atusb/Makefile: add missing atusb back layer to upload target | |
---|---|
1 | Board characteristics: |
2 | |
3 | - stacking: 2 layers, solder mask on front and back, silk screen on front |
4 | - board material: FR4, thickness 0.8 mm (1/32"), 1 oz copper |
5 | - surface finish: TBD, ENIG is preferred |
6 | - via holes: diameter is nominally 10 mil, but any size <= 15 mil can be used |
7 | - ground via of the antenna: hole diameter is nominally 8 mil, but any size |
8 | <= 15 mil can be used |
9 | - mechanical tolerances: <= +/- 0.1 mm on all sides |
10 | - the holes for the positioning pins of the USB connector have a nominal |
11 | diameter of 1.15 mm. The minimum finished hole size must be 1.10 mm, |
12 | maximum 1.25 mm. |
13 | |
14 | |
15 | Hole for the USB connector: |
16 | |
17 | The USB connector extends below (!) the surface of the PCB. For SMT, a |
18 | 16-17 mm hole must be left next to the PCB's edge: |
19 | |
20 | <-17mm-> |
21 | +------+-------------+ |
22 | | |- | |
23 | | Hole | PCB | |
24 | | |- | |
25 | +------+-------------+ |
26 | |
27 | For illustration: |
28 | http://downloads.qi-hardware.com/people/werner/wpan/tmp/usb-off-board.jpg |
29 | |
30 | |
31 | Layer stacking, from top to bottom: |
32 | |
33 | atusb-SilkS_Front.gto Front silk screen |
34 | atusb-Mask_Front.gts Front solder mask |
35 | atusb-Front.gtl Front copper |
36 | atusb-Back.gbl Back copper |
37 | atusb-Mask_Back.gbs Back solder mask |
38 | |
39 | |
40 | Other design files: |
41 | |
42 | atusb-front.png Illustration of the PCB's front side |
43 | atusb-back.png idem, for the back side |
44 | atusb-PCB_Edges.gbr Board edges, for routing (Gerber) |
45 | atusb.dxf idem (AutoCAD DXF) |
46 | atusb.drl Excellon drill file |
47 | atusb-SoldP_Front.gtp Front solder paste, for stencil |
48 | |
49 | |
50 | Interpretation of files: |
51 | |
52 | - for all coordinates, the origin is the lower left corner of the board |
53 | - do not print component values on silk screen |
54 | - the center (!) of the board edge line marks the true board edge, e.g., |
55 | |
56 | Edge line (5 mil) |
57 | ======= |
58 | ------- - - - - - ---------- |
59 | | | |
60 | PCB outside | | PCB inside |
61 | | | |
62 | ------- - - - - - ---------- |
63 | | |
64 | Volume removed when cutting |
65 | (width depends on tool used) |
66 |