Root/atusd/ERRATA

Source at commit a18d5969bd1582a6bc4623cdd0ee3d19b74d8627 created 13 years 6 months ago.
By Werner Almesberger, Next part of board bringup: reset and power cycling.
1- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
2  a bad trace. According to simulations, 22 pF should be more than enough.
3
4- added wire connecting uSD-side ground plane to ground plane at outer edge,
5  to improve CLK signal return. (Probably unnecessary, too.)
6
7- the footprint of the transistor (Q1) is reversed :-( It works after
8  converting the chip from SOT to PLCC.
9

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