IEEE 802.15.4 subsystem
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Source at commit bd5b008c44baf01201efd8a8dc3b429f2925dd76 created 13 years 2 months ago. By Werner Almesberger, atusb/fw/include/at86rf230.h: make one section per register, not one per field | |
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1 | /* |
2 | * include/at86rf230.h - AT86RF230/AT86RF231 protocol and register definitions |
3 | * |
4 | * Written 2008-2011 by Werner Almesberger |
5 | * Copyright 2008-2011 Werner Almesberger |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by |
9 | * the Free Software Foundation; either version 2 of the License, or |
10 | * (at your option) any later version. |
11 | */ |
12 | |
13 | |
14 | #ifndef AT86RF230_H |
15 | #define AT86RF230_H |
16 | |
17 | enum { |
18 | AT86RF230_REG_WRITE = 0xc0, /* 11... */ |
19 | AT86RF230_REG_READ = 0x80, /* 10... */ |
20 | AT86RF230_BUF_WRITE = 0x60, /* 011... */ |
21 | AT86RF230_BUF_READ = 0x20, /* 001... */ |
22 | AT86RF230_SRAM_WRITE = 0x40, /* 010... */ |
23 | AT86RF230_SRAM_READ = 0x00 /* 000... */ |
24 | }; |
25 | |
26 | #define MAX_PSDU 127 /* octets, see AT86RF230 manual section 8.1 */ |
27 | #define SRAM_SIZE 128 |
28 | |
29 | |
30 | /* --- Registers ----------------------------------------------------------- */ |
31 | |
32 | enum { |
33 | REG_TRX_STATUS = 0x01, |
34 | REG_TRX_STATE = 0x02, |
35 | REG_TRX_CTRL_0 = 0x03, |
36 | |
37 | REG_TRX_CTRL_1 = 0x04, /* 231 only */ |
38 | |
39 | REG_PHY_TX_PWR = 0x05, |
40 | REG_PHY_RSSI = 0x06, |
41 | REG_PHY_ED_LEVEL = 0x07, |
42 | REG_PHY_CC_CCA = 0x08, |
43 | REG_CCA_THRES = 0x09, |
44 | |
45 | REG_RX_CTRL = 0x0a, /* 231 only */ |
46 | REG_SFD_VALUE = 0x0b, /* 231 only */ |
47 | REG_TRX_CTRL_2 = 0x0c, /* 231 only */ |
48 | REG_ANT_DIV = 0x0d, /* 231 only */ |
49 | |
50 | REG_IRQ_MASK = 0x0e, |
51 | REG_IRQ_STATUS = 0x0f, |
52 | REG_VREG_CTRL = 0x10, |
53 | REG_BATMON = 0x10, |
54 | REG_XOSC_CTRL = 0x12, |
55 | |
56 | REG_RX_SYN = 0x15, /* 231 only */ |
57 | REG_XAH_CTRL_1 = 0x17, /* 231 only */ |
58 | REG_FTN_CTRL = 0x18, /* 231 only */ |
59 | |
60 | REG_PLL_CF = 0x1a, |
61 | REL_PLL_DCU = 0x1b, |
62 | REG_PART_NUM = 0x1c, |
63 | REG_VERSION_NUM = 0x1d, |
64 | REG_MAN_ID_0 = 0x1e, |
65 | REG_MAN_ID_1 = 0x1f, |
66 | REG_SHORT_ADDR_0 = 0x20, |
67 | REG_SHORT_ADDR_1 = 0x21, |
68 | REG_PAN_ID_0 = 0x22, |
69 | REG_PAN_ID_1 = 0x23, |
70 | REG_IEEE_ADDR_0 = 0x24, |
71 | REG_IEEE_ADDR_1 = 0x25, |
72 | REG_IEEE_ADDR_2 = 0x26, |
73 | REG_IEEE_ADDR_3 = 0x27, |
74 | REG_IEEE_ADDR_4 = 0x28, |
75 | REG_IEEE_ADDR_5 = 0x29, |
76 | REG_IEEE_ADDR_6 = 0x2a, |
77 | REG_IEEE_ADDR_7 = 0x2b, |
78 | |
79 | REG_XAH_CTRL_0 = 0x2c, /* XAH_CTRL in 230 */ |
80 | REG_CSMA_SEED_0 = 0x2d, |
81 | REG_CSMA_SEED_1 = 0x2e, |
82 | REG_CSMA_BE = 0x2f, /* 231 only */ |
83 | |
84 | REG_CONT_TX_0 = 0x36, |
85 | REG_CONT_TX_1 = 0x3d, |
86 | }; |
87 | |
88 | /* --- TRX_STATUS --- ------------------------------------------------------ */ |
89 | |
90 | #define CCA_DONE (1 << 7) |
91 | #define CCA_STATUS (1 << 6) |
92 | |
93 | #define TRX_STATUS_SHIFT 0 |
94 | #define TRX_STATUS_MASK 0x1f |
95 | |
96 | enum { |
97 | TRX_STATUS_P_ON = 0x00, /* reset default */ |
98 | TRX_STATUS_BUSY_RX = 0x01, |
99 | TRX_STATUS_BUSY_TX = 0x02, |
100 | TRX_STATUS_RX_ON = 0x06, |
101 | TRX_STATUS_TRX_OFF = 0x08, |
102 | TRX_STATUS_PLL_ON = 0x09, |
103 | TRX_STATUS_SLEEP = 0x0f, |
104 | TRX_STATUS_BUSY_RX_AACK = 0x11, |
105 | TRX_STATUS_BUSY_TX_ARET = 0x12, |
106 | TRX_STATUS_RX_AACK_ON = 0x16, |
107 | TRX_STATUS_TX_ARET_ON = 0x19, |
108 | TRX_STATUS_RX_ON_NOCLK = 0x1c, |
109 | TRX_STATUS_RX_AACK_ON_NOCLK = 0x1d, |
110 | TRX_STATUS_BUSY_RX_AACK_NOCLK = 0x1e, |
111 | TRX_STATUS_TRANSITION = 0x1f /* ..._IN_PROGRESS */ |
112 | }; |
113 | |
114 | /* --- TRX_STATE ----------------------------------------------------------- */ |
115 | |
116 | #define TRAC_STATUS_SHIFT 5 |
117 | #define TRAC_STATUS_MASK 7 |
118 | |
119 | enum { |
120 | TRAC_STATUS_SUCCESS = 0, /* reset default */ |
121 | TRAC_STATUS_SUCCESS_DATA_PENDING = 1, |
122 | TRAC_STATUS_SUCCESS_WAIT_FOR_ACK = 2, /* 231 only */ |
123 | TRAC_STATUS_CHANNEL_ACCESS_FAILURE = 3, |
124 | TRAC_STATUS_NO_ACK = 5, |
125 | TRAC_STATUS_INVALID = 7 |
126 | }; |
127 | |
128 | #define TRX_CMD_SHIFT 0 |
129 | #define TRX_CMD_MASK 7 |
130 | |
131 | enum { |
132 | TRX_CMD_NOP = 0x00, /* reset default */ |
133 | TRX_CMD_TX_START = 0x02, |
134 | TRX_CMD_FORCE_TRX_OFF = 0x03, |
135 | TRX_CMD_FORCE_PLL_ON = 0x04, /* 231 only */ |
136 | TRX_CMD_RX_ON = 0x06, |
137 | TRX_CMD_TRX_OFF = 0x08, |
138 | TRX_CMD_PLL_ON = 0x09, |
139 | TRX_CMD_RX_AACK_ON = 0x16, |
140 | TRX_CMD_TX_ARET_ON = 0x19, |
141 | }; |
142 | |
143 | /* --- TRX_CTRL_0 ---------------------------------------------------------- */ |
144 | |
145 | #define PAD_IO_SHIFT 6 |
146 | #define PAD_IO_MASK 3 |
147 | |
148 | enum { |
149 | PAD_IO_2mA, /* reset default */ |
150 | PAD_IO_4mA, |
151 | PAD_IO_6mA, |
152 | PAD_IO_8mA |
153 | }; |
154 | |
155 | #define PAD_IO_CLKM_SHIFT 4 |
156 | #define PAD_IO_CLKM_MASK 3 |
157 | |
158 | enum { |
159 | PAD_IO_CLKM_2mA, |
160 | PAD_IO_CLKM_4mA, /* reset default */ |
161 | PAD_IO_CLKM_5mA, |
162 | PAD_IO_CLKM_8mA, |
163 | }; |
164 | |
165 | #define CLKM_SHA_SEL (1 << 3) |
166 | |
167 | #define CLKM_CTRL_SHIFT 0 |
168 | #define CLKM_CTRL_MASK 3 |
169 | |
170 | enum { |
171 | CLKM_CTRL_OFF = 0, |
172 | CLKM_CTRL_1MHz = 1, /* reset default */ |
173 | CLKM_CTRL_2MHz = 2, |
174 | CLKM_CTRL_4MHz = 3, |
175 | CLKM_CTRL_8MHz = 4, |
176 | CLKM_CTRL_16MHz = 5 |
177 | }; |
178 | |
179 | /* --- TRX_CTRL_1 (231 only) ----------------------------------------------- */ |
180 | |
181 | #define PA_EXT_EN (1 << 8) |
182 | #define IRQ_2_EXT_EN (1 << 7) |
183 | #define TX_AUTO_CRC_ON_231 (1 << 6) /* 231 */ |
184 | |
185 | #define SPI_CMD_MODE_SHIFT 2 |
186 | #define SPI_CMD_MODE_MASK 3 |
187 | |
188 | enum { |
189 | SPI_CMD_MODE_EMPTY = 0, /* reset default */ |
190 | SPI_CMD_MODE_TRX_STATUS = 1, |
191 | SPI_CMD_MODE_PHY_RSSI = 2, |
192 | SPI_CMD_MODE_IRQ_STATUS = 3, |
193 | }; |
194 | |
195 | #define IRQ_MASK_MODE (1 << 1) |
196 | #define IRQ_POLARITY (1 << 0) |
197 | |
198 | /* --- PHY_TX_PWR -====----------------------------------------------------- */ |
199 | |
200 | #define TX_AUTO_CRC_ON (1 << 7) /* 230 */ |
201 | |
202 | #define TX_PWR_SHIFT 0 |
203 | #define TX_PWR_MASK 0x0f |
204 | |
205 | /* --- PHY_RSSI ------------------------------------------------------------ */ |
206 | |
207 | #define RX_CRC_VALID (1 << 7) |
208 | |
209 | #define RSSI_SHIFT 0 |
210 | #define RSSI_MASK 0x1f |
211 | |
212 | /* --- PHY_CC_CCA ---------------------------------------------------------- */ |
213 | |
214 | #define CCA_REQUEST (1 << 7) |
215 | |
216 | #define CCA_MODE_SHIFT 5 |
217 | #define CCA_MODE_MASK 3 |
218 | |
219 | #define CHANNEL_SHIFT 0 |
220 | #define CHANNEL_MASK 0x1f |
221 | |
222 | /* --- CCA_THRES ----------------------------------------------------------- */ |
223 | |
224 | #define CCA_ED_THRES_SHIFT 0 |
225 | #define CCA_ED_THRES_MASK 0x0f |
226 | |
227 | /* --- IRQ_MASK/IRQ_STATUS ------------------------------------------------- */ |
228 | |
229 | enum { |
230 | IRQ_PLL_LOCK = 1 << 0, |
231 | IRQ_PLL_UNLOCK = 1 << 1, |
232 | IRQ_RX_START = 1 << 2, |
233 | IRQ_TRX_END = 1 << 3, |
234 | IRQ_TRX_UR = 1 << 6, |
235 | IRQ_BAT_LOW = 1 << 7 |
236 | }; |
237 | |
238 | /* --- VREG_CTRL ----------------------------------------------------------- */ |
239 | |
240 | #define AVREG_EXT (1 << 7) |
241 | #define AVDD_OK (1 << 6) |
242 | #define DVREG_EXT (1 << 3) |
243 | #define DVDD_OK (1 << 2) |
244 | |
245 | /* --- BATMON -------------------------------------------------------------- */ |
246 | |
247 | #define BATMON_OK (1 << 5) |
248 | #define BATMON_HR (1 << 4) |
249 | |
250 | #define NATMON_VTH_SHIFT 0 |
251 | #define NATMON_VTH_MASK 0x0f |
252 | |
253 | /* --- XOSC_CTRL ----------------------------------------------------------- */ |
254 | |
255 | #define XTAL_MODE_SHIFT 4 |
256 | #define XTAL_MODE_MASK 0x0f |
257 | |
258 | enum { |
259 | XTAL_MODE_OFF = 0x0, |
260 | XTAL_MODE_EXT = 0x4, |
261 | XTAL_MODE_INT = 0xf /* reset default */ |
262 | }; |
263 | |
264 | #define XTAL_TRIM_SHIFT 4 |
265 | #define XTAL_TRIM_MASK 0x0f |
266 | |
267 | /* --- XAH_CTRL ------------------------------------------------------------ */ |
268 | |
269 | #define MAX_FRAME_RETRIES_SHIFT 4 |
270 | #define MAX_FRAME_RETRIES_MASK 0x0f |
271 | |
272 | #define MAX_CSMA_RETRIES_SHIFT 1 |
273 | #define MAX_CSMA_RETRIES_MASK 0x07 |
274 | |
275 | /* --- PLL_CF -------------------------------------------------------------- */ |
276 | |
277 | #define PLL_CF_START (1 << 7) |
278 | |
279 | /* --- PLL_DCU ------------------------------------------------------------- */ |
280 | |
281 | #define PLL_DCU_START (1 << 7) |
282 | |
283 | /* --- CSMA_SEED_1 --------------------------------------------------------- */ |
284 | |
285 | #define MIN_BE_SHIFT 6 |
286 | #define MIN_BE_MASK 3 |
287 | |
288 | #define AACK_SET_PD (1 << 5) |
289 | |
290 | #define I_AM_COORD (1 << 3) |
291 | |
292 | #define CSMA_SEED_1_SHIFT 0 |
293 | #define CSMA_SEED_1_MASK 7 |
294 | |
295 | /* --- REG_CONT_TX_0 ------------------------------------------------------- */ |
296 | |
297 | #define CONT_TX_MAGIC 0x0f |
298 | |
299 | /* --- REG_CONT_TX_1 ------------------------------------------------------- */ |
300 | |
301 | #define CONT_TX_MOD 0x00 /* modulated */ |
302 | #define CONT_TX_M2M 0x10 /* f_CH-2 MHz */ |
303 | #define CONT_TX_M500K 0x80 /* f_CH-0.5 MHz */ |
304 | #define CONT_TX_P500K 0xc0 /* f_CH+0.5 MHz */ |
305 | |
306 | #endif /* !AT86RF230_H */ |
307 |