Root/atrf/fw/include/at86rf230.h

Source at commit c2dd23840ce5875deca09673fcb8abb8dc3a8e7a created 9 years 1 month ago.
By Werner Almesberger, Moved fw/ and tools/ into atrf/ as well.
1/*
2 * include/at86rf230.h - AT86RF230 protocol and register definitions
3 *
4 * Written 2008-2010 by Werner Almesberger
5 * Copyright 2008-2010 Werner Almesberger
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13
14#ifndef AT86RF230_H
15#define AT86RF230_H
16
17enum {
18    AT86RF230_REG_WRITE = 0xc0, /* 11... */
19    AT86RF230_REG_READ = 0x80, /* 10... */
20    AT86RF230_BUF_WRITE = 0x60, /* 011... */
21    AT86RF230_BUF_READ = 0x20, /* 001... */
22    AT86RF230_SRAM_WRITE = 0x40, /* 010... */
23    AT86RF230_SRAM_READ = 0x00 /* 000... */
24};
25
26#define MAX_PSDU 127 /* octets, see AT86RF230 manual section 8.1 */
27#define SRAM_SIZE 128
28
29
30/* --- Registers ----------------------------------------------------------- */
31
32enum {
33    REG_TRX_STATUS = 0x01,
34    REG_TRX_STATE = 0x02,
35    REG_TRX_CTRL_0 = 0x03,
36
37    REG_TR_PWR = 0x05,
38    REG_PHY_RSSI = 0x06,
39    REG_PHY_ED_LEVEL = 0x07,
40    REG_PHY_CC_CCA = 0x08,
41    REG_CCA_THRES = 0x09,
42
43    REG_IRQ_MASK = 0x0e,
44    REG_IRQ_STATUS = 0x0f,
45    REG_VREG_CTRL = 0x10,
46    REG_BATMON = 0x10,
47    REG_XOSC_CTRL = 0x12,
48
49    REG_PLL_CF = 0x1a,
50    REL_PLL_DCU = 0x1b,
51    REG_PART_NUM = 0x1c,
52    REG_VERSION_NUM = 0x1d,
53    REG_MAN_ID_0 = 0x1e,
54    REG_MAN_ID_1 = 0x1f,
55    REG_SHORT_ADDR_0 = 0x20,
56    REG_SHORT_ADDR_1 = 0x21,
57    REG_PAN_ID_0 = 0x22,
58    REG_PAN_ID_1 = 0x23,
59    REG_IEEE_ADDR_0 = 0x24,
60    REG_IEEE_ADDR_1 = 0x25,
61    REG_IEEE_ADDR_2 = 0x26,
62    REG_IEEE_ADDR_3 = 0x27,
63    REG_IEEE_ADDR_4 = 0x28,
64    REG_IEEE_ADDR_5 = 0x29,
65    REG_IEEE_ADDR_6 = 0x2a,
66    REG_IEEE_ADDR_7 = 0x2b,
67    REG_XAH_CTRL = 0x2c,
68    REG_CSMA_SEED_0 = 0x2d,
69    REG_CSMA_SEED_1 = 0x2e,
70};
71
72/* --- TRX_STATUS [7] ------------------------------------------------------ */
73
74#define CCA_DONE (1 << 7)
75
76/* --- TRX_STATUS [6] ------------------------------------------------------ */
77
78#define CCA_STATUS (1 << 6)
79
80/* --- TRX_STATUS [4:0] ---------------------------------------------------- */
81
82#define TRX_STATUS_SHIFT 0
83#define TRX_STATUS_MASK 0x0f
84
85enum {
86    TRX_STATUS_P_ON = 0x00, /* reset default */
87    TRX_STATUS_BUSY_RX = 0x01,
88    TRX_STATUS_BUSY_TX = 0x02,
89    TRX_STATUS_RX_ON = 0x06,
90    TRX_STATUS_TRX_OFF = 0x08,
91    TRX_STATUS_PLL_ON = 0x09,
92    TRX_STATUS_SLEEP = 0x0f,
93    TRX_STATUS_BUSY_RX_AACK = 0x11,
94    TRX_STATUS_BUSY_TX_ARET = 0x12,
95    TRX_STATUS_RX_AACK_ON = 0x16,
96    TRX_STATUS_TX_ARET_ON = 0x19,
97    TRX_STATUS_RX_ON_NOCLK = 0x1c,
98    TRX_STATUS_RX_AACK_ON_NOCLK = 0x1d,
99    TRX_STATUS_BUSY_RX_AACK_NOCLK = 0x1e,
100    TRX_STATUS_TRANSITION = 0x1f
101};
102
103/* --- TRX_STATE [7:5] ----------------------------------------------------- */
104
105#define TRAC_STATUS_SHIFT 5
106#define TRAC_STATUS_MASK 7
107
108enum {
109    TRAC_STATUS_SUCCESS = 0, /* reset default */
110    TRAC_STATUS_SUCCESS_DATA_PENDING = 1,
111    TRAC_STATUS_CHANNEL_ACCESS_FAILURE = 3,
112    TRAC_STATUS_NO_ACK = 5,
113    TRAC_STATUS_INVALID = 7
114};
115
116/* --- TRX_CMD [4:0] ----------------------------------------------------- */
117
118#define TRX_CMD_SHIFT 0
119#define TRX_CMD_MASK 7
120
121enum {
122    TRX_CMD_NOP = 0x00, /* reset default */
123    TRX_CMD_TX_START = 0x02,
124    TRX_CMD_FORCE_TRX_OFF = 0x03,
125    TRX_CMD_RX_ON = 0x06,
126    TRX_CMD_TRX_OFF = 0x08,
127    TRX_CMD_PLL_ON = 0x09,
128    TRX_CMD_RX_AACK_ON = 0x16,
129    TRX_CMD_TX_ARET_ON = 0x19,
130};
131
132/* --- TRX_CTRL_0 [7:6] ---------------------------------------------------- */
133
134#define PAD_IO_SHIFT 6
135#define PAD_IO_MASK 3
136
137enum {
138    PAD_IO_2mA, /* reset default */
139    PAD_IO_4mA,
140    PAD_IO_6mA,
141    PAD_IO_8mA
142};
143
144/* --- TRX_CTRL_0 [5:4] ---------------------------------------------------- */
145
146#define PAD_IO_CLKM_SHIFT 4
147#define PAD_IO_CLKM_MASK 3
148
149enum {
150    PAD_IO_CLKM_2mA,
151    PAD_IO_CLKM_4mA, /* reset default */
152    PAD_IO_CLKM_5mA,
153    PAD_IO_CLKM_8mA,
154};
155
156/* --- TRX_CTRL_0 [3] ------------------------------------------------------ */
157
158#define CLKM_SHA_SEL (1 << 3)
159
160/* --- TRX_CTRL_0 [2:0] ---------------------------------------------------- */
161
162#define CLKM_CTRL_SHIFT 0
163#define CLKM_CTRL_MASK 3
164
165enum {
166    CLKM_CTRL_OFF = 0,
167    CLKM_CTRL_1MHz = 1, /* reset default */
168    CLKM_CTRL_2MHz = 2,
169    CLKM_CTRL_4MHz = 3,
170    CLKM_CTRL_8MHz = 4,
171    CLKM_CTRL_16MHz = 5
172};
173
174/* --- PHY_TX_PWR [7] ------------------------------------------------------ */
175
176#define TX_AUTO_CRC_ON (1 << 7)
177
178/* --- PHY_TX_PWR [3:0] ---------------------------------------------------- */
179
180#define TX_PWR_SHIFT 0
181#define TX_PWR_MASK 0x0f
182
183/* --- PHY_RSSI [7] -------------------------------------------------------- */
184
185#define RX_CRC_VALID (1 << 7)
186
187/* --- PHY_RSSI [4:0] ------------------------------------------------------ */
188
189#define RSSI_SHIFT 0
190#define RSSI_MASK 0x1f
191
192/* --- PHY_CC_CCA [7] ------------------------------------------------------ */
193
194#define CCA_REQUEST (1 << 7)
195
196/* --- PHY_CC_CCA [6:5] ---------------------------------------------------- */
197
198#define CCA_MODE_SHIFT 5
199#define CCA_MODE_MASK 3
200
201/* --- PHY_CC_CCA [4:0] ---------------------------------------------------- */
202
203#define CHANNEL_SHIFT 0
204#define CHANNEL_MASK 0x1f
205
206/* --- CCA_THRES [3:0] ----------------------------------------------------- */
207
208#define CCA_ED_THRES_SHIFT 0
209#define CCA_ED_THRES_MASK 0x0f
210
211/* --- IRQ_MASK/IRQ_STATUS ------------------------------------------------- */
212
213enum {
214    IRQ_PLL_LOCK = 1 << 0,
215    IRQ_PLL_UNLOCK = 1 << 1,
216    IRQ_RX_START = 1 << 2,
217    IRQ_TRX_END = 1 << 3,
218    IRQ_TRX_UR = 1 << 6,
219    IRQ_BAT_LOW = 1 << 7
220};
221
222/* --- VREG_CTRL [7, 6, 3, 2] ---------------------------------------------- */
223
224#define AVREG_EXT (1 << 7)
225#define AVDD_OK (1 << 6)
226#define DVREG_EXT (1 << 3)
227#define DVDD_OK (1 << 2)
228
229/* --- BATMON [5, 4] ------------------------------------------------------- */
230
231#define BATMON_OK (1 << 5)
232#define BATMON_HR (1 << 4)
233
234/* --- BATMON [3:0] -------------------------------------------------------- */
235
236#define NATMON_VTH_SHIFT 0
237#define NATMON_VTH_MASK 0x0f
238
239/* --- XOSC_CTRL [7:4] ----------------------------------------------------- */
240
241#define XTAL_MODE_SHIFT 4
242#define XTAL_MODE_MASK 0x0f
243
244enum {
245    XTAL_MODE_OFF = 0x0,
246    XTAL_MODE_EXT = 0x4,
247    XTAL_MODE_INT = 0xf /* reset default */
248};
249
250/* --- XOSC_CTRL [3:1] ----------------------------------------------------- */
251
252#define XTAL_TRIM_SHIFT 4
253#define XTAL_TRIM_MASK 0x0f
254
255/* --- XAH_CTRL [7:4] ------------------------------------------------------ */
256
257#define MAX_FRAME_RETRIES_SHIFT 4
258#define MAX_FRAME_RETRIES_MASK 0x0f
259#define MAX_CSMA_RETRIES_SHIFT 1
260#define MAX_CSMA_RETRIES_MASK 0x07
261
262/* --- PLL_CF [7] ---------------------------------------------------------- */
263
264#define PLL_CF_START (1 << 7)
265
266/* --- PLL_DCU [8] --------------------------------------------------------- */
267
268#define PLL_DCU_START (1 << 7)
269
270/* --- CSMA_SEED_1 [7:6] --------------------------------------------------- */
271
272#define MIN_BE_SHIFT 6
273#define MIN_BE_MASK 3
274
275/* --- CSMA_SEED_1 [5] ----------------------------------------------------- */
276
277#define AACK_SET_PD (1 << 5)
278
279/* --- CSMA_SEED_1 [3] ----------------------------------------------------- */
280
281#define I_AM_COORD (1 << 3)
282
283/* --- CSMA_SEED_1 [2:0] --------------------------------------------------- */
284
285#define CSMA_SEED_1_SHIFT 0
286#define CSMA_SEED_1_MASK 7
287
288#endif /* !AT86RF230_H */
289

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