IEEE 802.15.4 subsystem
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Source at commit d4fe0277c28563f870334b68dde373751ace8197 created 13 years 4 months ago. By Werner Almesberger, atspi-txrx: option -T <delta_MHz> to emit a constant wave | |
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1 | /* |
2 | * include/at86rf230.h - AT86RF230 protocol and register definitions |
3 | * |
4 | * Written 2008-2010 by Werner Almesberger |
5 | * Copyright 2008-2010 Werner Almesberger |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by |
9 | * the Free Software Foundation; either version 2 of the License, or |
10 | * (at your option) any later version. |
11 | */ |
12 | |
13 | |
14 | #ifndef AT86RF230_H |
15 | #define AT86RF230_H |
16 | |
17 | enum { |
18 | AT86RF230_REG_WRITE = 0xc0, /* 11... */ |
19 | AT86RF230_REG_READ = 0x80, /* 10... */ |
20 | AT86RF230_BUF_WRITE = 0x60, /* 011... */ |
21 | AT86RF230_BUF_READ = 0x20, /* 001... */ |
22 | AT86RF230_SRAM_WRITE = 0x40, /* 010... */ |
23 | AT86RF230_SRAM_READ = 0x00 /* 000... */ |
24 | }; |
25 | |
26 | #define MAX_PSDU 127 /* octets, see AT86RF230 manual section 8.1 */ |
27 | #define SRAM_SIZE 128 |
28 | |
29 | |
30 | /* --- Registers ----------------------------------------------------------- */ |
31 | |
32 | enum { |
33 | REG_TRX_STATUS = 0x01, |
34 | REG_TRX_STATE = 0x02, |
35 | REG_TRX_CTRL_0 = 0x03, |
36 | |
37 | REG_PHY_TX_PWR = 0x05, |
38 | REG_PHY_RSSI = 0x06, |
39 | REG_PHY_ED_LEVEL = 0x07, |
40 | REG_PHY_CC_CCA = 0x08, |
41 | REG_CCA_THRES = 0x09, |
42 | |
43 | REG_IRQ_MASK = 0x0e, |
44 | REG_IRQ_STATUS = 0x0f, |
45 | REG_VREG_CTRL = 0x10, |
46 | REG_BATMON = 0x10, |
47 | REG_XOSC_CTRL = 0x12, |
48 | |
49 | REG_PLL_CF = 0x1a, |
50 | REL_PLL_DCU = 0x1b, |
51 | REG_PART_NUM = 0x1c, |
52 | REG_VERSION_NUM = 0x1d, |
53 | REG_MAN_ID_0 = 0x1e, |
54 | REG_MAN_ID_1 = 0x1f, |
55 | REG_SHORT_ADDR_0 = 0x20, |
56 | REG_SHORT_ADDR_1 = 0x21, |
57 | REG_PAN_ID_0 = 0x22, |
58 | REG_PAN_ID_1 = 0x23, |
59 | REG_IEEE_ADDR_0 = 0x24, |
60 | REG_IEEE_ADDR_1 = 0x25, |
61 | REG_IEEE_ADDR_2 = 0x26, |
62 | REG_IEEE_ADDR_3 = 0x27, |
63 | REG_IEEE_ADDR_4 = 0x28, |
64 | REG_IEEE_ADDR_5 = 0x29, |
65 | REG_IEEE_ADDR_6 = 0x2a, |
66 | REG_IEEE_ADDR_7 = 0x2b, |
67 | REG_XAH_CTRL = 0x2c, |
68 | REG_CSMA_SEED_0 = 0x2d, |
69 | REG_CSMA_SEED_1 = 0x2e, |
70 | |
71 | REG_CONT_TX_0 = 0x36, |
72 | REG_CONT_TX_1 = 0x3d, |
73 | }; |
74 | |
75 | /* --- TRX_STATUS [7] ------------------------------------------------------ */ |
76 | |
77 | #define CCA_DONE (1 << 7) |
78 | |
79 | /* --- TRX_STATUS [6] ------------------------------------------------------ */ |
80 | |
81 | #define CCA_STATUS (1 << 6) |
82 | |
83 | /* --- TRX_STATUS [4:0] ---------------------------------------------------- */ |
84 | |
85 | #define TRX_STATUS_SHIFT 0 |
86 | #define TRX_STATUS_MASK 0x0f |
87 | |
88 | enum { |
89 | TRX_STATUS_P_ON = 0x00, /* reset default */ |
90 | TRX_STATUS_BUSY_RX = 0x01, |
91 | TRX_STATUS_BUSY_TX = 0x02, |
92 | TRX_STATUS_RX_ON = 0x06, |
93 | TRX_STATUS_TRX_OFF = 0x08, |
94 | TRX_STATUS_PLL_ON = 0x09, |
95 | TRX_STATUS_SLEEP = 0x0f, |
96 | TRX_STATUS_BUSY_RX_AACK = 0x11, |
97 | TRX_STATUS_BUSY_TX_ARET = 0x12, |
98 | TRX_STATUS_RX_AACK_ON = 0x16, |
99 | TRX_STATUS_TX_ARET_ON = 0x19, |
100 | TRX_STATUS_RX_ON_NOCLK = 0x1c, |
101 | TRX_STATUS_RX_AACK_ON_NOCLK = 0x1d, |
102 | TRX_STATUS_BUSY_RX_AACK_NOCLK = 0x1e, |
103 | TRX_STATUS_TRANSITION = 0x1f |
104 | }; |
105 | |
106 | /* --- TRX_STATE [7:5] ----------------------------------------------------- */ |
107 | |
108 | #define TRAC_STATUS_SHIFT 5 |
109 | #define TRAC_STATUS_MASK 7 |
110 | |
111 | enum { |
112 | TRAC_STATUS_SUCCESS = 0, /* reset default */ |
113 | TRAC_STATUS_SUCCESS_DATA_PENDING = 1, |
114 | TRAC_STATUS_CHANNEL_ACCESS_FAILURE = 3, |
115 | TRAC_STATUS_NO_ACK = 5, |
116 | TRAC_STATUS_INVALID = 7 |
117 | }; |
118 | |
119 | /* --- TRX_STATE [4:0] ----------------------------------------------------- */ |
120 | |
121 | #define TRX_CMD_SHIFT 0 |
122 | #define TRX_CMD_MASK 7 |
123 | |
124 | enum { |
125 | TRX_CMD_NOP = 0x00, /* reset default */ |
126 | TRX_CMD_TX_START = 0x02, |
127 | TRX_CMD_FORCE_TRX_OFF = 0x03, |
128 | TRX_CMD_RX_ON = 0x06, |
129 | TRX_CMD_TRX_OFF = 0x08, |
130 | TRX_CMD_PLL_ON = 0x09, |
131 | TRX_CMD_RX_AACK_ON = 0x16, |
132 | TRX_CMD_TX_ARET_ON = 0x19, |
133 | }; |
134 | |
135 | /* --- TRX_CTRL_0 [7:6] ---------------------------------------------------- */ |
136 | |
137 | #define PAD_IO_SHIFT 6 |
138 | #define PAD_IO_MASK 3 |
139 | |
140 | enum { |
141 | PAD_IO_2mA, /* reset default */ |
142 | PAD_IO_4mA, |
143 | PAD_IO_6mA, |
144 | PAD_IO_8mA |
145 | }; |
146 | |
147 | /* --- TRX_CTRL_0 [5:4] ---------------------------------------------------- */ |
148 | |
149 | #define PAD_IO_CLKM_SHIFT 4 |
150 | #define PAD_IO_CLKM_MASK 3 |
151 | |
152 | enum { |
153 | PAD_IO_CLKM_2mA, |
154 | PAD_IO_CLKM_4mA, /* reset default */ |
155 | PAD_IO_CLKM_5mA, |
156 | PAD_IO_CLKM_8mA, |
157 | }; |
158 | |
159 | /* --- TRX_CTRL_0 [3] ------------------------------------------------------ */ |
160 | |
161 | #define CLKM_SHA_SEL (1 << 3) |
162 | |
163 | /* --- TRX_CTRL_0 [2:0] ---------------------------------------------------- */ |
164 | |
165 | #define CLKM_CTRL_SHIFT 0 |
166 | #define CLKM_CTRL_MASK 3 |
167 | |
168 | enum { |
169 | CLKM_CTRL_OFF = 0, |
170 | CLKM_CTRL_1MHz = 1, /* reset default */ |
171 | CLKM_CTRL_2MHz = 2, |
172 | CLKM_CTRL_4MHz = 3, |
173 | CLKM_CTRL_8MHz = 4, |
174 | CLKM_CTRL_16MHz = 5 |
175 | }; |
176 | |
177 | /* --- PHY_TX_PWR [7] ------------------------------------------------------ */ |
178 | |
179 | #define TX_AUTO_CRC_ON (1 << 7) |
180 | |
181 | /* --- PHY_TX_PWR [3:0] ---------------------------------------------------- */ |
182 | |
183 | #define TX_PWR_SHIFT 0 |
184 | #define TX_PWR_MASK 0x0f |
185 | |
186 | /* --- PHY_RSSI [7] -------------------------------------------------------- */ |
187 | |
188 | #define RX_CRC_VALID (1 << 7) |
189 | |
190 | /* --- PHY_RSSI [4:0] ------------------------------------------------------ */ |
191 | |
192 | #define RSSI_SHIFT 0 |
193 | #define RSSI_MASK 0x1f |
194 | |
195 | /* --- PHY_CC_CCA [7] ------------------------------------------------------ */ |
196 | |
197 | #define CCA_REQUEST (1 << 7) |
198 | |
199 | /* --- PHY_CC_CCA [6:5] ---------------------------------------------------- */ |
200 | |
201 | #define CCA_MODE_SHIFT 5 |
202 | #define CCA_MODE_MASK 3 |
203 | |
204 | /* --- PHY_CC_CCA [4:0] ---------------------------------------------------- */ |
205 | |
206 | #define CHANNEL_SHIFT 0 |
207 | #define CHANNEL_MASK 0x1f |
208 | |
209 | /* --- CCA_THRES [3:0] ----------------------------------------------------- */ |
210 | |
211 | #define CCA_ED_THRES_SHIFT 0 |
212 | #define CCA_ED_THRES_MASK 0x0f |
213 | |
214 | /* --- IRQ_MASK/IRQ_STATUS ------------------------------------------------- */ |
215 | |
216 | enum { |
217 | IRQ_PLL_LOCK = 1 << 0, |
218 | IRQ_PLL_UNLOCK = 1 << 1, |
219 | IRQ_RX_START = 1 << 2, |
220 | IRQ_TRX_END = 1 << 3, |
221 | IRQ_TRX_UR = 1 << 6, |
222 | IRQ_BAT_LOW = 1 << 7 |
223 | }; |
224 | |
225 | /* --- VREG_CTRL [7, 6, 3, 2] ---------------------------------------------- */ |
226 | |
227 | #define AVREG_EXT (1 << 7) |
228 | #define AVDD_OK (1 << 6) |
229 | #define DVREG_EXT (1 << 3) |
230 | #define DVDD_OK (1 << 2) |
231 | |
232 | /* --- BATMON [5, 4] ------------------------------------------------------- */ |
233 | |
234 | #define BATMON_OK (1 << 5) |
235 | #define BATMON_HR (1 << 4) |
236 | |
237 | /* --- BATMON [3:0] -------------------------------------------------------- */ |
238 | |
239 | #define NATMON_VTH_SHIFT 0 |
240 | #define NATMON_VTH_MASK 0x0f |
241 | |
242 | /* --- XOSC_CTRL [7:4] ----------------------------------------------------- */ |
243 | |
244 | #define XTAL_MODE_SHIFT 4 |
245 | #define XTAL_MODE_MASK 0x0f |
246 | |
247 | enum { |
248 | XTAL_MODE_OFF = 0x0, |
249 | XTAL_MODE_EXT = 0x4, |
250 | XTAL_MODE_INT = 0xf /* reset default */ |
251 | }; |
252 | |
253 | /* --- XOSC_CTRL [3:1] ----------------------------------------------------- */ |
254 | |
255 | #define XTAL_TRIM_SHIFT 4 |
256 | #define XTAL_TRIM_MASK 0x0f |
257 | |
258 | /* --- XAH_CTRL [7:4] ------------------------------------------------------ */ |
259 | |
260 | #define MAX_FRAME_RETRIES_SHIFT 4 |
261 | #define MAX_FRAME_RETRIES_MASK 0x0f |
262 | #define MAX_CSMA_RETRIES_SHIFT 1 |
263 | #define MAX_CSMA_RETRIES_MASK 0x07 |
264 | |
265 | /* --- PLL_CF [7] ---------------------------------------------------------- */ |
266 | |
267 | #define PLL_CF_START (1 << 7) |
268 | |
269 | /* --- PLL_DCU [8] --------------------------------------------------------- */ |
270 | |
271 | #define PLL_DCU_START (1 << 7) |
272 | |
273 | /* --- CSMA_SEED_1 [7:6] --------------------------------------------------- */ |
274 | |
275 | #define MIN_BE_SHIFT 6 |
276 | #define MIN_BE_MASK 3 |
277 | |
278 | /* --- CSMA_SEED_1 [5] ----------------------------------------------------- */ |
279 | |
280 | #define AACK_SET_PD (1 << 5) |
281 | |
282 | /* --- CSMA_SEED_1 [3] ----------------------------------------------------- */ |
283 | |
284 | #define I_AM_COORD (1 << 3) |
285 | |
286 | /* --- CSMA_SEED_1 [2:0] --------------------------------------------------- */ |
287 | |
288 | #define CSMA_SEED_1_SHIFT 0 |
289 | #define CSMA_SEED_1_MASK 7 |
290 | |
291 | /* --- REG_CONT_TX_0 [7:0] ------------------------------------------------- */ |
292 | |
293 | #define CONT_TX_MAGIC 0x0f |
294 | |
295 | /* --- REG_CONT_TX_1 [7:0] ------------------------------------------------- */ |
296 | |
297 | #define CONT_TX_MOD 0x00 /* modulated */ |
298 | #define CONT_TX_M2M 0x10 /* f_CH-2 MHz */ |
299 | #define CONT_TX_M500K 0x80 /* f_CH-0.5 MHz */ |
300 | #define CONT_TX_P500K 0xc0 /* f_CH+0.5 MHz */ |
301 | |
302 | #endif /* !AT86RF230_H */ |
303 |