IEEE 802.15.4 subsystem
Sign in or create your account | Project List | Help
IEEE 802.15.4 subsystem Git Source Tree
Root/
Source at commit e678401ac35ea9bcb1a5075091bd5454d8100f27 created 12 years 9 months ago. By Werner Almesberger, atusb/fw/: split board functions into app-only/shared part (boot overlflowed) | |
---|---|
1 | /* |
2 | * fw/board.c - Board-specific functions (for boot loader and application) |
3 | * |
4 | * Written 2011 by Werner Almesberger |
5 | * Copyright 2011 Werner Almesberger |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by |
9 | * the Free Software Foundation; either version 2 of the License, or |
10 | * (at your option) any later version. |
11 | */ |
12 | |
13 | |
14 | #include <stdint.h> |
15 | |
16 | #include <avr/io.h> |
17 | #include <avr/interrupt.h> |
18 | #include <avr/boot.h> |
19 | |
20 | #define F_CPU 8000000UL |
21 | #include <util/delay.h> |
22 | |
23 | #include "usb.h" |
24 | #include "at86rf230.h" |
25 | #include "board.h" |
26 | #include "spi.h" |
27 | |
28 | |
29 | uint8_t board_sernum[42] = { 42, USB_DT_STRING }; |
30 | |
31 | |
32 | static void set_clkm(void) |
33 | { |
34 | /* switch CLKM to 8 MHz */ |
35 | |
36 | /* |
37 | * @@@ Note: Atmel advise against changing the external clock in |
38 | * mid-flight. We should therefore switch to the RC clock first, then |
39 | * crank up the external clock, and finally switch back to the external |
40 | * clock. The clock switching procedure is described in the ATmega32U2 |
41 | * data sheet in secton 8.2.2. |
42 | */ |
43 | |
44 | spi_begin(); |
45 | spi_send(AT86RF230_REG_WRITE | REG_TRX_CTRL_0); |
46 | spi_send(CLKM_CTRL_8MHz); |
47 | spi_end(); |
48 | } |
49 | |
50 | |
51 | void reset_rf(void) |
52 | { |
53 | /* set up all the outputs; default port value is 0 */ |
54 | |
55 | DDRB = 0; |
56 | DDRC = 0; |
57 | DDRD = 0; |
58 | PORTB = 0; |
59 | PORTC = 0; |
60 | PORTD = 0; |
61 | |
62 | OUT(LED); |
63 | OUT(nRST_RF); /* this also resets the transceiver */ |
64 | OUT(SLP_TR); |
65 | |
66 | spi_init(); |
67 | |
68 | /* AT86RF231 data sheet, 12.4.13, reset pulse width: 625 ns (min) */ |
69 | |
70 | CLR(nRST_RF); |
71 | _delay_us(1); |
72 | SET(nRST_RF); |
73 | |
74 | /* 12.4.14: SPI access latency after reset: 625 ns (min) */ |
75 | |
76 | _delay_us(1); |
77 | |
78 | /* we must restore TRX_CTRL_0 after each reset (9.6.4) */ |
79 | |
80 | set_clkm(); |
81 | } |
82 | |
83 | |
84 | void led(int on) |
85 | { |
86 | if (on) |
87 | SET(LED); |
88 | else |
89 | CLR(LED); |
90 | } |
91 | |
92 | |
93 | void panic(void) |
94 | { |
95 | cli(); |
96 | while (1) { |
97 | SET(LED); |
98 | _delay_ms(100); |
99 | CLR(LED); |
100 | _delay_ms(100); |
101 | } |
102 | } |
103 | |
104 | |
105 | static char hex(uint8_t nibble) |
106 | { |
107 | return nibble < 10 ? '0'+nibble : 'a'+nibble-10; |
108 | } |
109 | |
110 | |
111 | static void get_sernum(void) |
112 | { |
113 | uint8_t sig; |
114 | int i; |
115 | |
116 | for (i = 0; i != 10; i++) { |
117 | sig = boot_signature_byte_get(i+0xe); |
118 | board_sernum[(i << 2)+2] = hex(sig >> 4); |
119 | board_sernum[(i << 2)+4] = hex(sig & 0xf); |
120 | } |
121 | } |
122 | |
123 | |
124 | void board_init(void) |
125 | { |
126 | /* Disable the watchdog timer */ |
127 | |
128 | MCUSR = 0; /* Remove override */ |
129 | WDTCSR |= 1 << WDCE; /* Enable change */ |
130 | WDTCSR = 1 << WDCE; /* Disable watchdog while still enabling |
131 | change */ |
132 | |
133 | /* We start with a 1 MHz/8 clock. Disable the prescaler. */ |
134 | |
135 | CLKPR = 1 << CLKPCE; |
136 | CLKPR = 0; |
137 | |
138 | /* configure timer 1 as a free-running CLK counter */ |
139 | |
140 | TCCR1A = 0; |
141 | TCCR1B = 1 << CS10; |
142 | |
143 | get_sernum(); |
144 | } |
145 |