Root/atusb/fw2/atusb.c

Source at commit ec21e4ba4756379934fc24635438040f66d2ab7c created 8 years 9 months ago.
By Werner Almesberger, atusb/fw2: support device -> host side of the ATUSB EP0 protocol
1#include <stdint.h>
2
3#include <avr/io.h>
4
5#define F_CPU 8000000UL
6#include <util/delay.h>
7
8#include "freakusb.h"
9
10#include "at86rf230.h"
11#include "io.h"
12#include "spi.h"
13
14
15void reset_rf(void);
16void ep0_init(void);
17
18
19void reset_rf(void)
20{
21    /* AT86RF231 data sheet, 12.4.13, reset pulse width: 625 ns (min) */
22
23    CLR(nRST_RF);
24    _delay_us(1);
25    SET(nRST_RF);
26
27    /* 12.4.14: SPI access latency after reset: 625 ns (min) */
28
29    _delay_us(1);
30}
31
32
33int main(void)
34{
35    /* We start with a 1 MHz/8 clock. Disable the prescaler. */
36
37    CLKPR = 1 << CLKPCE;
38    CLKPR = 0;
39
40    /* set up all the outputs; default port value is 0 */
41
42    OUT(LED);
43    OUT(nRST_RF); /* resets the transceiver */
44    OUT(SLP_TR);
45
46    spi_init();
47
48    reset_rf();
49
50    /* switch CLKM to 8 MHz */
51
52    /*
53     * @@@ Note: Atmel advise against changing the external clock in
54     * mid-flight. We should therefore switch to the RC clock first, then
55     * crank up the external clock, and finally switch back to the external
56     * clock. The clock switching procedure is described in the ATmega32U2
57     * data sheet in secton 8.2.2.
58     */
59
60    spi_begin();
61    spi_send(AT86RF230_REG_WRITE | REG_TRX_CTRL_0);
62    spi_send(CLKM_CTRL_8MHz);
63    spi_end();
64
65    /* now we should be at 8 MHz */
66
67    SET(LED);
68    _delay_ms(100);
69    CLR(LED);
70
71    usb_init();
72    ep0_init();
73    hw_init();
74
75    while (1)
76        usb_poll();
77}
78

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