IEEE 802.15.4 subsystem
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IEEE 802.15.4 subsystem Git Source Tree
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| 1 | Version 20100903: |
| 2 | |
| 3 | - changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be |
| 4 | a bad trace. According to simulations, 22 pF should be more than enough. |
| 5 | |
| 6 | - added wire connecting uSD-side ground plane to ground plane at outer edge, |
| 7 | to improve CLK signal return. (Probably unnecessary, too.) |
| 8 | |
| 9 | - the footprint of the transistor (Q1) is reversed :-( It works after |
| 10 | converting the chip from SOT to PLCC. |
| 11 | |
| 12 | - not an erratum, but with experiments showing power-on reset to be |
| 13 | reliable, we can consider removing the hardware reset circuit. This will |
| 14 | also simplify the layout. |
| 15 | |
| 16 | Version 20100908: |
| 17 | |
| 18 | - SPI activity causes the PLL to unlock. Specifically, toggling nSEL does |
| 19 | this. |
| 20 | |
| 21 | - work-around on second 20100908 board: replace the resistive divider with |
| 22 | a capacitative divider. See sim/cdiv.sch. This is a simple BOM change: |
| 23 | |
| 24 | C7 -> 0 R |
| 25 | R3 -> 33 pF |
| 26 | R4 -> 220 pF |
| 27 | |
| 28 | Applied work-around also to first 20100908 board after confirming dismal |
| 29 | performance caused by clock instability. |
| 30 | |
| 31 | - considering that the clock input has a Vpp of only 400-500 mV, we should |
| 32 | have a ground plane also under as much of the the clock circuit as |
| 33 | possible. |
| 34 | |
| 35 | - via between pins 1 and 32 is too close to the chip for DIY PCBs |
| 36 | |
| 37 | Version 20100912: |
| 38 | |
| 39 | - zone fill did not reach upper GND end of antenna. This was not intended, |
| 40 | but may be harmless or even an improvement. |
| 41 |
