IEEE 802.15.4 subsystem
Sign in or create your account | Project List | Help
IEEE 802.15.4 subsystem Git Source Tree
Root/
1 | Correct atusd clock voltage divider |
2 | |
3 | |
4 | According to section 9.6.3 of the data sheet, an external clock supplied |
5 | to the AT86RF230 has a minimum peak-to-peak voltage of 400 mV and a |
6 | maximum of only 500 mV. Furthermore, the signal must be DC-free. |
7 | |
8 | The voltage divider in the 20100903 and 20100908 designs is too sensitive |
9 | to interference and the PLL constantly unlocks, rendering the device |
10 | dysfunctional. |
11 | |
12 | A more robust divider circuit can be obtained with the following |
13 | replacements: C7 -> 0R, R3 -> 33 pF, R4 -> 220 pF. After reworking the |
14 | 20100908 boards, they no longer suffer PLL unlocks. |
15 | |
16 | A Qucs simulation of the circuit can be found in ../atusd/sim/cdiv.sim |
17 | |
18 | Frequency measurements yield the following results: |
19 | |
20 | Host Board Error Meas. accuracy |
21 | (f, ppm) (ppm, nom.) |
22 | ------- --------------- --------------- --------------- |
23 | Ben #2 20100908-A +2 99.7 |
24 | +1 99.6 |
25 | Ben #1 20100908-A +23 99.7 |
26 | +24 99.9 |
27 | Ben #1 20100908-B +24 99.4 |
28 | +24 99.7 |
29 | Ben #2 20100908-B +2 99.8 |
30 | +2 99.9 |
31 | |
32 | The Ben's 12 MHz crystal has a tolerance of +/- 30 ppm, which is better |
33 | than the +/- 40 ppm required by IEEE 802.15.4. |
34 | |
35 | What remains to be verified is whether this change causes interferences |
36 | that may affect transceiver performance and may also violate emission |
37 | regulations. |
38 |