C8051F32x firmware infrastructure
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| 1 | /* |
| 2 | * common/regs-f32x.h - C8051F32x register definitions |
| 3 | * |
| 4 | * Written 2008 by Werner Almesberger |
| 5 | * Copyright 2008 Werner Almesberger |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | |
| 14 | #ifndef REGS_F32X_H |
| 15 | #define REGS_F32X_H |
| 16 | |
| 17 | #include "usb-regs.h" |
| 18 | |
| 19 | |
| 20 | /* REG0CN */ |
| 21 | #define REGMOD 0x10 /* Voltage Regulator Mode Select */ |
| 22 | #define VBPOL 0x20 /* VBUS Interrupt Polarity Select */ |
| 23 | #define VBSTAT 0x40 /* VBUS Signal Status */ |
| 24 | #define REGDIS 0x80 /* Voltage Regulator Disable */ |
| 25 | |
| 26 | /* RSTSRC */ |
| 27 | #define PINRSF 0x01 /* HW Pin Reset Flag */ |
| 28 | /* PORSF 0x02 -- Power-On/VDD Monitor Reset Flag */ |
| 29 | #define MCFRSF 0x04 /* Missing Clock Detector Flag */ |
| 30 | /* SWRSF 0x10 -- Software Reset Force and Flag */ |
| 31 | #define FERROR 0x40 /* Flash Error Indicator */ |
| 32 | #define USBRSF 0x80 /* USB Reset Flag */ |
| 33 | |
| 34 | /* OSCICN */ |
| 35 | #define IFCN0 0x01 /* Internal Oscillator Frequency Control */ |
| 36 | #define IFCN1 0x02 /* 00: /8, 01: /4, 10: /2, 11: /1 */ |
| 37 | #define SUSPEND 0x20 /* Force Suspend */ |
| 38 | #define IFRDY 0x40 /* Internal Oscillator Frequency Ready Flag */ |
| 39 | #define IOSCEN 0x80 /* Internal Oscillator Enable Bit */ |
| 40 | |
| 41 | /* CLKMUL */ |
| 42 | #define MULSEL 0x01 /* Clock Multiplier Input Select */ |
| 43 | #define MULRDY 0x20 /* Clock Multiplier Ready */ |
| 44 | #define MULINIT 0x40 /* Clock Multiplier Initialize */ |
| 45 | #define MULEN 0x80 /* Clock Multiplier Enable */ |
| 46 | |
| 47 | /* VDM0CN */ |
| 48 | #define VDMEN 0x80 /* VDD Monitor Enable */ |
| 49 | #define VDDSTAT 0x40 /* VDD Status */ |
| 50 | |
| 51 | /* USB0XCN */ |
| 52 | #define Dn 0x01 /* D- Signal Status */ |
| 53 | #define Dp 0x02 /* D+ Signal Status */ |
| 54 | #define DFREC 0x04 /* Differential Receiver */ |
| 55 | #define PHYTST0 0x08 /* Physical Layer Test */ |
| 56 | #define PHYTST1 0x10 /* 00: normal, 01: "1", 10: "0", 11: SE0 */ |
| 57 | #define SPEED 0x20 /* USB0 Speed Select */ |
| 58 | #define PHYEN 0x40 /* Physical Layer Enable */ |
| 59 | #define PREN 0x80 /* Internal Pullup Resistor Enable */ |
| 60 | |
| 61 | /* USB0ADR */ |
| 62 | #define AUTORD 0x40 /* USB0 Register Auto-read Flag */ |
| 63 | #define BUSY 0x80 /* USB0 Register Read Busy Flag */ |
| 64 | |
| 65 | /* SMOD0 */ |
| 66 | #define S0DL0 0x04 /* Data Length */ |
| 67 | #define S0DL1 0x08 /* 00: 5-bit, 01: 6-bit, 10: 7-bit, 11: 8-bit */ |
| 68 | |
| 69 | /* SBCON0 */ |
| 70 | #define SB0PS0 0x01 /* Baud Rate Prescaler Select */ |
| 71 | #define SB0PS1 0x02 /* 00: /12, 01: /4, 10: /48, 11: /1 */ |
| 72 | #define SB0RUN 0x40 /* Baud Rate Generator Enable */ |
| 73 | #define SB0CLK 0x80 /* Baud Rate Clock Source */ |
| 74 | |
| 75 | /* TCON */ |
| 76 | #define IT0 0x01 /* Interrupt 0 Type Select */ |
| 77 | #define IE0 0x02 /* External Interrupt 0 */ |
| 78 | #define IT1 0x04 /* Interrupt 1 Type Select */ |
| 79 | #define IE1 0x08 /* External Interrupt 1 */ |
| 80 | #define TR0 0x10 /* Timer 0 Run Control */ |
| 81 | #define TF0 0x20 /* Timer 0 Overflow Flag */ |
| 82 | #define TR1 0x40 /* Timer 1 Run Control */ |
| 83 | #define TF1 0x80 /* Timer 1 Overflow Flag */ |
| 84 | |
| 85 | /* TMOD */ |
| 86 | #define T0M0 0x01 /* Timer 0 Mode Select */ |
| 87 | #define T0M1 0x02 |
| 88 | #define GATE0 0x08 /* Timer 0 Gate Control */ |
| 89 | #define T1M0 0x10 /* Timer 1 Mode Select */ |
| 90 | #define T1M1 0x20 |
| 91 | #define GATE1 0x80 /* Timer 1 Gate Control */ |
| 92 | |
| 93 | /* CKCON */ |
| 94 | #define SCA0 0x01 /* Timer 0/1 Prescale Bits */ |
| 95 | #define SCA1 0x02 |
| 96 | #define T0M 0x04 /* Timer 0 Clock Select */ |
| 97 | #define T1M 0x08 /* Timer 0 Clock Select */ |
| 98 | |
| 99 | #endif /* REGS_F32X_H */ |
| 100 |
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