C8051F32x firmware infrastructure
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| 1 | /* |
| 2 | * common/usb-regs.h - C8051F326 USB register definitions |
| 3 | * |
| 4 | * Written 2008 by Werner Almesberger |
| 5 | * Copyright 2008 Werner Almesberger |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | |
| 14 | #ifndef USB_REGS_H |
| 15 | #define USB_REGS_H |
| 16 | |
| 17 | /* Indirect USB registers */ |
| 18 | |
| 19 | #define FADDR 0x00 /* Function Address */ |
| 20 | |
| 21 | #define POWER 0x01 /* Power Management */ |
| 22 | #define SUSEN 0x01 /* Suspend Detection Enable */ |
| 23 | #define SUSMD 0x02 /* Suspend Mode */ |
| 24 | #define RESUME 0x04 /* Force Resume */ |
| 25 | #define USBRST 0x08 /* Reset Detect */ |
| 26 | #define USBINH 0x10 /* USB0 Inhibit */ |
| 27 | #define ISOUD 0x80 /* ISO Update */ |
| 28 | |
| 29 | #define IN1INT 0x02 /* EP0 and EP1 IN Interrupt Flags */ |
| 30 | #define EP0 0x01 /* EP0 Interrupt-pending Flag */ |
| 31 | #define IN1 0x02 /* IN EP1 Interrupt-pending Flag */ |
| 32 | |
| 33 | #define OUT1INT 0x04 /* EP1 OUT Interrupt Flag */ |
| 34 | |
| 35 | #define CMINT 0x06 /* Common USB Interrupt Flags */ |
| 36 | #define SUSINT 0x01 /* Suspend Interrupt-Pending Flag */ |
| 37 | #define RSUINT 0x02 /* Resume Interrupt-Pending Flag */ |
| 38 | #define RSTINT 0x04 /* Reset Interrupt-Pending Flag */ |
| 39 | #define SOF 0x08 /* Start of Frame Interrupt */ |
| 40 | |
| 41 | #define IN1IE 0x07 /* EP0 and EP1 IN Interrupt Enables */ |
| 42 | |
| 43 | #define OUT1IE 0x09 /* EP1 out Interrupt Enable */ |
| 44 | |
| 45 | #define CMIE 0x0b /* Common USB Interrupt Enable */ |
| 46 | |
| 47 | #define FRAMEL 0x0c /* Frame Number Low Byte */ |
| 48 | |
| 49 | #define FRAMEH 0x0d /* Frame Number Low Byte */ |
| 50 | |
| 51 | #define INDEX 0x0e /* USB0 EP Index */ |
| 52 | |
| 53 | #define CLKREC 0x0f /* Clock Recovery Control */ |
| 54 | #define CRLOW 0x20 /* Low Speed Clock Recovery Mode */ |
| 55 | #define CRSSEN 0x40 /* Clock Recovery Single Step */ |
| 56 | #define CRE 0x80 /* Clock Recovery Enable */ |
| 57 | |
| 58 | #define E0CSR 0x11 /* EP0 Control/Status */ |
| 59 | #define OPRDY_0 0x01 /* OUT Packet Ready */ |
| 60 | #define INPRDY_0 0x02 /* IN Packet Ready */ |
| 61 | #define STSTL_0 0x04 /* Sent Stall */ |
| 62 | #define DATAEND 0x08 /* Data End */ |
| 63 | #define SUEND 0x10 /* Setup End */ |
| 64 | #define SDSTL_0 0x20 /* Send Stall */ |
| 65 | #define SOPRDY 0x40 /* Serviced OPRDY */ |
| 66 | #define SSUEND 0x80 /* Serviced Setup End */ |
| 67 | |
| 68 | #define EINCSRL 0x11 /* EP IN Control/Status Low Byte */ |
| 69 | #define INPRDY_IN 0x01 /* IN Packet Ready */ |
| 70 | #define FIFONE 0x02 /* FIFO Not Empty */ |
| 71 | #define UNDRUN 0x04 /* Data Underrun */ |
| 72 | #define FLUSH_IN 0x08 /* FIFO Flush */ |
| 73 | #define SDSTL_IN 0x10 /* Send Stall */ |
| 74 | #define STSTL_IN 0x20 /* Sent Stall */ |
| 75 | #define CLRDT_IN 0x40 /* Clear Data Toggle */ |
| 76 | |
| 77 | #define EINCSRH 0x12 /* EP OUT Control/Status High Byte */ |
| 78 | |
| 79 | #define EOUTCSRL 0x14 /* EP OUT Control/Status Low Byte */ |
| 80 | #define OPRDY_OUT 0x01 /* OUT Packet Ready */ |
| 81 | #define FIFOFUL 0x02 /* OUT FIFO Full */ |
| 82 | #define OVRUN 0x04 /* Data Overrun */ |
| 83 | #define DATERR 0x08 /* Data Error */ |
| 84 | #define FLUSH_OUT 0x10 /* FIFO Flush */ |
| 85 | #define SDSTL_OUT 0x20 /* Send Stall */ |
| 86 | #define STSTL_OUT 0x40 /* Sent Stall */ |
| 87 | #define CLRDT_OUT 0x80 /* Clear Data Toggle */ |
| 88 | |
| 89 | #define EOUTCSRH 0x15 /* EP OUT Control/Status High Byte */ |
| 90 | |
| 91 | #define E0CNT 0x16 /* Number of Received Bytes in EP0 FIFO */ |
| 92 | |
| 93 | #define EOUTCNTL 0x16 /* EP OUT Packet Count Low Byte */ |
| 94 | |
| 95 | #define EOUTCNTH 0x17 /* EP OUT Packet Count High Byte */ |
| 96 | |
| 97 | #define FIFO0 0x20 /* EP0 FIFO */ |
| 98 | |
| 99 | #define FIFO1 0x21 /* EP1 FIFO */ |
| 100 | |
| 101 | #endif /* !USB_REGS_H */ |
| 102 |
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