mips/nanonote/unbrick.ccp |
| 1 | #pypp 0 |
| 2 | // Iris: micro-kernel for a capability-based operating system. |
| 3 | // mips/nanonote/unbrick.ccp: Host-side helper for USB boot. |
| 4 | // Copyright 2009-2010 Bas Wijnen <wijnen@debian.org> |
| 5 | // |
| 6 | // This program is free software: you can redistribute it and/or modify |
| 7 | // it under the terms of the GNU General Public License as published by |
| 8 | // the Free Software Foundation, either version 3 of the License, or |
| 9 | // (at your option) any later version. |
| 10 | // |
| 11 | // This program is distributed in the hope that it will be useful, |
| 12 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | // GNU General Public License for more details. |
| 15 | // |
| 16 | // You should have received a copy of the GNU General Public License |
| 17 | // along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | |
| 19 | #include <unistd.h> |
| 20 | #include <usb.h> |
| 21 | #include <fstream> |
| 22 | #include <sstream> |
| 23 | #include <iostream> |
| 24 | #include <iomanip> |
| 25 | #include <cstring> |
| 26 | #include <shevek/args.hh> |
| 27 | #include <shevek/error.hh> |
| 28 | |
| 29 | #define STAGE1_FILE "stage1.raw" |
| 30 | |
| 31 | static usb_dev_handle *handle |
| 32 | static int const boot_vendor = 0x601a |
| 33 | static int const boot_product = 0x4740 |
| 34 | static int const run_vendor = 0xfffe |
| 35 | static int const run_product = 0x0002 |
| 36 | static unsigned const timeout = 10000 |
| 37 | void boot (std::string const &filename, unsigned load, unsigned entry) |
| 38 | static unsigned const STAGE1_LOAD = 0x80002000 |
| 39 | static unsigned const STAGE1_ENTRY = STAGE1_LOAD |
| 40 | enum requests: |
| 41 | VR_GET_CPU_INFO = 0 |
| 42 | VR_SET_DATA_ADDRESS = 1 |
| 43 | VR_SET_DATA_LENGTH = 2 |
| 44 | VR_FLUSH_CACHES = 3 |
| 45 | VR_PROGRAM_START1 = 4 |
| 46 | VR_PROGRAM_START2 = 5 |
| 47 | void request (requests num, unsigned data = 0) |
| 48 | void get_device (unsigned vendor, unsigned product, unsigned tries) |
| 49 | |
| 50 | void request (requests r, unsigned data): |
| 51 | if usb_control_msg (handle, USB_ENDPOINT_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, r, (data >> 16) & 0xffff, data & 0xffff, NULL, 0, timeout) < 0: |
| 52 | std::cerr << "unable to send control message to NanoNote: " << usb_strerror () << ".\n" |
| 53 | usb_release_interface (handle, 0) |
| 54 | usb_close (handle) |
| 55 | handle = NULL |
| 56 | |
| 57 | void send_file (unsigned address, int size, char const *data): |
| 58 | request (VR_SET_DATA_ADDRESS, address) |
| 59 | char const *ptr = data |
| 60 | while ptr - data < size: |
| 61 | int ret = usb_bulk_write (handle, 1, ptr, size - (ptr - data), timeout) |
| 62 | if ret <= 0: |
| 63 | std::cerr << "failed to write to NanoNote.\n" |
| 64 | usb_release_interface (handle, 0) |
| 65 | usb_close (handle) |
| 66 | handle = NULL |
| 67 | return |
| 68 | ptr += ret |
| 69 | |
| 70 | void get_device (unsigned vendor, unsigned product, unsigned tries): |
| 71 | for unsigned i = 0; i < tries; ++i: |
| 72 | usb_find_busses () |
| 73 | usb_find_devices () |
| 74 | for struct usb_bus *bus = usb_busses; bus; bus = bus->next: |
| 75 | for struct usb_device *dev = bus->devices; dev; dev = dev->next: |
| 76 | if dev->descriptor.idProduct != product || dev->descriptor.idVendor != vendor: |
| 77 | //std::cerr << shevek::ostring ("Not using %04x:%04x when looking for %04x:%04x\n", dev->descriptor.idVendor, dev->descriptor.idProduct, vendor, product) |
| 78 | continue |
| 79 | handle = usb_open (dev) |
| 80 | if usb_claim_interface (handle, 0) < 0: |
| 81 | std::cerr << "unable to claim interface: " << usb_strerror () << "\n" |
| 82 | usb_close (handle) |
| 83 | handle = NULL |
| 84 | continue |
| 85 | return |
| 86 | if i + 1 < tries: |
| 87 | //std::cerr << "failed to find device, still trying...\n" |
| 88 | sleep (1) |
| 89 | std::cerr << shevek::ostring ("giving up finding device %04x:%04x\n", vendor, product) |
| 90 | |
| 91 | void boot (std::string const &filename, unsigned load, unsigned entry): |
| 92 | std::cerr << "booting " << shevek::ostring ("%s from %x@%x", Glib::ustring (filename), load, entry) << "\n" |
| 93 | get_device (boot_vendor, boot_product, 1) |
| 94 | if !handle: |
| 95 | std::cerr << "unable to find device\n" |
| 96 | return |
| 97 | std::cerr << "sending stage 1\n" |
| 98 | std::ifstream file (STAGE1_FILE) |
| 99 | std::ostringstream stage1 |
| 100 | stage1 << file.rdbuf () |
| 101 | send_file (STAGE1_LOAD, stage1.str ().size (), stage1.str ().data ()) |
| 102 | std::cerr << "running stage 1\n" |
| 103 | request (VR_PROGRAM_START1, STAGE1_ENTRY) |
| 104 | usleep (100) |
| 105 | std::ostringstream stage2 |
| 106 | usb_release_interface (handle, 0) |
| 107 | file.close () |
| 108 | file.open (filename.c_str ()) |
| 109 | stage2 << file.rdbuf () |
| 110 | std::cerr << shevek::ostring ("sending Iris (size 0x%x)\n", stage2.str ().size ()) |
| 111 | send_file (load, stage2.str ().size (), stage2.str ().data ()) |
| 112 | std::cerr << "flushing caches\n" |
| 113 | request (VR_FLUSH_CACHES) |
| 114 | std::cerr << "running Iris\n" |
| 115 | request (VR_PROGRAM_START2, entry) |
| 116 | usb_release_interface (handle, 0) |
| 117 | usb_close (handle) |
| 118 | handle = NULL |
| 119 | std::cerr << "done\n" |
| 120 | |
| 121 | int main (int argc, char **argv): |
| 122 | std::string filename ("iris.raw") |
| 123 | unsigned load (0x80000000), entry (0) |
| 124 | handle = NULL |
| 125 | usb_init () |
| 126 | shevek::args::option opts[] = { |
| 127 | shevek::args::option ('f', "file", "image file", true, filename), |
| 128 | shevek::args::option ('l', "load", "load address", true, load), |
| 129 | shevek::args::option ('e', "entry", "entry point address", false, entry) |
| 130 | } |
| 131 | shevek::args args (argc, argv, opts, 0, 0, "unbrick program for NanoNote", "2009-2010") |
| 132 | if !entry: |
| 133 | shevek_error ("You must specify the entry point") |
| 134 | boot (filename, load, entry) |
| 135 | return 0 |
source/usb-mass-storage.ccp |
28 | 28 | IN interrupt: csw received, do nothing. |
29 | 29 | OUT interrupt: cbw; handle |
30 | 30 | -> IDLE (no data; csw sent) |
31 | | -> CSW (data sent in one packet) |
32 | | -> TX (more than one packet to send) |
| 31 | -> TX (send) |
33 | 32 | -> RX (receive packets) |
34 | 33 | TX: transmitting data. |
35 | 34 | IN interrupt: host received data; send more. |
36 | 35 | -> TX (more to send) |
37 | | -> CSW (last data has now been sent) |
38 | 36 | RX: receiving data. |
39 | 37 | OUT interrupt: host sent data; handle. |
40 | 38 | -> RX (more to receive) |
41 | 39 | -> IDLE (done receiving; send csw) |
42 | | CSW: waiting to transmit csw. |
43 | | IN interrupt: TX is done; send csw |
44 | | -> IDLE |
45 | 40 | #endif |
46 | 41 | |
47 | 42 | extern "C": |
... | ... | |
218 | 213 | char configuration |
219 | 214 | unsigned get_descriptor (unsigned type, unsigned idx, unsigned len) |
220 | 215 | unsigned handle_setup (Setup *s) |
221 | | void irq_usb () |
| 216 | void reset () |
222 | 217 | void irq_in0 () |
223 | | void irq_out () |
| 218 | void handle_rx () |
| 219 | void handle_tx () |
| 220 | void handle_cbw () |
224 | 221 | void send_csw () |
225 | 222 | unsigned big_endian (unsigned src) |
226 | 223 | bool handle_interrupt (bool usb, bool in) |
227 | 224 | void stall (unsigned error) |
228 | | bool stalling[3] |
| 225 | bool stalling |
| 226 | enum State: |
| 227 | IDLE |
| 228 | TX |
| 229 | RX |
| 230 | SENT_CSW |
| 231 | STALL |
| 232 | State state |
229 | 233 | unsigned residue |
230 | 234 | unsigned status |
231 | 235 | unsigned tag |
| 236 | unsigned data_done, lba, blocks |
232 | 237 | unsigned block_bits |
233 | 238 | Iris::WBlock block |
234 | 239 | Iris::Page buffer_page |
... | ... | |
248 | 253 | Udc::String <16> Udc::s_product |
249 | 254 | Udc::String <12> Udc::s_serial |
250 | 255 | |
| 256 | void Udc::reset (): |
| 257 | // Reset. |
| 258 | UDC_TESTMODE = 0 |
| 259 | configuration = 0 |
| 260 | state = IDLE |
| 261 | status = 0 |
| 262 | residue = 0 |
| 263 | // enable interrupt on bus reset. |
| 264 | UDC_INTRUSBE = UDC_INTR_RESET |
| 265 | // enable interrupts on endpoint 0 and in endpoint 2 |
| 266 | UDC_INTRINE = 1 << 0 | 1 << 2 |
| 267 | // and on out endpoint 1. |
| 268 | UDC_INTROUTE = 1 << 1 |
| 269 | // exit suspend mode by reading the interrupt register. |
| 270 | unsigned i = UDC_INTRUSB |
| 271 | // reset all pending endpoint interrupts. |
| 272 | i = UDC_INTRIN |
| 273 | i = UDC_INTROUT |
| 274 | UDC_INDEX = 1 |
| 275 | UDC_OUTMAXP = max_packet_size_bulk |
| 276 | // Do this twice to flush a double-buffered fifo completely. |
| 277 | UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
| 278 | UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
| 279 | UDC_INDEX = 2 |
| 280 | UDC_INMAXP = max_packet_size_bulk |
| 281 | UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF |
| 282 | UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF |
| 283 | //Iris::debug ("usb reset\n") |
| 284 | |
251 | 285 | void Udc::init (Iris::WBlock b): |
252 | 286 | block = b |
253 | 287 | block_bits = block.get_align_bits () |
... | ... | |
272 | 306 | cpm_start_udc () |
273 | 307 | // Disconnect from the bus and don't try to get high-speed. |
274 | 308 | UDC_POWER = 0 |
275 | | UDC_TESTMODE = 0 |
276 | | configuration = 0 |
277 | | // Set max packet sizes. |
278 | | UDC_INDEX = 1 |
279 | | UDC_OUTMAXP = max_packet_size_bulk |
280 | | UDC_OUTCSR = UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
281 | | UDC_OUTCSR = UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
282 | | UDC_INDEX = 2 |
283 | | UDC_INMAXP = max_packet_size_bulk |
284 | | UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF |
285 | | UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF |
286 | | // exit suspend mode by reading the interrupt register. |
287 | | unsigned i = UDC_INTRUSB |
288 | | // reset all pending endpoint interrupts. |
289 | | i = UDC_INTRIN |
290 | | i = UDC_INTROUT |
291 | | // enable interrupt on bus reset. |
292 | | UDC_INTRUSBE = UDC_INTR_RESET |
293 | | // enable interrupts on endpoint 0 and in endpoint 2 |
294 | | UDC_INTRINE = 1 << 0 | 1 << 2 |
295 | | // and on out endpoint 1. |
296 | | UDC_INTROUTE = 1 << 1 |
| 309 | reset () |
297 | 310 | // Wait a while. |
298 | 311 | Iris::sleep (HZ / 10) |
299 | 312 | // Connect to the host. |
300 | 313 | UDC_POWER = UDC_POWER_SOFTCONN |
301 | 314 | |
302 | | // Initialize cbw state |
303 | | status = 0 |
304 | | residue = 0 |
305 | | |
306 | 315 | void Udc::send (unsigned ep, char const *data, unsigned length, unsigned maxlength): |
307 | 316 | if maxlength < length: |
308 | 317 | length = maxlength |
... | ... | |
318 | 327 | |
319 | 328 | void Udc::send_padded (char const *data, unsigned length, unsigned maxlength): |
320 | 329 | UDC_INDEX = 2 |
321 | | if UDC_INCSR & UDC_INCSR_INPKTRDY: |
322 | | Iris::panic (0, "sending padded not possible because a packet is already waiting.\n") |
323 | 330 | unsigned len = length < maxlength ? length : maxlength |
324 | 331 | residue = maxlength - len |
325 | 332 | len = (len + 3) & ~3 |
... | ... | |
328 | 335 | while len + 3 < maxlength: |
329 | 336 | UDC_FIFO (2) = 0 |
330 | 337 | len += 4 |
331 | | if len % max_packet_size_bulk == 0: |
332 | | // This doesn't ever happen, because the largest packet we send is smaller than max_packet_size_bulk. |
333 | | Iris::debug ("sending at len %x\n", len) |
334 | | UDC_INCSR |= UDC_INCSR_INPKTRDY |
335 | | while true: |
336 | | Iris::register_interrupt (IRQ_UDC) |
337 | | Iris::wait_for_interrupt (IRQ_UDC) |
338 | | kdebug ("interrupt pad0\n") |
339 | | unsigned usb = UDC_INTRUSB |
340 | | unsigned in = UDC_INTRIN |
341 | | if usb & 4 || in & 1: |
342 | | //kdebug ("general interrupt pad0\t") |
343 | | if !handle_interrupt (usb & 4, in & 1): |
344 | | return |
345 | | unsigned out = UDC_INTROUT |
346 | | if out & 2: |
347 | | Iris::panic (0, "out interrupt while waiting for in") |
348 | | if in & 4: |
349 | | break |
350 | 338 | //kdebug_char ('-') |
351 | | if len % max_packet_size_bulk != 0 || len < maxlength: |
352 | | while len < maxlength: |
353 | | UDC_FIFO8 (2) = 0 |
354 | | ++len |
355 | | //kdebug_char ('.') |
356 | | UDC_INCSR |= UDC_INCSR_INPKTRDY |
357 | | while true: |
358 | | Iris::register_interrupt (IRQ_UDC) |
359 | | Iris::wait_for_interrupt (IRQ_UDC) |
360 | | kdebug ("interrupt pad\t") |
361 | | unsigned usb = UDC_INTRUSB |
362 | | unsigned in = UDC_INTRIN |
363 | | if usb & 4 || in & 1: |
364 | | //kdebug ("general interrupt pad\t") |
365 | | if !handle_interrupt (usb & 4, in & 1): |
366 | | return |
367 | | unsigned out = UDC_INTROUT |
368 | | if out & 2: |
369 | | Iris::panic (0, "out interrupt while waiting for in") |
370 | | if in & 4: |
371 | | break |
372 | | //kdebug ("done interrupt pad\n") |
| 339 | while len < maxlength: |
| 340 | UDC_FIFO8 (2) = 0 |
| 341 | ++len |
| 342 | //kdebug_char ('.') |
| 343 | UDC_INCSR |= UDC_INCSR_INPKTRDY |
| 344 | blocks = 0 |
| 345 | state = TX |
373 | 346 | |
374 | 347 | unsigned Udc::get_descriptor (unsigned type, unsigned idx, unsigned len): |
375 | 348 | switch type: |
... | ... | |
424 | 397 | switch s->request: |
425 | 398 | case SET_ADDRESS: |
426 | 399 | UDC_FADDR = s->value |
427 | | //Iris::debug ("set address %x\n", s->value) |
| 400 | Iris::debug ("set address %x\n", s->value) |
428 | 401 | return 0 |
429 | 402 | case SET_CONFIGURATION: |
430 | 403 | if s->value >= 2: |
431 | 404 | return ~0 |
432 | 405 | configuration = s->value |
433 | | //Iris::debug ("set configuration %x\n", s->value) |
| 406 | Iris::debug ("set configuration %x\n", s->value) |
434 | 407 | return 0 |
435 | 408 | case SET_INTERFACE: |
436 | 409 | if s->value != 0: |
437 | 410 | return ~0 |
438 | | //Iris::debug ("set interface %x\n", s->value) |
| 411 | Iris::debug ("set interface %x\n", s->value) |
439 | 412 | return 0 |
440 | 413 | default: |
441 | 414 | return ~0 |
... | ... | |
444 | 417 | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
445 | 418 | switch s->request: |
446 | 419 | case GET_STATUS: |
447 | | //Iris::debug ("get status\t") |
| 420 | Iris::debug ("get status\t") |
448 | 421 | send (0, "\0\0", 2, s->length) |
449 | 422 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
450 | 423 | case GET_DESCRIPTOR: |
451 | 424 | return get_descriptor ((s->value >> 8) & 0xff, s->value & 0xff, s->length) |
452 | 425 | case GET_CONFIGURATION: |
453 | | //Iris::debug ("get configuration\t") |
| 426 | Iris::debug ("get configuration\t") |
454 | 427 | send (0, &configuration, 1, s->length) |
455 | 428 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
456 | 429 | case GET_INTERFACE: |
457 | | //Iris::debug ("get interface\t") |
| 430 | Iris::debug ("get interface\t") |
458 | 431 | send (0, "\0", 1, s->length) |
459 | 432 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
460 | 433 | default: |
... | ... | |
466 | 439 | case ENDPOINT_HALT: |
467 | 440 | switch s->index: |
468 | 441 | case 0x82: |
469 | | Iris::debug ("in ep halt reset\n") |
| 442 | //Iris::debug ("in ep halt reset\n") |
470 | 443 | UDC_INDEX = 2 |
471 | | UDC_INCSR &= ~UDC_INCSR_SENDSTALL |
472 | | stalling[2] = false |
| 444 | UDC_INCSR = (UDC_INCSR & ~UDC_INCSR_SENDSTALL) | UDC_INCSR_CDT |
| 445 | stalling = false |
| 446 | send_csw () |
473 | 447 | break |
474 | 448 | case 1: |
475 | | Iris::debug ("out ep halt reset\n") |
| 449 | //Iris::panic (0, "halt reset on out endpoint") |
476 | 450 | UDC_INDEX = 1 |
477 | | UDC_OUTCSR &= ~UDC_OUTCSR_SENDSTALL |
478 | | stalling[1] = false |
| 451 | UDC_OUTCSR |= UDC_OUTCSR_CDT |
479 | 452 | break |
480 | 453 | default: |
481 | 454 | return ~0 |
... | ... | |
499 | 472 | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
500 | 473 | switch s->request: |
501 | 474 | case BULK_ONLY_RESET: |
502 | | //Iris::debug ("bulk reset\n") |
| 475 | Iris::debug ("bulk reset\n") |
| 476 | state = IDLE |
503 | 477 | return 0 |
504 | 478 | default: |
505 | 479 | return ~0 |
... | ... | |
507 | 481 | Iris::debug ("request: %x %x %x %x %x\n", s->request_type, s->request, s->index, s->length, s->value) |
508 | 482 | return ~0 |
509 | 483 | |
510 | | void Udc::irq_usb (): |
511 | | // Reset. |
512 | | // enable interrupts on endpoint 0 and in endpoint 2 |
513 | | UDC_INTRINE = 1 << 0 | 1 << 2 |
514 | | // and on out endpoint 1. |
515 | | UDC_INTROUTE = 1 << 1 |
516 | | UDC_INDEX = 1 |
517 | | // Do this twice to flush a double-buffered fifo completely. |
518 | | UDC_OUTMAXP = max_packet_size_bulk |
519 | | UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
520 | | UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
521 | | UDC_INDEX = 2 |
522 | | UDC_INMAXP = max_packet_size_bulk |
523 | | UDC_INCSR |= UDC_INCSR_CDT |
524 | | //Iris::debug ("usb reset\n") |
525 | | |
526 | 484 | void Udc::irq_in0 (): |
527 | 485 | // Interrupt on endpoint 0. |
528 | 486 | UDC_INDEX = 0 |
529 | 487 | unsigned csr = UDC_CSR0 |
530 | 488 | if csr & UDC_CSR0_SENTSTALL: |
531 | 489 | UDC_CSR0 = 0 |
532 | | //Iris::debug ("stall done\t") |
| 490 | //Iris::debug ("stall 0 done\t") |
533 | 491 | if csr & UDC_CSR0_SETUPEND: |
534 | 492 | UDC_CSR0 = UDC_CSR0_SVDSETUPEND |
535 | | //Iris::debug ("setup aborted\t") |
| 493 | Iris::debug ("setup aborted\t") |
536 | 494 | if !(csr & UDC_CSR0_OUTPKTRDY): |
537 | 495 | //Iris::debug ("no packet 0: %x\n", csr) |
538 | 496 | return |
539 | | UDC_INDEX = 1 |
540 | | UDC_OUTCSR |= UDC_OUTCSR_CDT |
541 | | UDC_INDEX = 2 |
542 | | UDC_INCSR |= UDC_INCSR_CDT |
543 | 497 | UDC_INDEX = 0 |
544 | 498 | union { unsigned d[2]; Setup s; } packet |
545 | 499 | packet.d[0] = UDC_FIFO (0) |
546 | 500 | packet.d[1] = UDC_FIFO (0) |
547 | 501 | if !(packet.s.request_type & 0x80) && packet.s.length > 0: |
548 | 502 | // More data will follow; unsupported. |
549 | | //Iris::debug ("packet on ep0 too long\n") |
| 503 | Iris::debug ("packet on ep0 too long\n") |
550 | 504 | UDC_CSR0 = UDC_CSR0_SENDSTALL |
551 | 505 | return |
552 | 506 | unsigned ret = handle_setup (&packet.s) |
553 | 507 | UDC_INDEX = 0 |
554 | 508 | if ret == ~0: |
555 | | Iris::debug ("failed setup: %x %x %x %x %x\n", packet.s.request_type, packet.s.request, packet.s.index, packet.s.length, packet.s.value) |
| 509 | //Iris::debug ("failed setup: %x %x %x %x %x\n", packet.s.request_type, packet.s.request, packet.s.index, packet.s.length, packet.s.value) |
556 | 510 | UDC_CSR0 = UDC_CSR0_SENDSTALL |
557 | 511 | return |
558 | 512 | if ret: |
... | ... | |
566 | 520 | UDC_FIFO (2) = residue |
567 | 521 | UDC_FIFO8 (2) = status |
568 | 522 | UDC_INCSR |= UDC_INCSR_INPKTRDY |
| 523 | state = SENT_CSW |
569 | 524 | status = 0 |
570 | 525 | residue = 0 |
571 | | while true: |
572 | | Iris::register_interrupt (IRQ_UDC) |
573 | | Iris::wait_for_interrupt (IRQ_UDC) |
574 | | kdebug ("interrupt csw\n") |
575 | | unsigned usb = UDC_INTRUSB |
576 | | unsigned in = UDC_INTRIN |
577 | | if usb & 4 || in & 1: |
578 | | if !handle_interrupt (usb & 4, in & 1): |
579 | | return |
580 | | if in & 4: |
581 | | break |
582 | | unsigned out = UDC_INTROUT |
583 | | if out & 2: |
584 | | Iris::panic (0, "out interrupt while waiting for in after csw") |
585 | | kdebug ("sent csw\n") |
| 526 | //kdebug ("sent csw\n") |
586 | 527 | |
587 | 528 | void Udc::stall (unsigned error): |
588 | | unsigned index = UDC_INDEX |
589 | | if stalling[index]: |
| 529 | if stalling: |
590 | 530 | Iris::debug ("already stalling!\n") |
591 | | if index == 1: |
592 | | UDC_OUTCSR |= UDC_OUTCSR_SENDSTALL |
593 | | else: |
594 | | UDC_INCSR |= UDC_INCSR_SENDSTALL |
595 | | stalling[index] = true |
596 | | while stalling[index]: |
597 | | //Iris::debug ("stalling %d\n", index) |
598 | | Iris::register_interrupt (IRQ_UDC) |
599 | | Iris::wait_for_interrupt (IRQ_UDC) |
600 | | kdebug ("stalling interrupt\n") |
601 | | unsigned usb = UDC_INTRUSB |
602 | | unsigned in = UDC_INTRIN |
603 | | if in & 4: |
604 | | if index != 2: |
605 | | Iris::panic (0, "stalling on out, but in responds") |
606 | | kdebug ("stall has been sent to in endpoint\n") |
607 | | UDC_INDEX = 2 |
608 | | UDC_INCSR &= ~UDC_INCSR_SENTSTALL |
609 | | //Iris::debug ("csr: %x\n", UDC_INCSR) |
610 | | if usb & 4 || in & 1: |
611 | | //kdebug ("stuff\n") |
612 | | if !handle_interrupt (usb & 4, in & 1): |
613 | | return |
614 | | unsigned out = UDC_INTROUT |
615 | | if out & 2: |
616 | | if index != 1: |
617 | | Iris::panic (0, "stalling on in, but out responds") |
618 | | kdebug ("stall has been sent to out endpoint\n") |
619 | | UDC_INDEX = 1 |
620 | | UDC_OUTCSR &= ~UDC_OUTCSR_SENTSTALL |
621 | | //kdebug ("done stalling\n") |
622 | | if index == 2: |
623 | | status = error |
624 | | send_csw () |
| 531 | UDC_INCSR |= UDC_INCSR_SENDSTALL |
| 532 | stalling = true |
| 533 | state = STALL |
625 | 534 | |
626 | 535 | unsigned Udc::big_endian (unsigned src): |
627 | 536 | return src >> 24 | src >> 8 & 0xff00 | src << 8 & 0xff0000 | src << 24 |
628 | 537 | |
629 | | void Udc::irq_out (): |
| 538 | void Udc::handle_rx (): |
| 539 | buffer_page.set_flags (Iris::Page::FRAME) |
| 540 | UDC_INDEX = 1 |
| 541 | if !(UDC_OUTCSR & UDC_OUTCSR_OUTPKTRDY): |
| 542 | Iris::panic (0, "no packet ready after out interrupt during rx") |
| 543 | if UDC_OUTCOUNT != max_packet_size_bulk: |
| 544 | Iris::panic (UDC_OUTCOUNT, "invalid packet size during rx") |
| 545 | for unsigned t = 0; t < max_packet_size_bulk; t += 4: |
| 546 | ((unsigned *)buffer)[(t + data_done) >> 2] = UDC_FIFO (1) |
| 547 | UDC_OUTCSR &= ~UDC_OUTCSR_OUTPKTRDY |
| 548 | data_done += max_packet_size_bulk |
| 549 | if data_done == 1 << block_bits: |
| 550 | //Iris::debug ("writing block %x\n", lba) |
| 551 | block.set_block (lba << block_bits, buffer_page, 1 << block_bits) |
| 552 | data_done = 0 |
| 553 | --blocks |
| 554 | ++lba |
| 555 | if blocks == 0: |
| 556 | send_csw () |
| 557 | return |
| 558 | |
| 559 | void Udc::handle_tx (): |
| 560 | if blocks == 0: |
| 561 | send_csw () |
| 562 | return |
| 563 | if data_done == 0: |
| 564 | // read block lba. |
| 565 | buffer_page.set_flags (Iris::Page::FRAME) |
| 566 | block.get_block (lba << block_bits, 1 << block_bits, 0, buffer_page) |
| 567 | UDC_INDEX = 2 |
| 568 | for unsigned t = 0; t < max_packet_size_bulk; t += 4: |
| 569 | UDC_FIFO (2) = ((unsigned *)buffer)[(data_done + t) >> 2] |
| 570 | data_done += max_packet_size_bulk |
| 571 | if data_done == 1 << block_bits: |
| 572 | data_done = 0 |
| 573 | ++lba |
| 574 | --blocks |
| 575 | UDC_INCSR |= UDC_INCSR_INPKTRDY |
| 576 | |
| 577 | void Udc::handle_cbw (): |
630 | 578 | UDC_INDEX = 1 |
631 | 579 | unsigned csr = UDC_OUTCSR |
632 | 580 | unsigned size = UDC_OUTCOUNT |
633 | | if !(csr & UDC_OUTCSR_OUTPKTRDY): |
634 | | // No packet, just a notification. |
635 | | kdebug ("no packet\n") |
636 | | return |
637 | 581 | if csr & UDC_OUTCSR_SENDSTALL: |
638 | 582 | // When stalling, do nothing else. |
639 | 583 | //kdebug ("not responding to out during stall\n") |
640 | 584 | UDC_OUTCSR = csr & ~UDC_OUTCSR_SENTSTALL |
641 | 585 | return |
| 586 | if !(csr & UDC_OUTCSR_OUTPKTRDY): |
| 587 | // No packet; this shouldn't happen. |
| 588 | Iris::panic (0, "no packet") |
| 589 | return |
642 | 590 | // expect a new cbw. |
643 | 591 | if size != 31: |
644 | 592 | Iris::debug ("count %d != 31\n", size) |
... | ... | |
656 | 604 | UDC_OUTCSR = csr & ~UDC_OUTCSR_OUTPKTRDY |
657 | 605 | tag = cbw.cbw.tag |
658 | 606 | if cbw.cbw.sig != 0x43425355 || cbw.cbw.lun != 0 || cbw.cbw.size == 0 || cbw.cbw.size > 16: |
659 | | Iris::debug ("sig %x lun %d size %d\n", cbw.cbw.sig, cbw.cbw.lun, cbw.cbw.size) |
| 607 | Iris::debug ("wrong cbw: sig %x lun %d size %d\n", cbw.cbw.sig, cbw.cbw.lun, cbw.cbw.size) |
660 | 608 | stall (2) |
661 | 609 | return |
662 | 610 | //kdebug ("bulk cbw\t") |
| 611 | #if 0 |
| 612 | Iris::debug ("cbw:") |
| 613 | for unsigned i = 0; i < cbw.cbw.size; ++i: |
| 614 | kdebug_char (' ') |
| 615 | kdebug_num (cbw.cbw.data[i], 2) |
| 616 | Iris::debug ("\n") |
| 617 | #endif |
663 | 618 | UDC_INDEX = 2 |
664 | 619 | bool to_host = cbw.cbw.flags & 0x80 |
665 | 620 | switch cbw.cbw.data[0]: |
... | ... | |
673 | 628 | case CBW::REQUEST_SENSE: |
674 | 629 | //Iris::debug ("sense requested\n") |
675 | 630 | send_padded ("\xf0\x00\x05\x00\x00\x00\x00\x00", 8, cbw.cbw.length) |
676 | | send_csw () |
677 | 631 | break |
678 | 632 | case CBW::FORMAT_UNIT: |
679 | 633 | Iris::panic (0, "FORMAT_UNIT isn't implemented") |
... | ... | |
682 | 636 | stall (2) |
683 | 637 | return |
684 | 638 | //Iris::debug ("sending inquiry response\t") |
| 639 | // TODO: find out why these bytes are messed up. |
685 | 640 | send_padded ("\x00\x00\x04\x02\x1f\x00\x00\x00shevek iris usb stick \x00\x00\x04\x02", 36, cbw.cbw.length) |
686 | | send_csw () |
687 | 641 | break |
688 | 642 | case CBW::RESERVE6: |
689 | 643 | Iris::panic (0, "RESERVE6 isn't implemented") |
... | ... | |
700 | 654 | capacity[1] = big_endian (1 << block_bits) |
701 | 655 | //Iris::debug ("sending capacity: %x * %x\t", capacity[0], capacity[1]) |
702 | 656 | send_padded ((char *)capacity, 8, cbw.cbw.length) |
703 | | send_csw () |
704 | 657 | break |
705 | 658 | case CBW::READ10: |
706 | | unsigned lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5] |
707 | | unsigned blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8] |
708 | | for unsigned i = 0; i < blocks; ++i: |
709 | | //Iris::debug ("reading block %d\n", lba + i) |
710 | | // read block lba + i. |
711 | | buffer_page.set_flags (Iris::Page::FRAME) |
712 | | block.get_block ((lba + i) << block_bits, 1 << block_bits, 0, buffer_page) |
713 | | for unsigned p = 0; p < 1 << block_bits; p += max_packet_size_bulk: |
714 | | //Iris::debug (" %d", p) |
715 | | UDC_INDEX = 2 |
716 | | for unsigned t = 0; t < max_packet_size_bulk; t += 4: |
717 | | UDC_FIFO (2) = ((unsigned *)buffer)[(p + t) >> 2] |
718 | | UDC_INCSR |= UDC_INCSR_INPKTRDY |
719 | | //Iris::debug ("\n") |
720 | | while true: |
721 | | Iris::register_interrupt (IRQ_UDC) |
722 | | Iris::wait_for_interrupt (IRQ_UDC) |
723 | | kdebug ("interrupt read10\n") |
724 | | unsigned usb = UDC_INTRUSB |
725 | | unsigned in = UDC_INTRIN |
726 | | unsigned out = UDC_INTROUT |
727 | | if usb & 4 || in & 1: |
728 | | //kdebug ("general interrupt read10\t") |
729 | | if !handle_interrupt (usb & 4, in & 1): |
730 | | return |
731 | | if out & 2: |
732 | | Iris::panic (0, "out interrupt while waiting for in") |
733 | | if in & 4: |
734 | | break |
735 | | send_csw () |
| 659 | if !to_host: |
| 660 | stall (2) |
| 661 | return |
| 662 | lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5] |
| 663 | blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8] |
| 664 | data_done = 0 |
| 665 | state = TX |
| 666 | handle_tx () |
736 | 667 | break |
737 | 668 | case CBW::WRITE10: |
738 | | unsigned lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5] |
739 | | unsigned blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8] |
740 | | for unsigned i = 0; i < blocks; ++i: |
741 | | //Iris::debug ("writing block %d\n", lba + i) |
742 | | // write block lba + i. |
743 | | buffer_page.set_flags (Iris::Page::FRAME) |
744 | | //Iris::debug ("@%x:", (lba + i) << block_bits) |
745 | | for unsigned p = 0; p < 1 << block_bits; p += max_packet_size_bulk: |
746 | | while true: |
747 | | Iris::register_interrupt (IRQ_UDC) |
748 | | Iris::wait_for_interrupt (IRQ_UDC) |
749 | | Iris::debug (".") |
750 | | unsigned usb = UDC_INTRUSB |
751 | | unsigned in = UDC_INTRIN |
752 | | unsigned out = UDC_INTROUT |
753 | | if usb & 4 || in & 1: |
754 | | if !handle_interrupt (usb & 4, in & 1): |
755 | | return |
756 | | if out & 2: |
757 | | break |
758 | | if in & 4: |
759 | | Iris::panic (0, "in interrupt while waiting for out") |
760 | | UDC_INDEX = 1 |
761 | | if !(UDC_OUTCSR & UDC_OUTCSR_OUTPKTRDY): |
762 | | Iris::panic (0, "no packet ready after out interrupt in write10") |
763 | | if UDC_OUTCOUNT != max_packet_size_bulk: |
764 | | Iris::panic (UDC_OUTCOUNT, "invalid packet size in write10") |
765 | | for unsigned t = 0; t < max_packet_size_bulk; t += 4: |
766 | | ((unsigned *)buffer)[(p + t) >> 2] = UDC_FIFO (1) |
767 | | //kdebug (" ") |
768 | | //kdebug_num (((unsigned *)buffer)[(p + t) >> 2], 8) |
769 | | UDC_OUTCSR &= ~UDC_OUTCSR_OUTPKTRDY |
770 | | //kdebug ("\n") |
771 | | //Iris::debug ("setting block %x@%x+%x\n", lba + i << block_bits, 0, 1 << block_bits) |
772 | | block.set_block ((lba + i) << block_bits, buffer_page, 1 << block_bits) |
773 | | send_csw () |
| 669 | if to_host: |
| 670 | stall (2) |
| 671 | return |
| 672 | lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5] |
| 673 | blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8] |
| 674 | if blocks == 0: |
| 675 | send_csw () |
| 676 | break |
| 677 | state = RX |
| 678 | data_done = 0 |
| 679 | buffer_page.set_flags (Iris::Page::FRAME) |
774 | 680 | break |
775 | 681 | case CBW::RESERVE10: |
776 | 682 | Iris::panic (0, "RESERVE10 isn't implemented") |
777 | 683 | case CBW::RELEASE10: |
778 | 684 | Iris::panic (0, "RELEASE10 isn't implemented") |
779 | 685 | default: |
780 | | Iris::debug ("cbw:") |
| 686 | #if 0 |
| 687 | Iris::debug ("unknown cbw:") |
781 | 688 | for unsigned i = 0; i < cbw.cbw.size; ++i: |
782 | 689 | kdebug_char (' ') |
783 | 690 | kdebug_num (cbw.cbw.data[i], 2) |
784 | 691 | Iris::debug ("\n") |
| 692 | #endif |
785 | 693 | residue = cbw.cbw.length |
786 | 694 | stall (1) |
787 | 695 | return |
788 | 696 | |
789 | | bool Udc::handle_interrupt (bool usb, bool in): |
790 | | if usb: |
791 | | //Iris::debug ("usb\t") |
792 | | // reset. |
793 | | irq_usb () |
794 | | return false |
795 | | if in: |
796 | | //Iris::debug ("control\t") |
797 | | // control request |
798 | | irq_in0 () |
799 | | return true |
800 | | |
801 | 697 | void Udc::interrupt (): |
802 | | Iris::debug ("interrupt\n") |
| 698 | //Iris::debug ("interrupt, state = %d\n", state) |
803 | 699 | while true: |
| 700 | bool action = false |
804 | 701 | unsigned usb = UDC_INTRUSB |
805 | 702 | unsigned in = UDC_INTRIN |
806 | | bool action = false |
| 703 | unsigned out = UDC_INTROUT |
| 704 | if usb & 4: |
| 705 | //Iris::debug ("reset\n") |
| 706 | reset () |
| 707 | action = true |
| 708 | if state == STALL && in & 4: |
| 709 | // This must be handled here, because the state can be changed by the control request. |
| 710 | //Iris::debug ("stalling\n") |
| 711 | in &= ~4 |
| 712 | if in & 1: |
| 713 | //Iris::debug ("control request\n") |
| 714 | irq_in0 () |
| 715 | action = true |
807 | 716 | if in & 4: |
808 | | Iris::panic (0, "data request during idle\n") |
809 | | if usb & 4 || in & 1: |
810 | | handle_interrupt (usb & 4, in & 1) |
| 717 | //Iris::debug ("in request\n") |
| 718 | // Notification of sent packet (or stall, but we don't do that on the in endpoint). |
| 719 | switch state: |
| 720 | case SENT_CSW: |
| 721 | // csw received. |
| 722 | state = IDLE |
| 723 | break |
| 724 | case TX: |
| 725 | handle_tx () |
| 726 | break |
| 727 | default: |
| 728 | Iris::panic (state, "invalid state for data send") |
| 729 | stall (2) |
| 730 | break |
811 | 731 | action = true |
812 | | unsigned out = UDC_INTROUT |
813 | 732 | if out & 2: |
814 | | irq_out () |
| 733 | //Iris::debug ("out request\n") |
| 734 | switch state: |
| 735 | case IDLE: |
| 736 | handle_cbw () |
| 737 | break |
| 738 | case RX: |
| 739 | handle_rx () |
| 740 | break |
| 741 | default: |
| 742 | stall (2) |
| 743 | Iris::panic (0, "invalid state for data receive") |
| 744 | break |
815 | 745 | action = true |
816 | 746 | if !action: |
817 | 747 | // No more interrupts to handle; this is normal, because we're looping until this happens. |