source/font.ccp |
| 1 | #pypp 0 |
| 2 | // Iris: micro-kernel for a capability-based operating system. |
| 3 | // source/font.ccp: Font manager. |
| 4 | // Copyright 2012 Bas Wijnen <wijnen@debian.org> |
| 5 | // |
| 6 | // This program is free software: you can redistribute it and/or modify |
| 7 | // it under the terms of the GNU General Public License as published by |
| 8 | // the Free Software Foundation, either version 3 of the License, or |
| 9 | // (at your option) any later version. |
| 10 | // |
| 11 | // This program is distributed in the hope that it will be useful, |
| 12 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | // GNU General Public License for more details. |
| 15 | // |
| 16 | // You should have received a copy of the GNU General Public License |
| 17 | // along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | |
| 19 | #include "devices.hh" |
| 20 | |
| 21 | #define screenw 320 |
| 22 | #define screenh 240 |
| 23 | |
| 24 | struct Glyph: |
| 25 | unsigned width, height, baseline |
| 26 | unsigned data[1] |
| 27 | |
| 28 | static Iris::Display display |
| 29 | static Iris::Caps caps, display_caps |
| 30 | static unsigned slot, num_glyphs |
| 31 | static unsigned long pages, base |
| 32 | static Glyph **glyphs |
| 33 | static char *fb |
| 34 | static unsigned x, y |
| 35 | |
| 36 | static unsigned read_int (unsigned addr): |
| 37 | return *reinterpret_cast <unsigned *> (addr) |
| 38 | |
| 39 | static void load_font (Iris::Block font): |
| 40 | unsigned long long size = font.get_size ().value () |
| 41 | pages = (size + PAGE_SIZE - 1) >> PAGE_BITS |
| 42 | caps = Iris::my_memory.create_caps (pages) |
| 43 | slot = caps.use () |
| 44 | for unsigned i = 0; i < size; i += PAGE_SIZE: |
| 45 | Iris::Page page = Iris::Cap (slot, i >> PAGE_BITS) |
| 46 | Iris::set_recv_arg (page) |
| 47 | font.get_block (i) |
| 48 | Iris::my_memory.map (page, base + i) |
| 49 | num_glyphs = read_int (base) |
| 50 | glyphs = reinterpret_cast <Glyph **> (base + sizeof (int)) |
| 51 | for unsigned i = 0; i < num_glyphs; ++i: |
| 52 | glyphs[i] = reinterpret_cast <Glyph *> (base + sizeof (int) + read_int (base + sizeof (int) + i * sizeof (int))) |
| 53 | |
| 54 | static void free_font (): |
| 55 | for unsigned i = 0; i < pages; ++i: |
| 56 | Iris::my_memory.destroy (Iris::Cap (slot, i)) |
| 57 | Iris::my_memory.destroy (caps) |
| 58 | Iris::free_slot (slot) |
| 59 | |
| 60 | static unsigned draw_char (char c, unsigned &w, unsigned &h): |
| 61 | if c >= num_glyphs: |
| 62 | c = num_glyphs - 1 |
| 63 | Glyph *g = glyphs[c] |
| 64 | w = g->width |
| 65 | h = g->height |
| 66 | for unsigned ty = 0; ty < h; ++ty: |
| 67 | unsigned py = ty + y - g->baseline |
| 68 | if py < 0 || py >= screenh: |
| 69 | continue |
| 70 | for unsigned tx = 0; tx < g->width; ++tx: |
| 71 | unsigned px = tx + x |
| 72 | if px < 0 || px >= screenw: |
| 73 | continue |
| 74 | unsigned p = g->data[ty * g->width + tx] |
| 75 | unsigned red = unsigned (p) & 0xff |
| 76 | unsigned green = unsigned (p >> 8) & 0xff |
| 77 | unsigned blue = unsigned (p >> 16) & 0xff |
| 78 | unsigned alpha = (unsigned (p >> 24) & 0xff) + 1 |
| 79 | if alpha == 0x100: |
| 80 | fb[(py * 320 + px) * 4 + 2] = red |
| 81 | fb[(py * 320 + px) * 4 + 1] = green |
| 82 | fb[(py * 320 + px) * 4 + 0] = blue |
| 83 | else: |
| 84 | unsigned unalpha = 256 - alpha |
| 85 | fb[(py * 320 + px) * 4 + 2] = (fb[(py * 320 + px) * 4 + 2] * unalpha + red * alpha) >> 8 |
| 86 | fb[(py * 320 + px) * 4 + 1] = (fb[(py * 320 + px) * 4 + 1] * unalpha + green * alpha) >> 8 |
| 87 | fb[(py * 320 + px) * 4 + 0] = (fb[(py * 320 + px) * 4 + 0] * unalpha + blue * alpha) >> 8 |
| 88 | return g->baseline |
| 89 | |
| 90 | static void get_size (char c, unsigned &w, unsigned &h, unsigned &b): |
| 91 | if c >= num_glyphs: |
| 92 | c = num_glyphs - 1 |
| 93 | Glyph *g = glyphs[c] |
| 94 | w = g->width |
| 95 | h = g->height |
| 96 | b = g->baseline |
| 97 | |
| 98 | Iris::Num start (): |
| 99 | x = 0 |
| 100 | y = 8 |
| 101 | // Random address which is large enough to store a huge file. |
| 102 | base = 0x40000000 |
| 103 | fb = reinterpret_cast <char *> (0x20000000) |
| 104 | Iris::Font self = Iris::my_receiver.create_capability (0) |
| 105 | Iris::my_parent.provide_capability <Iris::Font> (self.copy ()) |
| 106 | Iris::free_cap (self) |
| 107 | //display = Iris::my_parent.get_capability <Iris::Display> () |
| 108 | Iris::Block font = Iris::my_parent.get_capability <Iris::Block> () |
| 109 | load_font (font) |
| 110 | Iris::free_cap (font) |
| 111 | Iris::my_parent.init_done () |
| 112 | //display_caps = display.map_fb (reinterpret_cast <unsigned> (fb)) |
| 113 | bool have_display = false |
| 114 | while true: |
| 115 | Iris::wait () |
| 116 | switch Iris::recv.data[0].l: |
| 117 | case Iris::Font::SET_DISPLAY: |
| 118 | Iris::Cap reply = Iris::get_reply () |
| 119 | if have_display: |
| 120 | Iris::free_cap (display) |
| 121 | have_display = true |
| 122 | display = Iris::get_arg () |
| 123 | display_caps = display.map_fb (reinterpret_cast <unsigned> (fb)) |
| 124 | reply.invoke () |
| 125 | Iris::free_cap (reply) |
| 126 | break |
| 127 | case Iris::Font::LOAD_FONT: |
| 128 | free_font () |
| 129 | font = Iris::get_arg () |
| 130 | load_font (font) |
| 131 | Iris::free_cap (font) |
| 132 | Iris::recv.reply.invoke () |
| 133 | break |
| 134 | case Iris::Font::SETUP: |
| 135 | // TODO: interface needs to be defined. |
| 136 | Iris::recv.reply.invoke () |
| 137 | break |
| 138 | case Iris::Font::AT: |
| 139 | if Iris::recv.data[0].h & 1: |
| 140 | x += Iris::recv.data[1].l |
| 141 | if x > screenw: |
| 142 | x = 0 |
| 143 | y += 16 |
| 144 | if y + 16 > screenh + 8: |
| 145 | y = 8 |
| 146 | else: |
| 147 | x = Iris::recv.data[1].l |
| 148 | if Iris::recv.data[0].h & 2: |
| 149 | y += Iris::recv.data[1].h |
| 150 | if y + 16 > screenh + 8: |
| 151 | y = 8 |
| 152 | else: |
| 153 | y = Iris::recv.data[1].h |
| 154 | Iris::recv.reply.invoke () |
| 155 | break |
| 156 | case Iris::Font::WRITE: |
| 157 | Iris::Cap reply = Iris::get_reply () |
| 158 | unsigned w, h |
| 159 | unsigned b = draw_char (Iris::recv.data[1].l, w, h) |
| 160 | x += w |
| 161 | if x + w > screenw: |
| 162 | x = 0 |
| 163 | y += h |
| 164 | if y + h > screenh + b: |
| 165 | y = b |
| 166 | reply.invoke () |
| 167 | Iris::free_cap (reply) |
| 168 | break |
| 169 | case Iris::Font::GET_POS: |
| 170 | Iris::recv.reply.invoke (x, y) |
| 171 | break |
| 172 | case Iris::Font::GET_SIZE: |
| 173 | unsigned w, h, b |
| 174 | get_size (Iris::recv.data[1].l, w, h, b) |
| 175 | Iris::recv.reply.invoke (Iris::Num (b, h), w) |
| 176 | break |
| 177 | default: |
| 178 | Iris::panic (0, "invalid operation type for lcd") |
| 179 | break |
source/nanonote-gpio.ccp |
21 | 21 | #include "arch.hh" |
22 | 22 | #include "keys.hh" |
23 | 23 | |
24 | | //#define QI |
| 24 | #define QI |
25 | 25 | #define SCAN_INTERVAL HZ / 50 |
26 | 26 | |
27 | 27 | class DevKbd: |
... | ... | |
128 | 128 | { Key::Q, Key::W, Key::E, Key::R, Key::T, Key::Y, Key::U, Key::I }, |
129 | 129 | { Key::A, Key::S, Key::D, Key::F, Key::G, Key::H, Key::J, Key::K }, |
130 | 130 | { Key::ESCAPE, Key::Z, Key::X, Key::C, Key::V, Key::B, Key::N, Key::M }, |
131 | | { Key::TAB, Key::CAPS, Key::BACKSLASH, Key::QUOTE, Key::COMMA, Key::PERIOD, Key::SLASH, Key::UP }, |
132 | | { Key::O, Key::L, Key::EQUAL, Key::ARROW, Key::SPACE, Key::QI, Key::CTRL, Key::LEFT }, |
| 131 | { Key::TAB, Key::CAPS_LOCK, Key::BACKSLASH, Key::QUOTE, Key::COMMA, Key::PERIOD, Key::SLASH, Key::UP }, |
| 132 | { Key::O, Key::L, Key::EQUALS, Key::SPECIAL + 0, Key::SPACE, Key::RIGHT_LOGO, Key::RIGHT_CONTROL, Key::LEFT }, |
133 | 133 | { Key::F8, Key::P, Key::BACKSPACE, Key::ENTER, Key::VOLUME_UP, Key::VOLUME_DOWN, Key::DOWN, Key::RIGHT }, |
134 | | { Key::SHIFT, Key::ALT, Key::FN, ~0, ~0, ~0, ~0, ~0 } |
| 134 | { Key::LEFT_SHIFT, Key::LEFT_ALT, Key::FN, ~0, ~0, ~0, ~0, ~0 } |
135 | 135 | #else |
136 | 136 | { Key::ESCAPE, Key::TAB, Key::F1, Key::F2, Key::F3, Key::F4, Key::SPECIAL + 0, ~0 }, |
137 | 137 | { Key::N1, Key::N2, Key::N3, Key::N4, Key::N5, Key::N6, Key::N7, Key::N8 }, |
... | ... | |
149 | 149 | Key::Q, Key::W, Key::E, Key::R, Key::T, Key::Y, Key::U, Key::I, |
150 | 150 | Key::A, Key::S, Key::D, Key::F, Key::G, Key::H, Key::J, Key::K, |
151 | 151 | Key::ESCAPE, Key::Z, Key::X, Key::C, Key::V, Key::B, Key::N, Key::M, |
152 | | Key::TAB, Key::CAPS, Key::BACKSLASH, Key::QUOTE, Key::COMMA, Key::PERIOD, Key::SLASH, Key::UP, |
153 | | Key::O, Key::L, Key::EQUAL, Key::ARROW, Key::SPACE, Key::QI, Key::CTRL, Key::LEFT, |
| 152 | Key::TAB, Key::CAPS_LOCK, Key::BACKSLASH, Key::QUOTE, Key::COMMA, Key::PERIOD, Key::SLASH, Key::UP, |
| 153 | Key::O, Key::L, Key::EQUALS, Key::SPECIAL + 0, Key::SPACE, Key::RIGHT_LOGO, Key::RIGHT_CONTROL, Key::LEFT, |
154 | 154 | Key::F8, Key::P, Key::BACKSPACE, Key::ENTER, Key::VOLUME_UP, Key::VOLUME_DOWN, Key::DOWN, Key::RIGHT, |
155 | | Key::SHIFT, Key::ALT, Key::FN |
| 155 | Key::LEFT_SHIFT, Key::LEFT_ALT, Key::FN |
156 | 156 | #else |
157 | 157 | Key::ESCAPE, Key::TAB, Key::F1, Key::F2, Key::F3, Key::F4, Key::SPECIAL + 0, |
158 | 158 | Key::N1, Key::N2, Key::N3, Key::N4, Key::N5, Key::N6, Key::N7, Key::N8, |
... | ... | |
195 | 195 | scan () |
196 | 196 | |
197 | 197 | enum codes: |
198 | | KBD_DEV = 32 |
| 198 | KBD_DEV = 1 |
199 | 199 | PWR |
200 | 200 | SDMMC |
201 | 201 | |
... | ... | |
228 | 228 | Iris::my_receiver.set_alarm (SCAN_INTERVAL) |
229 | 229 | continue |
230 | 230 | switch Iris::recv.protected_data.l: |
231 | | case IRQ_GPIO3: |
| 231 | case 0: |
232 | 232 | // Interrupt. |
233 | 233 | pwr.scan () |
234 | 234 | kbd.scan () |
source/sd+mmc.ccp |
1 | | #pypp 0 |
2 | | // Iris: micro-kernel for a capability-based operating system. |
3 | | // source/sd+mmc.ccp: sd+mmc driver. |
4 | | // Copyright 2009 Bas Wijnen <wijnen@debian.org> |
5 | | // |
6 | | // This program is free software: you can redistribute it and/or modify |
7 | | // it under the terms of the GNU General Public License as published by |
8 | | // the Free Software Foundation, either version 3 of the License, or |
9 | | // (at your option) any later version. |
10 | | // |
11 | | // This program is distributed in the hope that it will be useful, |
12 | | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | | // GNU General Public License for more details. |
15 | | // |
16 | | // You should have received a copy of the GNU General Public License |
17 | | // along with this program. If not, see <http://www.gnu.org/licenses/>. |
18 | | |
19 | | #include "devices.hh" |
20 | | #define ARCH |
21 | | #include "arch.hh" |
22 | | |
23 | | class Mmc: |
24 | | public: |
25 | | enum Response_type: |
26 | | NONE = MSC_CMDAT_RESPONSE_NONE |
27 | | RD_DATA = MSC_CMDAT_RESPONSE_R1 | MSC_CMDAT_DATA_EN | MSC_CMDAT_READ |
28 | | WR_DATA = MSC_CMDAT_RESPONSE_R1 | MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE |
29 | | R1 = MSC_CMDAT_RESPONSE_R1 |
30 | | R1B = MSC_CMDAT_RESPONSE_R1 | MSC_CMDAT_BUSY |
31 | | R2 = MSC_CMDAT_RESPONSE_R2 |
32 | | R3 = MSC_CMDAT_RESPONSE_R3 |
33 | | R4 = MSC_CMDAT_RESPONSE_R4 |
34 | | R5 = MSC_CMDAT_RESPONSE_R5 |
35 | | R6 = MSC_CMDAT_RESPONSE_R6 |
36 | | R7 = MSC_CMDAT_RESPONSE_R7 |
37 | | static unsigned const POWER_PORT = 3 |
38 | | static unsigned const POWER_PIN = 2 |
39 | | struct CID: |
40 | | unsigned mid |
41 | | char oid[2] |
42 | | char pnm[5] |
43 | | unsigned prv |
44 | | unsigned psn |
45 | | unsigned year |
46 | | unsigned month |
47 | | struct CSD: |
48 | | unsigned c_size |
49 | | unsigned c_size_mult |
50 | | unsigned read_bl_len, write_bl_len |
51 | | bool copy |
52 | | bool perm_write_protect |
53 | | bool tmp_write_protect |
54 | | bool send (unsigned cmd, unsigned arg, Response_type response_type, unsigned *response = NULL) |
55 | | void check_sd () |
56 | | void check_sdmem () |
57 | | void check_mmc () |
58 | | public: |
59 | | void reset () |
60 | | void detect () |
61 | | void release () |
62 | | void interrupt () |
63 | | CID const &get_cid (): |
64 | | return cid |
65 | | unsigned get_num_blocks (): |
66 | | return num_blocks |
67 | | unsigned get_read_block_size (): |
68 | | return read_block_size |
69 | | unsigned get_block_bits (): |
70 | | return hc ? 9 : csd.read_bl_len > csd.write_bl_len ? csd.read_bl_len : csd.write_bl_len |
71 | | void write_page (Iris::Page page, Iris::Num address, unsigned size, unsigned offset) |
72 | | void read_page (Iris::Page page, Iris::Num address, unsigned size, unsigned offset) |
73 | | void wait_write () |
74 | | void add_cb (Iris::Listitem item): |
75 | | cb_list.add_item (item) |
76 | | private: |
77 | | void set_block (unsigned block) |
78 | | unsigned current_block_num |
79 | | bool dirty |
80 | | unsigned *current_block |
81 | | unsigned rca |
82 | | bool have_sdmem, have_io |
83 | | bool hc |
84 | | CID cid |
85 | | CSD csd |
86 | | unsigned num_blocks, read_block_size |
87 | | Iris::Page buffer_page |
88 | | Iris::List cb_list |
89 | | static unsigned const buffer = 0x15000 |
90 | | |
91 | | bool Mmc::send (unsigned cmd, unsigned arg, Response_type response_type, unsigned *response): |
92 | | MSC_CMD = cmd |
93 | | MSC_ARG = arg |
94 | | MSC_CMDAT = response_type |
95 | | MSC_IMASK = ~MSC_IMASK_END_CMD_RES |
96 | | Iris::register_interrupt (IRQ_MSC) |
97 | | msc_start_op () |
98 | | Iris::wait_for_interrupt (IRQ_MSC) |
99 | | MSC_IMASK = ~0 |
100 | | //kdebug ("cmd: ") |
101 | | //kdebug_num (cmd) |
102 | | unsigned stat = MSC_STAT |
103 | | //kdebug (", stat: ") |
104 | | //kdebug_num (stat) |
105 | | //kdebug ("\n") |
106 | | if stat & MSC_STAT_CRC_RES_ERR: |
107 | | Iris::panic (0, "crc error in mmc response") |
108 | | return false |
109 | | if stat & MSC_STAT_TIME_OUT_RES: |
110 | | kdebug ("time out waiting for mmc response\n") |
111 | | MSC_IREG = MSC_IREG_END_CMD_RES |
112 | | return false |
113 | | if response_type == R2: |
114 | | unsigned d = MSC_RES |
115 | | if d >> 8 != 0x3f: |
116 | | Iris::panic (d, "invalid r2 response") |
117 | | if cmd == 3: |
118 | | // Read out result. |
119 | | cid.mid = d & 0xff |
120 | | d = MSC_RES |
121 | | cid.oid[0] = d >> 8 |
122 | | cid.oid[1] = d & 0xff |
123 | | d = MSC_RES |
124 | | cid.pnm[0] = d >> 8 |
125 | | cid.pnm[1] = d & 0xff |
126 | | d = MSC_RES |
127 | | cid.pnm[2] = d >> 8 |
128 | | cid.pnm[3] = d & 0xff |
129 | | d = MSC_RES |
130 | | cid.pnm[4] = d >> 8 |
131 | | cid.prv = d & 0xff |
132 | | d = MSC_RES |
133 | | cid.psn = d << 16 |
134 | | d = MSC_RES |
135 | | cid.psn |= d |
136 | | d = MSC_RES |
137 | | cid.year = 2000 + (d >> 4 & 0xff) |
138 | | cid.month = d & 0xf |
139 | | #if 1 |
140 | | Iris::debug ("CID: mid=%x, oid=%x %x, pnm=%x %x %x %x %x, prv=%x, psn=%x, year=%x, month=%x\n", cid.mid, cid.oid[0], cid.oid[1], cid.pnm[0], cid.pnm[1], cid.pnm[2], cid.pnm[3], cid.pnm[4], cid.prv, cid.psn, cid.year, cid.month) |
141 | | #endif |
142 | | else: |
143 | | // Header (8) 1.0 1.0 |
144 | | // Read out csd. |
145 | | // Ignore csd_structure. 2 (+ 6) 1.0 2.0 *** |
146 | | d = MSC_RES |
147 | | // Ignore taac and nsac. 8 + 8 2.0 4.0 *** |
148 | | d = MSC_RES |
149 | | // Ignore tran_speed, ccc. 8 + 8/12 2.0 6.0 *** |
150 | | d = MSC_RES |
151 | | // Ignore rest of ccc. 4/12 0.4 6.4 |
152 | | // 4 0.4 7.0 |
153 | | csd.read_bl_len = (d >> 8) & 0xf |
154 | | // Ignore read_bl_partial, write_blk_misalign, read_blk_misalign, dsr_imp. 1 + 1 + 1 + 1 (+ 2) 0.6 7.6 |
155 | | // 2/12 0.2 8.0 *** |
156 | | csd.c_size = (d & 0x0003) << 10 |
157 | | d = MSC_RES |
158 | | // 10/12 1.2 9.2 |
159 | | csd.c_size |= d >> 6 |
160 | | // Ignore vdd_r_cur_min, vdd_r_cur_max. 3 + 3 0.6 10.0 *** |
161 | | d = MSC_RES |
162 | | // Ignore vdd_w_cur_min, vdd_w_cur_max. 3 + 3 0.6 10.6 |
163 | | // 3 0.3 11.1 |
164 | | csd.c_size_mult = (d >> 7) & 0x7 |
165 | | // Ignore erase_blk_enable, sector_size. 1 + 6/7 0.7 12.0 *** |
166 | | d = MSC_RES |
167 | | // Ignore rest of sector_size, wp_grp_size, wp_grp_enable, r2w_factor. 1/7 + 7 + 1 (+ 2) + 3 1.6 13.6 |
168 | | // 2/4 0.4 14.0 *** |
169 | | csd.write_bl_len = (d << 2) & 0xc |
170 | | d = MSC_RES |
171 | | // 2/4 0.2 14.2 |
172 | | csd.write_bl_len |= (d >> 14) & 0x3 |
173 | | // Ignore write_bl_partial, file_format_grp. 1 (+ 5) + 1 0.7 15.1 |
174 | | // 1 0.1 15.2 |
175 | | csd.copy = d & 0x40 |
176 | | // 1 0.1 15.3 |
177 | | csd.perm_write_protect = d & 0x20 |
178 | | // 1 0.1 15.4 |
179 | | csd.tmp_write_protect = d & 0x10 |
180 | | // Ignore file_format. 2 (+ 2) 0.4 16.0 *** |
181 | | read_block_size = hc ? 512 : 1 << csd.read_bl_len |
182 | | num_blocks = (csd.c_size + 1) << (csd.c_size_mult + 2) |
183 | | if hc: |
184 | | if csd.read_bl_len < 9: |
185 | | num_blocks >>= 9 - csd.read_bl_len |
186 | | else: |
187 | | num_blocks <<= csd.read_bl_len - 9 |
188 | | #if 1 |
189 | | Iris::debug ("CSD: size=%x<<%x, r/w len=%x/%x, %s, %s, %s\n", csd.c_size, csd.c_size_mult, csd.read_bl_len, csd.write_bl_len, csd.copy ? "copy" : "no copy", csd.perm_write_protect ? "fixed write protect" : "no fixed write protect", csd.tmp_write_protect ? "write protect" : "no write protect") |
190 | | #endif |
191 | | unsigned c_size |
192 | | unsigned c_size_mult |
193 | | unsigned read_bl_len, write_bl_len |
194 | | bool copy |
195 | | bool perm_write_protect |
196 | | bool tmp_write_protect |
197 | | else if response_type != NONE: |
198 | | unsigned r = MSC_RES |
199 | | if response_type == R3: |
200 | | if r >> 8 != 0x3f: |
201 | | Iris::panic (r, "r3 response was not 3f") |
202 | | else if r >> 8 != cmd: |
203 | | kdebug ("stat: ") |
204 | | kdebug_num (MSC_STAT) |
205 | | kdebug ("; response: ") |
206 | | kdebug_num (r) |
207 | | kdebug ("; cmd: ") |
208 | | kdebug_num (cmd) |
209 | | Iris::panic (r, "response doesn't match command") |
210 | | r <<= 24 |
211 | | r |= MSC_RES << 8 |
212 | | r |= MSC_RES & 0xff |
213 | | if response: |
214 | | *response = r |
215 | | else: |
216 | | //kdebug ("extra response fifo read: ") |
217 | | //for unsigned i = 0; i < 9; ++i: |
218 | | //kdebug (" ") |
219 | | //kdebug_num (MSC_RES, 4) |
220 | | //kdebug ("\n") |
221 | | MSC_IREG = MSC_IREG_END_CMD_RES |
222 | | return true |
223 | | |
224 | | void Mmc::reset (): |
225 | | current_block_num = ~0 |
226 | | dirty = false |
227 | | cb_list = Iris::my_memory.create_list () |
228 | | current_block = (unsigned *)(buffer + PAGE_SIZE) |
229 | | // Create a buffer to use for data transfer. |
230 | | buffer_page = Iris::my_memory.create_page () |
231 | | Iris::my_memory.map (buffer_page, buffer) |
232 | | // Reset all state, by faking a release event. |
233 | | release () |
234 | | // Enable 25 MHz clock to msc. |
235 | | CPM_MSCCDR = 13 |
236 | | cpm_start_msc () |
237 | | // Enable msc pins. |
238 | | gpio_as_msc () |
239 | | // Disable power to card. |
240 | | gpio_as_gpio (POWER_PORT, 1 << POWER_PIN) |
241 | | gpio_as_output (POWER_PORT, 1 << POWER_PIN) |
242 | | gpio_disable_pull (POWER_PORT, 1 << POWER_PIN) |
243 | | gpio_set (POWER_PORT, 1 << POWER_PIN) |
244 | | |
245 | | // Stop the clock. |
246 | | MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP |
247 | | while MSC_STAT & MSC_STAT_CLK_EN: |
248 | | //kdebug (",") |
249 | | Iris::sleep (1) |
250 | | |
251 | | // Reset controller and inserted devices. |
252 | | MSC_STRPCL = MSC_STRPCL_RESET |
253 | | while MSC_STAT & MSC_STAT_IS_RESETTING: |
254 | | //kdebug (":") |
255 | | Iris::sleep (1) |
256 | | |
257 | | // Initialize registers. |
258 | | MSC_CLKRT = MSC_CLKRT_CLK_RATE_DIV_1 |
259 | | MSC_RESTO = 64 |
260 | | MSC_RDTO = ~0 |
261 | | MSC_BLKLEN = 0x200 |
262 | | MSC_NOB = 0 |
263 | | MSC_IREG = ~0 |
264 | | MSC_IMASK = ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_RXFIFO_RD_REQ) |
265 | | MSC_ARG = 0 |
266 | | |
267 | | // Start the clock. |
268 | | MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START |
269 | | // Set cards, if any, to idle. |
270 | | send (0, 0, NONE) |
271 | | |
272 | | // Reset SDIO device, if any. Don't do this, because it breaks for some reason. |
273 | | //send (52, 0x88000c08, R5) |
274 | | |
275 | | void Mmc::check_mmc (): |
276 | | //kdebug ("checking mmc\n") |
277 | | // 1. SEND CMD1 (SEND_OP_CMD) TO VALIDATE VOLTAGE (THE GENERAL OCR VALUE IS 0X00FF88000). |
278 | | // 2. IF THE RESPONSE IS CORRECT, THEN CONTINUE, ELSE GOTO 9. |
279 | | // 3. IF THE INITIALIZATION HAS FINISHED, GO TO 5. (THE RESPONSE IS THE OCR REGISTER AND IT INCLUDES A STATUS INFORMATION BIT (BIT [31]). THIS STATUS BIT IS SET IF THE CARD POWER UP PROCEDURE HAS BEEN FINISHED. AS LONG AS THE CARD IS BUSY, THE CORRESPONDING BIT[31] IS SET TO LOW.) |
280 | | // 4. Send CMD1 (SEND_OP_CMD) to validate voltage, and then go to 3. |
281 | | // 5. Send CMD2 (ALL_SEND_CID) to get the card CID. |
282 | | // 6. If the response timeout occurs, goto 9. |
283 | | // 7. Send CMD3 (SET_RELATIVE_ADDR) to assign the card a RCA. |
284 | | |
285 | | void Mmc::check_sdmem (): |
286 | | kdebug ("checking sdmem\n") |
287 | | // 2. Send CMD55. Here the default RCA 0x0000 is used for CMD55. |
288 | | // 3. If the response is correct (CMD55 has response), then continue, else go to check MMC. |
289 | | unsigned code |
290 | | hc = false |
291 | | if send (8, 0x1aa, R7, &code) && (code & 0xff) == 0xaa: |
292 | | kdebug ("hc\n") |
293 | | hc = true |
294 | | if !send (55, 0, R1, &code): |
295 | | check_mmc () |
296 | | return |
297 | | // 4. Send ACMD41 (SD_SEND_OP_CMD) to validate voltage (the general OCR value is 0x00FF8000). |
298 | | if !send (41, hc ? 0x40800000 : 0x00800000, R3, &code): |
299 | | check_mmc () |
300 | | return |
301 | | // 5. If the initialization has finished, go to 7. (The response is the OCR register and it includes a status information bit (bit [31]). This status bit is set if the card power up procedure has been finished. As long as the card is busy, the corresponding bit[31] is set to LOW.) |
302 | | // 6. Send CMD55 and ACMD41 to validate voltage, and then go to 5. |
303 | | unsigned retries = 100 |
304 | | while !(code & (1 << 31)) && --retries: |
305 | | if !send (55, 0, R1, &code): |
306 | | return |
307 | | if !send (41, hc ? 0x40800000 : 0x00800000, R3, &code): |
308 | | return |
309 | | Iris::sleep (1) |
310 | | if !(code & (1 << 31)): |
311 | | Iris::panic (code, "card fails to finish setting up") |
312 | | // 7. Send CMD2 (ALL_SEND_CID) to get the card CID. |
313 | | if !send (2, 0, R2): |
314 | | Iris::panic (0, "card failed to send CID") |
315 | | // 8. Send CMD3 (SET_RELATIVE_ADDR) to let card publish a RCA. The RCA is returned from the response. |
316 | | // 9. If do not accept the new RCA, go to 8, else record the new RCA. |
317 | | rca = 0 |
318 | | while !rca: |
319 | | if !send (3, 0, R6, &rca): |
320 | | Iris::panic (0, "card failed to provide rca") |
321 | | rca &= 0xffff0000 |
322 | | kdebug ("received rca ") |
323 | | kdebug_num (rca >> 16, 4) |
324 | | kdebug ("\n") |
325 | | have_sdmem = true |
326 | | |
327 | | void Mmc::check_sd (): |
328 | | //kdebug ("checking sdio\n") |
329 | | if !send (0, 0, NONE): |
330 | | Iris::panic (0, "unable to reset cards?") |
331 | | // 2. Send CMD5 (IO_SEND_OP_CMD) to validate voltage. |
332 | | // 3. If the response is correct and the number of IO functions > 0, then continue, else go to check SDMEM. |
333 | | unsigned code |
334 | | if !send (5, 1 << 20, R4, &code) || !(code & (7 << 28)): |
335 | | check_sdmem () |
336 | | return |
337 | | // 4. If C-bit in the response is ready (the initialization has finished), go to 6. |
338 | | // 5. Send CMD5 (IO_SEND_OP_CMD) to validate voltage, then go to 4. |
339 | | while !(code & (1 << 31)): |
340 | | if !send (5, 1 << 20, R4, &code): |
341 | | Iris::panic (0, "invalid response to cmd 5") |
342 | | // 6. If memory-present-bit in the response is true, then it is a combo card (SDIO + Memory), else it is only a SDIO card. |
343 | | // 7. If it is a combo card, go to check SDMEM to initialize the memory part. |
344 | | have_io = true |
345 | | if code & (1 << 27): |
346 | | check_sdmem () |
347 | | return |
348 | | // 8. Send CMD3 (SET_RELATIVE_ADDR) to let the card publish a RCA. The RCA is returned from the response. |
349 | | // 9. If do not accept the new RCA, go to 8, else record the new RCA. |
350 | | rca = 0 |
351 | | while rca == 0: |
352 | | if !send (3, 0, R6, &rca): |
353 | | Iris::panic (0, "unable to set rca") |
354 | | rca &= 0xffff0000 |
355 | | check_mmc () |
356 | | |
357 | | void Mmc::detect (): |
358 | | kdebug ("mmc detect\n") |
359 | | gpio_clear (POWER_PORT, 1 << POWER_PIN) |
360 | | check_sd () |
361 | | check_mmc () |
362 | | if have_sdmem: |
363 | | if !send (9, rca, R2): |
364 | | Iris::panic (0, "unable to request csd") |
365 | | if !send (7, rca, R1B): |
366 | | Iris::panic (0, "unable to select sdmem") |
367 | | kdebug ("found device; size = ") |
368 | | kdebug_num (num_blocks) |
369 | | kdebug (" * ") |
370 | | kdebug_num (read_block_size) |
371 | | kdebug (" = ") |
372 | | kdebug_num (num_blocks * read_block_size) |
373 | | kdebug ("\n") |
374 | | // Set up buffer memory. |
375 | | for unsigned i = 0; i < 1 << csd.write_bl_len; i += PAGE_SIZE: |
376 | | Iris::Page p = Iris::my_memory.create_page () |
377 | | p.set_flags (Iris::Page::PAYING | Iris::Page::FRAME) |
378 | | Iris::my_memory.map (p, (unsigned)current_block + i) |
379 | | Iris::free_cap (p) |
380 | | Iris::Listitem item = cb_list.get_next () |
381 | | while item.code != Iris::Cap ().code: |
382 | | Iris::Cap c = cb_list.get_cap (item) |
383 | | c.invoke (0, ~0) |
384 | | Iris::free_cap (c) |
385 | | Iris::Listitem nextitem = cb_list.get_next (item); |
386 | | Iris::free_cap (item) |
387 | | item = nextitem |
388 | | |
389 | | void Mmc::release (): |
390 | | kdebug ("mmc release\n") |
391 | | gpio_set (POWER_PORT, 1 << POWER_PIN) |
392 | | have_sdmem = false |
393 | | have_io = false |
394 | | read_block_size = 0 |
395 | | if num_blocks != 0: |
396 | | for unsigned i = 0; i < 1 << csd.write_bl_len; i += PAGE_SIZE: |
397 | | Iris::Page p = Iris::my_memory.mapping ((void *)((unsigned)current_block + i)) |
398 | | Iris::my_memory.destroy (p) |
399 | | Iris::free_cap (p) |
400 | | if dirty: |
401 | | Iris::debug ("Warning: sd/mmc card removed before data was written to it") |
402 | | current_block_num = ~0 |
403 | | dirty = false |
404 | | num_blocks = 0 |
405 | | Iris::Listitem item = cb_list.get_next () |
406 | | while item.code != Iris::Cap ().code: |
407 | | Iris::Cap c = cb_list.get_cap (item) |
408 | | c.invoke (0, ~0) |
409 | | Iris::free_cap (c) |
410 | | Iris::Listitem nextitem = cb_list.get_next (item); |
411 | | Iris::free_cap (item) |
412 | | item = nextitem |
413 | | |
414 | | void Mmc::interrupt (): |
415 | | kdebug ("mmc interrupt\n") |
416 | | |
417 | | void Mmc::set_block (unsigned block): |
418 | | if current_block_num == block: |
419 | | return |
420 | | if dirty && current_block_num != ~0: |
421 | | MSC_NOB = 1 |
422 | | MSC_BLKLEN = 1 << csd.write_bl_len |
423 | | if !send (24, (current_block_num << csd.write_bl_len), WR_DATA): |
424 | | Iris::panic (0, "unable to send data") |
425 | | MSC_IMASK = ~MSC_IMASK_TXFIFO_WR_REQ |
426 | | for unsigned a = 0; a < 1 << csd.write_bl_len; a += 4: |
427 | | while MSC_STAT & MSC_STAT_DATA_FIFO_FULL: |
428 | | Iris::register_interrupt (IRQ_MSC) |
429 | | Iris::wait_for_interrupt (IRQ_MSC) |
430 | | MSC_TXFIFO = current_block[a >> 2] |
431 | | MSC_IMASK = ~0 |
432 | | MSC_IREG = MSC_IREG_DATA_TRAN_DONE |
433 | | //kdebug ("done writing page\n") |
434 | | current_block_num = block |
435 | | dirty = false |
436 | | MSC_NOB = 1 |
437 | | MSC_BLKLEN = 1 << 9 |
438 | | for unsigned a = 0; a < 1 << csd.write_bl_len; a += 1 << 9: |
439 | | if !send (17, (block << csd.write_bl_len) + a, RD_DATA): |
440 | | Iris::panic (0, "unable to request data") |
441 | | MSC_IMASK = ~MSC_IMASK_RXFIFO_RD_REQ |
442 | | for unsigned aa = 0; aa < 1 << 9; aa += 4: |
443 | | while MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY: |
444 | | Iris::register_interrupt (IRQ_MSC) |
445 | | Iris::wait_for_interrupt (IRQ_MSC) |
446 | | current_block[(a + aa) >> 2] = MSC_RXFIFO |
447 | | MSC_IMASK = ~0 |
448 | | MSC_IREG = MSC_IREG_DATA_TRAN_DONE |
449 | | //kdebug ("done filling page\n") |
450 | | |
451 | | void Mmc::read_page (Iris::Page page, Iris::Num address, unsigned size, unsigned offset): |
452 | | if address.value () >> (csd.write_bl_len + 32): |
453 | | Iris::panic (address.h, "page too high: not supported") |
454 | | unsigned block = address.value () >> csd.write_bl_len |
455 | | unsigned start_pos = address.l & (1 << csd.write_bl_len) - 1 |
456 | | set_block (block) |
457 | | unsigned blockmask = ~((1 << 9) - 1) |
458 | | size &= blockmask |
459 | | offset &= ~PAGE_MASK & ~3 |
460 | | if size + offset > PAGE_SIZE: |
461 | | size = PAGE_SIZE - offset |
462 | | page.share (buffer_page) |
463 | | buffer_page.set_flags (Iris::Page::PAYING | Iris::Page::FRAME) |
464 | | for unsigned i = 0; i < size; i += 4: |
465 | | ((unsigned *)buffer)[(offset + i) >> 2] = current_block[(start_pos + i) >> 2] |
466 | | |
467 | | void Mmc::write_page (Iris::Page page, Iris::Num address, unsigned size, unsigned offset): |
468 | | if address.value () >> (csd.write_bl_len + 32): |
469 | | Iris::panic (address.h, "page too high: not supported") |
470 | | unsigned block = address.value () >> csd.write_bl_len |
471 | | unsigned start_pos = address.l & (1 << csd.write_bl_len) - 1 |
472 | | set_block (block) |
473 | | unsigned blockmask = ~((1 << 9) - 1) |
474 | | size &= blockmask |
475 | | offset &= ~PAGE_MASK & ~3 |
476 | | if size + offset > PAGE_SIZE: |
477 | | size = PAGE_SIZE - offset |
478 | | page.share (buffer_page) |
479 | | buffer_page.set_flags (Iris::Page::PAYING | Iris::Page::FRAME) |
480 | | for unsigned i = 0; i < size; i += 4: |
481 | | current_block[(start_pos + i) >> 2] = ((unsigned *)buffer)[(offset + i) >> 2] |
482 | | dirty = true |
483 | | |
484 | | void Mmc::wait_write (): |
485 | | MSC_IMASK = ~MSC_IMASK_PRG_DONE |
486 | | while !MSC_STAT & MSC_STAT_PRG_DONE: |
487 | | Iris::register_interrupt (IRQ_MSC) |
488 | | Iris::wait_for_interrupt (IRQ_MSC) |
489 | | MSC_IREG = MSC_IREG_PRG_DONE |
490 | | |
491 | | static Mmc mmc |
492 | | |
493 | | enum types: |
494 | | DETECT |
495 | | REQUEST |
496 | | |
497 | | Iris::Num start (): |
498 | | map_msc () |
499 | | map_gpio () |
500 | | map_cpm () |
501 | | |
502 | | mmc.reset () |
503 | | |
504 | | Iris::Event detect = Iris::my_parent.get_capability <Iris::Event> () |
505 | | Iris::Cap cap = Iris::my_receiver.create_capability (DETECT) |
506 | | detect.set_cb (cap.copy ()) |
507 | | cap.invoke (~0) |
508 | | Iris::free_cap (cap) |
509 | | |
510 | | // Get a message from the queue. This is either the "there is no card" message, or the message we just sent. |
511 | | Iris::wait () |
512 | | if Iris::recv.data[0].l != ~0: |
513 | | // If it was "there is no card", the message we sent is still in the queue. |
514 | | Iris::wait () |
515 | | else: |
516 | | // Otherwise, there is a card. |
517 | | mmc.detect () |
518 | | |
519 | | cap = Iris::my_receiver.create_capability (REQUEST) |
520 | | Iris::my_parent.provide_capability <Iris::WBlock> (cap.copy ()) |
521 | | Iris::free_cap (cap) |
522 | | |
523 | | Iris::my_parent.init_done () |
524 | | |
525 | | while true: |
526 | | Iris::wait () |
527 | | switch Iris::recv.protected_data.l: |
528 | | case DETECT: |
529 | | if Iris::recv.data[0].l: |
530 | | mmc.detect () |
531 | | else: |
532 | | mmc.release () |
533 | | break |
534 | | case IRQ_MSC: |
535 | | mmc.interrupt () |
536 | | break |
537 | | case REQUEST: |
538 | | //kdebug ("sd+mmc request ") |
539 | | //kdebug_num (Iris::recv.data[0].l) |
540 | | //kdebug ("\n") |
541 | | switch Iris::recv.data[0].l: |
542 | | case Iris::Block::GET_SIZE: |
543 | | Iris::debug ("get size\n") |
544 | | unsigned long long size = mmc.get_num_blocks () * mmc.get_read_block_size () |
545 | | Iris::recv.reply.invoke (size) |
546 | | break |
547 | | case Iris::Block::GET_ALIGN_BITS: |
548 | | Iris::debug ("get align bits\n") |
549 | | Iris::recv.reply.invoke (9) |
550 | | break |
551 | | case Iris::Block::GET_BLOCK: |
552 | | //Iris::debug ("get block\n") |
553 | | Iris::Cap reply = Iris::get_reply () |
554 | | Iris::Page page = Iris::get_arg () |
555 | | mmc.read_page (page, Iris::recv.data[1], Iris::recv.data[0].h >> 16, Iris::recv.data[0].h & 0xffff) |
556 | | reply.invoke () |
557 | | Iris::free_cap (page) |
558 | | Iris::free_cap (reply) |
559 | | break |
560 | | case Iris::WBlock::SET_BLOCK: |
561 | | Iris::debug ("set block\n") |
562 | | Iris::Cap reply = Iris::get_reply () |
563 | | Iris::Page page = Iris::get_arg () |
564 | | mmc.write_page (page, Iris::recv.data[1], Iris::recv.data[0].h >> 16, Iris::recv.data[0].h & 0xffff) |
565 | | reply.invoke () |
566 | | Iris::free_cap (page) |
567 | | Iris::free_cap (reply) |
568 | | mmc.wait_write () |
569 | | break |
570 | | case Iris::Block::SET_CHANGE_CB: |
571 | | Iris::debug ("set change cb\n") |
572 | | Iris::Listitem item = Iris::get_arg () |
573 | | Iris::Cap reply = Iris::get_reply () |
574 | | mmc.add_cb (item) |
575 | | reply.invoke () |
576 | | Iris::free_cap (item) |
577 | | Iris::free_cap (reply) |
578 | | break |
579 | | case Iris::WBlock::TRUNCATE: |
580 | | Iris::debug ("truncate\n") |
581 | | // Fall through: don't support resizing. |
582 | | default: |
583 | | Iris::panic (0, "unexpected event for sd+mmc") |
584 | | break |
585 | | default: |
586 | | Iris::panic (0, "unexpected request source for sd+mmc") |
source/sdmmc.ccp |
| 1 | #pypp 0 |
| 2 | // Iris: micro-kernel for a capability-based operating system. |
| 3 | // source/sd+mmc.ccp: sd+mmc driver. |
| 4 | // Copyright 2009 Bas Wijnen <wijnen@debian.org> |
| 5 | // |
| 6 | // This program is free software: you can redistribute it and/or modify |
| 7 | // it under the terms of the GNU General Public License as published by |
| 8 | // the Free Software Foundation, either version 3 of the License, or |
| 9 | // (at your option) any later version. |
| 10 | // |
| 11 | // This program is distributed in the hope that it will be useful, |
| 12 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | // GNU General Public License for more details. |
| 15 | // |
| 16 | // You should have received a copy of the GNU General Public License |
| 17 | // along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | |
| 19 | #include "devices.hh" |
| 20 | #define ARCH |
| 21 | #include "arch.hh" |
| 22 | |
| 23 | class Mmc: |
| 24 | public: |
| 25 | enum Response_type: |
| 26 | NONE = MSC_CMDAT_RESPONSE_NONE |
| 27 | RD_DATA = MSC_CMDAT_RESPONSE_R1 | MSC_CMDAT_DATA_EN | MSC_CMDAT_READ |
| 28 | WR_DATA = MSC_CMDAT_RESPONSE_R1 | MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE |
| 29 | R1 = MSC_CMDAT_RESPONSE_R1 |
| 30 | R1B = MSC_CMDAT_RESPONSE_R1 | MSC_CMDAT_BUSY |
| 31 | R2 = MSC_CMDAT_RESPONSE_R2 |
| 32 | R3 = MSC_CMDAT_RESPONSE_R3 |
| 33 | R4 = MSC_CMDAT_RESPONSE_R4 |
| 34 | R5 = MSC_CMDAT_RESPONSE_R5 |
| 35 | R6 = MSC_CMDAT_RESPONSE_R6 |
| 36 | R7 = MSC_CMDAT_RESPONSE_R7 |
| 37 | static unsigned const POWER_PORT = 3 |
| 38 | static unsigned const POWER_PIN = 2 |
| 39 | struct CID: |
| 40 | unsigned mid |
| 41 | char oid[2] |
| 42 | char pnm[5] |
| 43 | unsigned prv |
| 44 | unsigned psn |
| 45 | unsigned year |
| 46 | unsigned month |
| 47 | struct CSD: |
| 48 | unsigned c_size |
| 49 | unsigned c_size_mult |
| 50 | unsigned read_bl_len, write_bl_len |
| 51 | bool copy |
| 52 | bool perm_write_protect |
| 53 | bool tmp_write_protect |
| 54 | bool send (unsigned cmd, unsigned arg, Response_type response_type, unsigned *response = NULL) |
| 55 | void check_sd () |
| 56 | void check_sdmem () |
| 57 | void check_mmc () |
| 58 | public: |
| 59 | void reset () |
| 60 | void detect () |
| 61 | void release () |
| 62 | void interrupt () |
| 63 | CID const &get_cid (): |
| 64 | return cid |
| 65 | unsigned get_num_blocks (): |
| 66 | return num_blocks |
| 67 | unsigned get_read_block_size (): |
| 68 | return read_block_size |
| 69 | unsigned get_block_bits (): |
| 70 | return hc ? 9 : csd.read_bl_len > csd.write_bl_len ? csd.read_bl_len : csd.write_bl_len |
| 71 | void write_page (Iris::Page page, Iris::Num address, unsigned size, unsigned offset) |
| 72 | void read_page (Iris::Page page, Iris::Num address, unsigned size, unsigned offset) |
| 73 | void wait_write () |
| 74 | void add_cb (Iris::Listitem item): |
| 75 | cb_list.add_item (item) |
| 76 | private: |
| 77 | void set_block (unsigned block) |
| 78 | unsigned current_block_num |
| 79 | bool dirty |
| 80 | unsigned *current_block |
| 81 | unsigned rca |
| 82 | bool have_sdmem, have_io |
| 83 | bool hc |
| 84 | CID cid |
| 85 | CSD csd |
| 86 | unsigned num_blocks, read_block_size |
| 87 | Iris::Page buffer_page |
| 88 | Iris::List cb_list |
| 89 | static unsigned const buffer = 0x15000 |
| 90 | |
| 91 | bool Mmc::send (unsigned cmd, unsigned arg, Response_type response_type, unsigned *response): |
| 92 | MSC_CMD = cmd |
| 93 | MSC_ARG = arg |
| 94 | MSC_CMDAT = response_type |
| 95 | MSC_IMASK = ~MSC_IMASK_END_CMD_RES |
| 96 | Iris::register_interrupt (IRQ_MSC) |
| 97 | msc_start_op () |
| 98 | Iris::wait_for_interrupt () |
| 99 | MSC_IMASK = ~0 |
| 100 | //kdebug ("cmd: ") |
| 101 | //kdebug_num (cmd) |
| 102 | unsigned stat = MSC_STAT |
| 103 | //kdebug (", stat: ") |
| 104 | //kdebug_num (stat) |
| 105 | //kdebug ("\n") |
| 106 | if stat & MSC_STAT_CRC_RES_ERR: |
| 107 | Iris::panic (0, "crc error in mmc response") |
| 108 | return false |
| 109 | if stat & MSC_STAT_TIME_OUT_RES: |
| 110 | kdebug ("time out waiting for mmc response\n") |
| 111 | MSC_IREG = MSC_IREG_END_CMD_RES |
| 112 | return false |
| 113 | if response_type == R2: |
| 114 | unsigned d = MSC_RES |
| 115 | if d >> 8 != 0x3f: |
| 116 | Iris::panic (d, "invalid r2 response") |
| 117 | if cmd == 3: |
| 118 | // Read out result. |
| 119 | cid.mid = d & 0xff |
| 120 | d = MSC_RES |
| 121 | cid.oid[0] = d >> 8 |
| 122 | cid.oid[1] = d & 0xff |
| 123 | d = MSC_RES |
| 124 | cid.pnm[0] = d >> 8 |
| 125 | cid.pnm[1] = d & 0xff |
| 126 | d = MSC_RES |
| 127 | cid.pnm[2] = d >> 8 |
| 128 | cid.pnm[3] = d & 0xff |
| 129 | d = MSC_RES |
| 130 | cid.pnm[4] = d >> 8 |
| 131 | cid.prv = d & 0xff |
| 132 | d = MSC_RES |
| 133 | cid.psn = d << 16 |
| 134 | d = MSC_RES |
| 135 | cid.psn |= d |
| 136 | d = MSC_RES |
| 137 | cid.year = 2000 + (d >> 4 & 0xff) |
| 138 | cid.month = d & 0xf |
| 139 | #if 1 |
| 140 | Iris::debug ("CID: mid=%x, oid=%x %x, pnm=%x %x %x %x %x, prv=%x, psn=%x, year=%x, month=%x\n", cid.mid, cid.oid[0], cid.oid[1], cid.pnm[0], cid.pnm[1], cid.pnm[2], cid.pnm[3], cid.pnm[4], cid.prv, cid.psn, cid.year, cid.month) |
| 141 | #endif |
| 142 | else: |
| 143 | // Header (8) 1.0 1.0 |
| 144 | // Read out csd. |
| 145 | // Ignore csd_structure. 2 (+ 6) 1.0 2.0 *** |
| 146 | d = MSC_RES |
| 147 | // Ignore taac and nsac. 8 + 8 2.0 4.0 *** |
| 148 | d = MSC_RES |
| 149 | // Ignore tran_speed, ccc. 8 + 8/12 2.0 6.0 *** |
| 150 | d = MSC_RES |
| 151 | // Ignore rest of ccc. 4/12 0.4 6.4 |
| 152 | // 4 0.4 7.0 |
| 153 | csd.read_bl_len = (d >> 8) & 0xf |
| 154 | // Ignore read_bl_partial, write_blk_misalign, read_blk_misalign, dsr_imp. 1 + 1 + 1 + 1 (+ 2) 0.6 7.6 |
| 155 | // 2/12 0.2 8.0 *** |
| 156 | csd.c_size = (d & 0x0003) << 10 |
| 157 | d = MSC_RES |
| 158 | // 10/12 1.2 9.2 |
| 159 | csd.c_size |= d >> 6 |
| 160 | // Ignore vdd_r_cur_min, vdd_r_cur_max. 3 + 3 0.6 10.0 *** |
| 161 | d = MSC_RES |
| 162 | // Ignore vdd_w_cur_min, vdd_w_cur_max. 3 + 3 0.6 10.6 |
| 163 | // 3 0.3 11.1 |
| 164 | csd.c_size_mult = (d >> 7) & 0x7 |
| 165 | // Ignore erase_blk_enable, sector_size. 1 + 6/7 0.7 12.0 *** |
| 166 | d = MSC_RES |
| 167 | // Ignore rest of sector_size, wp_grp_size, wp_grp_enable, r2w_factor. 1/7 + 7 + 1 (+ 2) + 3 1.6 13.6 |
| 168 | // 2/4 0.4 14.0 *** |
| 169 | csd.write_bl_len = (d << 2) & 0xc |
| 170 | d = MSC_RES |
| 171 | // 2/4 0.2 14.2 |
| 172 | csd.write_bl_len |= (d >> 14) & 0x3 |
| 173 | // Ignore write_bl_partial, file_format_grp. 1 (+ 5) + 1 0.7 15.1 |
| 174 | // 1 0.1 15.2 |
| 175 | csd.copy = d & 0x40 |
| 176 | // 1 0.1 15.3 |
| 177 | csd.perm_write_protect = d & 0x20 |
| 178 | // 1 0.1 15.4 |
| 179 | csd.tmp_write_protect = d & 0x10 |
| 180 | // Ignore file_format. 2 (+ 2) 0.4 16.0 *** |
| 181 | read_block_size = hc ? 512 : 1 << csd.read_bl_len |
| 182 | num_blocks = (csd.c_size + 1) << (csd.c_size_mult + 2) |
| 183 | if hc: |
| 184 | if csd.read_bl_len < 9: |
| 185 | num_blocks >>= 9 - csd.read_bl_len |
| 186 | else: |
| 187 | num_blocks <<= csd.read_bl_len - 9 |
| 188 | #if 1 |
| 189 | Iris::debug ("CSD: size=%x<<%x, r/w len=%x/%x, %s, %s, %s\n", csd.c_size, csd.c_size_mult, csd.read_bl_len, csd.write_bl_len, csd.copy ? "copy" : "no copy", csd.perm_write_protect ? "fixed write protect" : "no fixed write protect", csd.tmp_write_protect ? "write protect" : "no write protect") |
| 190 | #endif |
| 191 | unsigned c_size |
| 192 | unsigned c_size_mult |
| 193 | unsigned read_bl_len, write_bl_len |
| 194 | bool copy |
| 195 | bool perm_write_protect |
| 196 | bool tmp_write_protect |
| 197 | else if response_type != NONE: |
| 198 | unsigned r = MSC_RES |
| 199 | if response_type == R3: |
| 200 | if r >> 8 != 0x3f: |
| 201 | Iris::panic (r, "r3 response was not 3f") |
| 202 | else if r >> 8 != cmd: |
| 203 | kdebug ("stat: ") |
| 204 | kdebug_num (MSC_STAT) |
| 205 | kdebug ("; response: ") |
| 206 | kdebug_num (r) |
| 207 | kdebug ("; cmd: ") |
| 208 | kdebug_num (cmd) |
| 209 | Iris::panic (r, "response doesn't match command") |
| 210 | r <<= 24 |
| 211 | r |= MSC_RES << 8 |
| 212 | r |= MSC_RES & 0xff |
| 213 | if response: |
| 214 | *response = r |
| 215 | else: |
| 216 | //kdebug ("extra response fifo read: ") |
| 217 | //for unsigned i = 0; i < 9; ++i: |
| 218 | //kdebug (" ") |
| 219 | //kdebug_num (MSC_RES, 4) |
| 220 | //kdebug ("\n") |
| 221 | MSC_IREG = MSC_IREG_END_CMD_RES |
| 222 | return true |
| 223 | |
| 224 | void Mmc::reset (): |
| 225 | current_block_num = ~0 |
| 226 | dirty = false |
| 227 | cb_list = Iris::my_memory.create_list () |
| 228 | current_block = (unsigned *)(buffer + PAGE_SIZE) |
| 229 | // Create a buffer to use for data transfer. |
| 230 | buffer_page = Iris::my_memory.create_page () |
| 231 | Iris::my_memory.map (buffer_page, buffer) |
| 232 | // Reset all state, by faking a release event. |
| 233 | release () |
| 234 | // Enable 25 MHz clock to msc. |
| 235 | CPM_MSCCDR = 13 |
| 236 | cpm_start_msc () |
| 237 | // Enable msc pins. |
| 238 | gpio_as_msc () |
| 239 | // Disable power to card. |
| 240 | gpio_as_gpio (POWER_PORT, 1 << POWER_PIN) |
| 241 | gpio_as_output (POWER_PORT, 1 << POWER_PIN) |
| 242 | gpio_disable_pull (POWER_PORT, 1 << POWER_PIN) |
| 243 | gpio_set (POWER_PORT, 1 << POWER_PIN) |
| 244 | |
| 245 | // Stop the clock. |
| 246 | MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP |
| 247 | while MSC_STAT & MSC_STAT_CLK_EN: |
| 248 | //kdebug (",") |
| 249 | Iris::sleep (1) |
| 250 | |
| 251 | // Reset controller and inserted devices. |
| 252 | MSC_STRPCL = MSC_STRPCL_RESET |
| 253 | while MSC_STAT & MSC_STAT_IS_RESETTING: |
| 254 | //kdebug (":") |
| 255 | Iris::sleep (1) |
| 256 | |
| 257 | // Initialize registers. |
| 258 | MSC_CLKRT = MSC_CLKRT_CLK_RATE_DIV_1 |
| 259 | MSC_RESTO = 64 |
| 260 | MSC_RDTO = ~0 |
| 261 | MSC_BLKLEN = 0x200 |
| 262 | MSC_NOB = 0 |
| 263 | MSC_IREG = ~0 |
| 264 | MSC_IMASK = ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_RXFIFO_RD_REQ) |
| 265 | MSC_ARG = 0 |
| 266 | |
| 267 | // Start the clock. |
| 268 | MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START |
| 269 | // Set cards, if any, to idle. |
| 270 | send (0, 0, NONE) |
| 271 | |
| 272 | // Reset SDIO device, if any. Don't do this, because it breaks for some reason. |
| 273 | //send (52, 0x88000c08, R5) |
| 274 | |
| 275 | void Mmc::check_mmc (): |
| 276 | //kdebug ("checking mmc\n") |
| 277 | // 1. SEND CMD1 (SEND_OP_CMD) TO VALIDATE VOLTAGE (THE GENERAL OCR VALUE IS 0X00FF88000). |
| 278 | // 2. IF THE RESPONSE IS CORRECT, THEN CONTINUE, ELSE GOTO 9. |
| 279 | // 3. IF THE INITIALIZATION HAS FINISHED, GO TO 5. (THE RESPONSE IS THE OCR REGISTER AND IT INCLUDES A STATUS INFORMATION BIT (BIT [31]). THIS STATUS BIT IS SET IF THE CARD POWER UP PROCEDURE HAS BEEN FINISHED. AS LONG AS THE CARD IS BUSY, THE CORRESPONDING BIT[31] IS SET TO LOW.) |
| 280 | // 4. Send CMD1 (SEND_OP_CMD) to validate voltage, and then go to 3. |
| 281 | // 5. Send CMD2 (ALL_SEND_CID) to get the card CID. |
| 282 | // 6. If the response timeout occurs, goto 9. |
| 283 | // 7. Send CMD3 (SET_RELATIVE_ADDR) to assign the card a RCA. |
| 284 | |
| 285 | void Mmc::check_sdmem (): |
| 286 | kdebug ("checking sdmem\n") |
| 287 | // 2. Send CMD55. Here the default RCA 0x0000 is used for CMD55. |
| 288 | // 3. If the response is correct (CMD55 has response), then continue, else go to check MMC. |
| 289 | unsigned code |
| 290 | hc = false |
| 291 | if send (8, 0x1aa, R7, &code) && (code & 0xff) == 0xaa: |
| 292 | kdebug ("hc\n") |
| 293 | hc = true |
| 294 | if !send (55, 0, R1, &code): |
| 295 | check_mmc () |
| 296 | return |
| 297 | // 4. Send ACMD41 (SD_SEND_OP_CMD) to validate voltage (the general OCR value is 0x00FF8000). |
| 298 | if !send (41, hc ? 0x40800000 : 0x00800000, R3, &code): |
| 299 | check_mmc () |
| 300 | return |
| 301 | // 5. If the initialization has finished, go to 7. (The response is the OCR register and it includes a status information bit (bit [31]). This status bit is set if the card power up procedure has been finished. As long as the card is busy, the corresponding bit[31] is set to LOW.) |
| 302 | // 6. Send CMD55 and ACMD41 to validate voltage, and then go to 5. |
| 303 | unsigned retries = 100 |
| 304 | while !(code & (1 << 31)) && --retries: |
| 305 | if !send (55, 0, R1, &code): |
| 306 | return |
| 307 | if !send (41, hc ? 0x40800000 : 0x00800000, R3, &code): |
| 308 | return |
| 309 | Iris::sleep (1) |
| 310 | if !(code & (1 << 31)): |
| 311 | Iris::panic (code, "card fails to finish setting up") |
| 312 | // 7. Send CMD2 (ALL_SEND_CID) to get the card CID. |
| 313 | if !send (2, 0, R2): |
| 314 | Iris::panic (0, "card failed to send CID") |
| 315 | // 8. Send CMD3 (SET_RELATIVE_ADDR) to let card publish a RCA. The RCA is returned from the response. |
| 316 | // 9. If do not accept the new RCA, go to 8, else record the new RCA. |
| 317 | rca = 0 |
| 318 | while !rca: |
| 319 | if !send (3, 0, R6, &rca): |
| 320 | Iris::panic (0, "card failed to provide rca") |
| 321 | rca &= 0xffff0000 |
| 322 | kdebug ("received rca ") |
| 323 | kdebug_num (rca >> 16, 4) |
| 324 | kdebug ("\n") |
| 325 | have_sdmem = true |
| 326 | |
| 327 | void Mmc::check_sd (): |
| 328 | //kdebug ("checking sdio\n") |
| 329 | if !send (0, 0, NONE): |
| 330 | Iris::panic (0, "unable to reset cards?") |
| 331 | // 2. Send CMD5 (IO_SEND_OP_CMD) to validate voltage. |
| 332 | // 3. If the response is correct and the number of IO functions > 0, then continue, else go to check SDMEM. |
| 333 | unsigned code |
| 334 | if !send (5, 1 << 20, R4, &code) || !(code & (7 << 28)): |
| 335 | check_sdmem () |
| 336 | return |
| 337 | // 4. If C-bit in the response is ready (the initialization has finished), go to 6. |
| 338 | // 5. Send CMD5 (IO_SEND_OP_CMD) to validate voltage, then go to 4. |
| 339 | while !(code & (1 << 31)): |
| 340 | if !send (5, 1 << 20, R4, &code): |
| 341 | Iris::panic (0, "invalid response to cmd 5") |
| 342 | // 6. If memory-present-bit in the response is true, then it is a combo card (SDIO + Memory), else it is only a SDIO card. |
| 343 | // 7. If it is a combo card, go to check SDMEM to initialize the memory part. |
| 344 | have_io = true |
| 345 | if code & (1 << 27): |
| 346 | check_sdmem () |
| 347 | return |
| 348 | // 8. Send CMD3 (SET_RELATIVE_ADDR) to let the card publish a RCA. The RCA is returned from the response. |
| 349 | // 9. If do not accept the new RCA, go to 8, else record the new RCA. |
| 350 | rca = 0 |
| 351 | while rca == 0: |
| 352 | if !send (3, 0, R6, &rca): |
| 353 | Iris::panic (0, "unable to set rca") |
| 354 | rca &= 0xffff0000 |
| 355 | check_mmc () |
| 356 | |
| 357 | void Mmc::detect (): |
| 358 | kdebug ("mmc detect\n") |
| 359 | gpio_clear (POWER_PORT, 1 << POWER_PIN) |
| 360 | check_sd () |
| 361 | check_mmc () |
| 362 | if have_sdmem: |
| 363 | if !send (9, rca, R2): |
| 364 | Iris::panic (0, "unable to request csd") |
| 365 | if !send (7, rca, R1B): |
| 366 | Iris::panic (0, "unable to select sdmem") |
| 367 | kdebug ("found device; size = ") |
| 368 | kdebug_num (num_blocks) |
| 369 | kdebug (" * ") |
| 370 | kdebug_num (read_block_size) |
| 371 | kdebug (" = ") |
| 372 | kdebug_num (num_blocks * read_block_size) |
| 373 | kdebug ("\n") |
| 374 | // Set up buffer memory. |
| 375 | for unsigned i = 0; i < 1 << csd.write_bl_len; i += PAGE_SIZE: |
| 376 | Iris::Page p = Iris::my_memory.create_page () |
| 377 | p.set_flags (Iris::Page::PAYING | Iris::Page::FRAME) |
| 378 | Iris::my_memory.map (p, (unsigned)current_block + i) |
| 379 | Iris::free_cap (p) |
| 380 | Iris::Listitem item = cb_list.get_next () |
| 381 | while item.code != Iris::Cap ().code: |
| 382 | Iris::Cap c = cb_list.get_cap (item) |
| 383 | c.invoke (0, ~0) |
| 384 | Iris::free_cap (c) |
| 385 | Iris::Listitem nextitem = cb_list.get_next (item); |
| 386 | Iris::free_cap (item) |
| 387 | item = nextitem |
| 388 | |
| 389 | void Mmc::release (): |
| 390 | kdebug ("mmc release\n") |
| 391 | gpio_set (POWER_PORT, 1 << POWER_PIN) |
| 392 | have_sdmem = false |
| 393 | have_io = false |
| 394 | read_block_size = 0 |
| 395 | if num_blocks != 0: |
| 396 | for unsigned i = 0; i < 1 << csd.write_bl_len; i += PAGE_SIZE: |
| 397 | Iris::Page p = Iris::my_memory.mapping ((void *)((unsigned)current_block + i)) |
| 398 | Iris::my_memory.destroy (p) |
| 399 | Iris::free_cap (p) |
| 400 | if dirty: |
| 401 | Iris::debug ("Warning: sd/mmc card removed before data was written to it") |
| 402 | current_block_num = ~0 |
| 403 | dirty = false |
| 404 | num_blocks = 0 |
| 405 | Iris::Listitem item = cb_list.get_next () |
| 406 | while item.code != Iris::Cap ().code: |
| 407 | Iris::Cap c = cb_list.get_cap (item) |
| 408 | c.invoke (0, ~0) |
| 409 | Iris::free_cap (c) |
| 410 | Iris::Listitem nextitem = cb_list.get_next (item); |
| 411 | Iris::free_cap (item) |
| 412 | item = nextitem |
| 413 | |
| 414 | void Mmc::interrupt (): |
| 415 | kdebug ("mmc interrupt\n") |
| 416 | |
| 417 | void Mmc::set_block (unsigned block): |
| 418 | if current_block_num == block: |
| 419 | return |
| 420 | if dirty && current_block_num != ~0: |
| 421 | MSC_NOB = 1 |
| 422 | MSC_BLKLEN = 1 << csd.write_bl_len |
| 423 | if !send (24, (current_block_num << csd.write_bl_len), WR_DATA): |
| 424 | Iris::panic (0, "unable to send data") |
| 425 | MSC_IMASK = ~MSC_IMASK_TXFIFO_WR_REQ |
| 426 | for unsigned a = 0; a < 1 << csd.write_bl_len; a += 4: |
| 427 | while MSC_STAT & MSC_STAT_DATA_FIFO_FULL: |
| 428 | Iris::register_interrupt (IRQ_MSC) |
| 429 | Iris::wait_for_interrupt () |
| 430 | MSC_TXFIFO = current_block[a >> 2] |
| 431 | MSC_IMASK = ~0 |
| 432 | MSC_IREG = MSC_IREG_DATA_TRAN_DONE |
| 433 | //kdebug ("done writing page\n") |
| 434 | current_block_num = block |
| 435 | dirty = false |
| 436 | MSC_NOB = 1 |
| 437 | MSC_BLKLEN = 1 << 9 |
| 438 | for unsigned a = 0; a < 1 << csd.write_bl_len; a += 1 << 9: |
| 439 | if !send (17, (block << csd.write_bl_len) + a, RD_DATA): |
| 440 | Iris::panic (0, "unable to request data") |
| 441 | MSC_IMASK = ~MSC_IMASK_RXFIFO_RD_REQ |
| 442 | for unsigned aa = 0; aa < 1 << 9; aa += 4: |
| 443 | while MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY: |
| 444 | Iris::register_interrupt (IRQ_MSC) |
| 445 | Iris::wait_for_interrupt () |
| 446 | current_block[(a + aa) >> 2] = MSC_RXFIFO |
| 447 | MSC_IMASK = ~0 |
| 448 | MSC_IREG = MSC_IREG_DATA_TRAN_DONE |
| 449 | //kdebug ("done filling page\n") |
| 450 | |
| 451 | void Mmc::read_page (Iris::Page page, Iris::Num address, unsigned size, unsigned offset): |
| 452 | if address.value () >> (csd.write_bl_len + 32): |
| 453 | Iris::panic (address.h, "page too high: not supported") |
| 454 | unsigned block = address.value () >> csd.write_bl_len |
| 455 | unsigned start_pos = address.l & (1 << csd.write_bl_len) - 1 |
| 456 | set_block (block) |
| 457 | unsigned blockmask = ~((1 << 9) - 1) |
| 458 | size &= blockmask |
| 459 | offset &= ~PAGE_MASK & ~3 |
| 460 | if size + offset > PAGE_SIZE: |
| 461 | size = PAGE_SIZE - offset |
| 462 | page.share (buffer_page) |
| 463 | buffer_page.set_flags (Iris::Page::PAYING | Iris::Page::FRAME) |
| 464 | for unsigned i = 0; i < size; i += 4: |
| 465 | ((unsigned *)buffer)[(offset + i) >> 2] = current_block[(start_pos + i) >> 2] |
| 466 | |
| 467 | void Mmc::write_page (Iris::Page page, Iris::Num address, unsigned size, unsigned offset): |
| 468 | if address.value () >> (csd.write_bl_len + 32): |
| 469 | Iris::panic (address.h, "page too high: not supported") |
| 470 | unsigned block = address.value () >> csd.write_bl_len |
| 471 | unsigned start_pos = address.l & (1 << csd.write_bl_len) - 1 |
| 472 | set_block (block) |
| 473 | unsigned blockmask = ~((1 << 9) - 1) |
| 474 | size &= blockmask |
| 475 | offset &= ~PAGE_MASK & ~3 |
| 476 | if size + offset > PAGE_SIZE: |
| 477 | size = PAGE_SIZE - offset |
| 478 | page.share (buffer_page) |
| 479 | buffer_page.set_flags (Iris::Page::PAYING | Iris::Page::FRAME) |
| 480 | for unsigned i = 0; i < size; i += 4: |
| 481 | current_block[(start_pos + i) >> 2] = ((unsigned *)buffer)[(offset + i) >> 2] |
| 482 | dirty = true |
| 483 | |
| 484 | void Mmc::wait_write (): |
| 485 | MSC_IMASK = ~MSC_IMASK_PRG_DONE |
| 486 | while !MSC_STAT & MSC_STAT_PRG_DONE: |
| 487 | Iris::register_interrupt (IRQ_MSC) |
| 488 | Iris::wait_for_interrupt () |
| 489 | MSC_IREG = MSC_IREG_PRG_DONE |
| 490 | |
| 491 | static Mmc mmc |
| 492 | |
| 493 | enum types: |
| 494 | DETECT = 1 |
| 495 | REQUEST |
| 496 | |
| 497 | Iris::Num start (): |
| 498 | map_msc () |
| 499 | map_gpio () |
| 500 | map_cpm () |
| 501 | |
| 502 | mmc.reset () |
| 503 | |
| 504 | Iris::Event detect = Iris::my_parent.get_capability <Iris::Event> () |
| 505 | Iris::Cap cap = Iris::my_receiver.create_capability (DETECT) |
| 506 | detect.set_cb (cap.copy ()) |
| 507 | cap.invoke (~0) |
| 508 | Iris::free_cap (cap) |
| 509 | |
| 510 | // Get a message from the queue. This is either the "there is no card" message, or the message we just sent. |
| 511 | Iris::wait () |
| 512 | if Iris::recv.data[0].l != ~0: |
| 513 | // If it was "there is no card", the message we sent is still in the queue. |
| 514 | Iris::wait () |
| 515 | else: |
| 516 | // Otherwise, there is a card. |
| 517 | mmc.detect () |
| 518 | |
| 519 | cap = Iris::my_receiver.create_capability (REQUEST) |
| 520 | Iris::my_parent.provide_capability <Iris::WBlock> (cap.copy ()) |
| 521 | Iris::free_cap (cap) |
| 522 | |
| 523 | Iris::my_parent.init_done () |
| 524 | |
| 525 | while true: |
| 526 | Iris::wait () |
| 527 | switch Iris::recv.protected_data.l: |
| 528 | case 0: |
| 529 | mmc.interrupt () |
| 530 | break |
| 531 | case DETECT: |
| 532 | if Iris::recv.data[0].l: |
| 533 | mmc.detect () |
| 534 | else: |
| 535 | mmc.release () |
| 536 | break |
| 537 | case REQUEST: |
| 538 | //kdebug ("sd+mmc request ") |
| 539 | //kdebug_num (Iris::recv.data[0].l) |
| 540 | //kdebug ("\n") |
| 541 | switch Iris::recv.data[0].l: |
| 542 | case Iris::Block::GET_SIZE: |
| 543 | Iris::debug ("get size\n") |
| 544 | unsigned long long size = mmc.get_num_blocks () * mmc.get_read_block_size () |
| 545 | Iris::recv.reply.invoke (size) |
| 546 | break |
| 547 | case Iris::Block::GET_ALIGN_BITS: |
| 548 | Iris::debug ("get align bits\n") |
| 549 | Iris::recv.reply.invoke (9) |
| 550 | break |
| 551 | case Iris::Block::GET_BLOCK: |
| 552 | //Iris::debug ("get block\n") |
| 553 | Iris::Cap reply = Iris::get_reply () |
| 554 | Iris::Page page = Iris::get_arg () |
| 555 | mmc.read_page (page, Iris::recv.data[1], Iris::recv.data[0].h >> 16, Iris::recv.data[0].h & 0xffff) |
| 556 | reply.invoke () |
| 557 | Iris::free_cap (page) |
| 558 | Iris::free_cap (reply) |
| 559 | break |
| 560 | case Iris::WBlock::SET_BLOCK: |
| 561 | Iris::debug ("set block\n") |
| 562 | Iris::Cap reply = Iris::get_reply () |
| 563 | Iris::Page page = Iris::get_arg () |
| 564 | mmc.write_page (page, Iris::recv.data[1], Iris::recv.data[0].h >> 16, Iris::recv.data[0].h & 0xffff) |
| 565 | reply.invoke () |
| 566 | Iris::free_cap (page) |
| 567 | Iris::free_cap (reply) |
| 568 | mmc.wait_write () |
| 569 | break |
| 570 | case Iris::Block::SET_CHANGE_CB: |
| 571 | Iris::debug ("set change cb\n") |
| 572 | Iris::Listitem item = Iris::get_arg () |
| 573 | Iris::Cap reply = Iris::get_reply () |
| 574 | mmc.add_cb (item) |
| 575 | reply.invoke () |
| 576 | Iris::free_cap (item) |
| 577 | Iris::free_cap (reply) |
| 578 | break |
| 579 | case Iris::WBlock::TRUNCATE: |
| 580 | Iris::debug ("truncate\n") |
| 581 | // Fall through: don't support resizing. |
| 582 | default: |
| 583 | Iris::panic (0, "unexpected event for sd+mmc") |
| 584 | break |
| 585 | default: |
| 586 | Iris::panic (0, "unexpected request source for sd+mmc") |
source/usb-mass-storage.ccp |
1 | | #pypp 0 |
2 | | // Iris: micro-kernel for a capability-based operating system. |
3 | | // source/usb-mass-storage.ccp: USB mass storage device driver. |
4 | | // Copyright 2009-2010 Bas Wijnen <wijnen@debian.org> |
5 | | // |
6 | | // This program is free software: you can redistribute it and/or modify |
7 | | // it under the terms of the GNU General Public License as published by |
8 | | // the Free Software Foundation, either version 3 of the License, or |
9 | | // (at your option) any later version. |
10 | | // |
11 | | // This program is distributed in the hope that it will be useful, |
12 | | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | | // GNU General Public License for more details. |
15 | | // |
16 | | // You should have received a copy of the GNU General Public License |
17 | | // along with this program. If not, see <http://www.gnu.org/licenses/>. |
18 | | |
19 | | #include "iris.hh" |
20 | | #include "devices.hh" |
21 | | #define ARCH |
22 | | #include "arch.hh" |
23 | | |
24 | | #if 0 |
25 | | States and expected interrupts: |
26 | | |
27 | | IDLE: after reset or csw. |
28 | | IN interrupt: csw received, do nothing. |
29 | | OUT interrupt: cbw; handle |
30 | | -> IDLE (no data; csw sent) |
31 | | -> TX (send) |
32 | | -> RX (receive packets) |
33 | | TX: transmitting data. |
34 | | IN interrupt: host received data; send more. |
35 | | -> TX (more to send) |
36 | | RX: receiving data. |
37 | | OUT interrupt: host sent data; handle. |
38 | | -> RX (more to receive) |
39 | | -> IDLE (done receiving; send csw) |
40 | | #endif |
41 | | |
42 | | extern "C": |
43 | | void *memset (char *s, int c, unsigned long n): |
44 | | Iris::debug ("memset called: %x %x->%x\n", s, n, c) |
45 | | for unsigned i = 0; i < n; ++i: |
46 | | s[i] = c |
47 | | return s |
48 | | |
49 | | class Udc: |
50 | | typedef unsigned char u8 |
51 | | typedef unsigned short u16 |
52 | | typedef unsigned int u32 |
53 | | typedef u8 string |
54 | | // The ugly stuff is because pypp doesn't support __attribute__. |
55 | | /**/struct Setup { |
56 | | u8 request_type; |
57 | | u8 request; |
58 | | u16 value; |
59 | | u16 index; |
60 | | u16 length; |
61 | | } __attribute__ ((packed)) |
62 | | /**/struct Device { |
63 | | static u8 const Type = 1; |
64 | | u8 length; |
65 | | u8 type; |
66 | | u16 usb_version; |
67 | | u8 dev_class; |
68 | | u8 subclass; |
69 | | u8 protocol; |
70 | | u8 max_packet_size0; |
71 | | u16 vendor; |
72 | | u16 product; |
73 | | u16 dev_version; |
74 | | string s_manufacturer; |
75 | | string s_product; |
76 | | string s_serial; |
77 | | u8 num_configurations; |
78 | | } __attribute__ ((packed)) |
79 | | /**/struct Configuration { |
80 | | static u8 const Type = 2; |
81 | | u8 length; |
82 | | u8 type; |
83 | | u16 total_length; |
84 | | u8 num_interfaces; |
85 | | u8 configuration_value; |
86 | | u8 configuration; |
87 | | u8 attributes; |
88 | | u8 max_power; |
89 | | } __attribute__ ((packed)) |
90 | | /**/struct Interface { |
91 | | static u8 const Type = 4; |
92 | | u8 length; |
93 | | u8 type; |
94 | | u8 interface; |
95 | | u8 alternate; |
96 | | u8 num_endpoints; |
97 | | u8 iface_class; |
98 | | u8 subclass; |
99 | | u8 protocol; |
100 | | string name; |
101 | | } __attribute__ ((packed)) |
102 | | /**/struct Endpoint { |
103 | | static u8 const Type = 5; |
104 | | u8 length; |
105 | | u8 type; |
106 | | u8 address; |
107 | | u8 attributes; |
108 | | u16 max_packet_size; |
109 | | u8 interval; |
110 | | } __attribute__ ((packed)) |
111 | | /**/struct Device_Qualifier { |
112 | | static u8 const Type = 6; |
113 | | u8 length; |
114 | | u8 type; |
115 | | u16 version; |
116 | | u8 dev_class; |
117 | | u8 subclass; |
118 | | u8 protocol; |
119 | | u8 max_packet_size0; |
120 | | u8 num_configurations; |
121 | | u8 reserved; |
122 | | } __attribute__ ((packed)) |
123 | | /**/struct Langs { |
124 | | static u8 const Type = 3; |
125 | | u8 length; |
126 | | u8 type; |
127 | | u8 lang; |
128 | | } __attribute__ ((packed)) |
129 | | template <unsigned size> struct String { |
130 | | static u8 const Type = 3; |
131 | | u8 length; |
132 | | u8 type; |
133 | | u16 data[size]; |
134 | | } __attribute__ ((packed)) |
135 | | /**/struct CBW { |
136 | | u32 sig; |
137 | | u32 tag; |
138 | | u32 length; |
139 | | u8 flags; |
140 | | u8 lun; |
141 | | u8 size; |
142 | | u8 data[16]; |
143 | | enum Code { |
144 | | TEST_UNIT_READY = 0x00, |
145 | | REQUEST_SENSE = 0x03, |
146 | | FORMAT_UNIT = 0x04, |
147 | | INQUIRY = 0x12, |
148 | | RESERVE6 = 0x16, |
149 | | RELEASE6 = 0x17, |
150 | | SEND_DIAGNOSTIC = 0x1d, |
151 | | READ_CAPACITY = 0x25, |
152 | | READ10 = 0x28, |
153 | | WRITE10 = 0x2a, |
154 | | RESERVE10 = 0x56, |
155 | | RELEASE10 = 0x57 |
156 | | }; |
157 | | } __attribute__ ((packed)) |
158 | | static unsigned const max_packet_size0 = 64 |
159 | | static unsigned const max_packet_size_bulk = 64 |
160 | | enum Requests: |
161 | | GET_STATUS = 0 |
162 | | CLEAR_FEATURE = 1 |
163 | | SET_FEATURE = 3 |
164 | | SET_ADDRESS = 5 |
165 | | GET_DESCRIPTOR = 6 |
166 | | SET_DESCRIPTOR = 7 |
167 | | GET_CONFIGURATION = 8 |
168 | | SET_CONFIGURATION = 9 |
169 | | GET_INTERFACE = 10 |
170 | | SET_INTERFACE = 11 |
171 | | SYNCH_FRAME = 12 |
172 | | enum Storage_requests: |
173 | | BULK_ONLY_RESET = 0xff |
174 | | GET_MAX_LUN = 0xfe |
175 | | enum Request_types: |
176 | | STANDARD_TO_DEVICE = 0 |
177 | | CLASS_TO_DEVICE = 0x20 |
178 | | VENDOR_TO_DEVICE = 0x40 |
179 | | STANDARD_TO_INTERFACE = 1 |
180 | | CLASS_TO_INTERFACE = 0x21 |
181 | | VENDOR_TO_INTERFACE = 0x41 |
182 | | STANDARD_TO_ENDPOINT = 2 |
183 | | CLASS_TO_ENDPOINT = 0x22 |
184 | | VENDOR_TO_ENDPOINT = 0x42 |
185 | | STANDARD_FROM_DEVICE = 0x80 |
186 | | CLASS_FROM_DEVICE = 0xa0 |
187 | | VENDOR_FROM_DEVICE = 0xc0 |
188 | | STANDARD_FROM_INTERFACE = 0x81 |
189 | | CLASS_FROM_INTERFACE = 0xa1 |
190 | | VENDOR_FROM_INTERFACE = 0xc1 |
191 | | STANDARD_FROM_ENDPOINT = 0x82 |
192 | | CLASS_FROM_ENDPOINT = 0xa2 |
193 | | VENDOR_FROM_ENDPOINT = 0xc2 |
194 | | enum Endpoint_types: |
195 | | CONTROL = 0 |
196 | | ISOCHRONOUS = 1 |
197 | | BULK = 2 |
198 | | INTERRUPT = 3 |
199 | | enum Endpoint_features: |
200 | | ENDPOINT_HALT = 0 |
201 | | /**/struct my_config { |
202 | | Configuration config; |
203 | | Interface interface; |
204 | | Endpoint endpoint[2]; |
205 | | } __attribute__ ((packed)) |
206 | | static Device device_descriptor |
207 | | //static Device_Qualifier device_qualifier_descriptor |
208 | | static my_config config_descriptor; //, other_config_descriptor |
209 | | static String <1> s_langs |
210 | | static String <6> s_manufacturer |
211 | | static String <16> s_product |
212 | | static String <12> s_serial |
213 | | char configuration |
214 | | unsigned get_descriptor (unsigned type, unsigned idx, unsigned len) |
215 | | unsigned handle_setup (Setup *s) |
216 | | void reset () |
217 | | void irq_in0 () |
218 | | void handle_rx () |
219 | | void handle_tx () |
220 | | void handle_cbw () |
221 | | void send_csw () |
222 | | unsigned big_endian (unsigned src) |
223 | | bool handle_interrupt (bool usb, bool in) |
224 | | void stall (unsigned error) |
225 | | bool stalling |
226 | | enum State: |
227 | | IDLE |
228 | | TX |
229 | | RX |
230 | | SENT_CSW |
231 | | STALL |
232 | | State state |
233 | | unsigned residue |
234 | | unsigned status |
235 | | unsigned tag |
236 | | unsigned data_done, lba, blocks |
237 | | unsigned block_bits |
238 | | Iris::WBlock block |
239 | | Iris::Page buffer_page |
240 | | // A random address to map the buffer. |
241 | | static unsigned const buffer = 0x15000 |
242 | | public: |
243 | | void init (Iris::WBlock b) |
244 | | void log (unsigned c) |
245 | | void interrupt () |
246 | | void send (unsigned ep, char const *data, unsigned length, unsigned maxlength) |
247 | | void send_padded (char const *data, unsigned length, unsigned maxlength) |
248 | | |
249 | | Udc::Device Udc::device_descriptor |
250 | | Udc::my_config Udc::config_descriptor |
251 | | Udc::String <1> Udc::s_langs |
252 | | Udc::String <6> Udc::s_manufacturer |
253 | | Udc::String <16> Udc::s_product |
254 | | Udc::String <12> Udc::s_serial |
255 | | |
256 | | void Udc::reset (): |
257 | | // Reset. |
258 | | UDC_TESTMODE = 0 |
259 | | configuration = 0 |
260 | | state = IDLE |
261 | | status = 0 |
262 | | residue = 0 |
263 | | // enable interrupt on bus reset. |
264 | | UDC_INTRUSBE = UDC_INTR_RESET |
265 | | // enable interrupts on endpoint 0 and in endpoint 2 |
266 | | UDC_INTRINE = 1 << 0 | 1 << 2 |
267 | | // and on out endpoint 1. |
268 | | UDC_INTROUTE = 1 << 1 |
269 | | // exit suspend mode by reading the interrupt register. |
270 | | unsigned i = UDC_INTRUSB |
271 | | // reset all pending endpoint interrupts. |
272 | | i = UDC_INTRIN |
273 | | i = UDC_INTROUT |
274 | | UDC_INDEX = 1 |
275 | | UDC_OUTMAXP = max_packet_size_bulk |
276 | | // Do this twice to flush a double-buffered fifo completely. |
277 | | UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
278 | | UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
279 | | UDC_INDEX = 2 |
280 | | UDC_INMAXP = max_packet_size_bulk |
281 | | UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF |
282 | | UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF |
283 | | //Iris::debug ("usb reset\n") |
284 | | |
285 | | void Udc::init (Iris::WBlock b): |
286 | | block = b |
287 | | block_bits = block.get_align_bits () |
288 | | // Set up the buffer page. |
289 | | buffer_page = Iris::my_memory.create_page () |
290 | | buffer_page.set_flags (Iris::Page::PAYING) |
291 | | Iris::my_memory.map (buffer_page, buffer) |
292 | | // Initialize the globals. My method of compiling doesn't handle global constructors. |
293 | | device_descriptor = (Device){ sizeof (Device), Device::Type, 0x200, 0, 0, 0, max_packet_size0, 0xfffe, 0x0002, 0x100, 1, 2, 3, 1 } |
294 | | config_descriptor = (my_config){ |
295 | | (Configuration){ sizeof (Configuration), Configuration::Type, sizeof (my_config), 1, 1, 0, 0xc0, 30 }, |
296 | | (Interface){ sizeof (Interface), Interface::Type, 0, 0, 2, 0x8, 0x6, 0x50, 0 }, { |
297 | | (Endpoint){ sizeof (Endpoint), Endpoint::Type, 1, BULK, max_packet_size_bulk, 0 }, |
298 | | (Endpoint){ sizeof (Endpoint), Endpoint::Type, 0x82, BULK, max_packet_size_bulk, 0 } |
299 | | } |
300 | | } |
301 | | s_langs = (String <1>){ sizeof (String <1>), String <1>::Type, { 0x0409 } } |
302 | | s_manufacturer = (String <6>){ sizeof (String <6>), String <6>::Type, { 's', 'h', 'e', 'v', 'e', 'k' } } |
303 | | s_product = (String <16>){ sizeof (String <16>), String <16>::Type, { 'I', 'r', 'i', 's', ' ', 'o', 'n', ' ', 'N', 'a', 'n', 'o', 'N', 'o', 't', 'e' } } |
304 | | s_serial = (String <12>){ sizeof (String <12>), String <12>::Type, { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B' } } |
305 | | |
306 | | cpm_start_udc () |
307 | | // Disconnect from the bus and don't try to get high-speed. |
308 | | UDC_POWER = 0 |
309 | | reset () |
310 | | // Wait a while. |
311 | | Iris::sleep (HZ / 10) |
312 | | // Connect to the host. |
313 | | UDC_POWER = UDC_POWER_SOFTCONN |
314 | | |
315 | | void Udc::send (unsigned ep, char const *data, unsigned length, unsigned maxlength): |
316 | | if maxlength < length: |
317 | | length = maxlength |
318 | | unsigned i |
319 | | for i = 0; (length - i & ~3) > 0 && i < length; i += 4: |
320 | | UDC_FIFO (ep) = ((unsigned *)data)[i / 4] |
321 | | //kdebug_num (((unsigned *)data)[i / 4], 8) |
322 | | //kdebug (" ") |
323 | | for ; i < length; ++i: |
324 | | UDC_FIFO8 (ep) = data[i] |
325 | | //kdebug_num (data[i], 2) |
326 | | //kdebug (" ") |
327 | | |
328 | | void Udc::send_padded (char const *data, unsigned length, unsigned maxlength): |
329 | | UDC_INDEX = 2 |
330 | | unsigned len = length < maxlength ? length : maxlength |
331 | | residue = maxlength - len |
332 | | len = (len + 3) & ~3 |
333 | | send (2, data, len, maxlength) |
334 | | //Iris::debug ("sending %x, valid %x\n", maxlength, len) |
335 | | while len + 3 < maxlength: |
336 | | UDC_FIFO (2) = 0 |
337 | | len += 4 |
338 | | //kdebug_char ('-') |
339 | | while len < maxlength: |
340 | | UDC_FIFO8 (2) = 0 |
341 | | ++len |
342 | | //kdebug_char ('.') |
343 | | UDC_INCSR |= UDC_INCSR_INPKTRDY |
344 | | blocks = 0 |
345 | | state = TX |
346 | | |
347 | | unsigned Udc::get_descriptor (unsigned type, unsigned idx, unsigned len): |
348 | | switch type: |
349 | | case Configuration::Type: |
350 | | if idx != 0: |
351 | | return false |
352 | | //Iris::debug ("get config descriptor\n") |
353 | | send (0, reinterpret_cast <char const *> (&config_descriptor), sizeof (config_descriptor), len) |
354 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
355 | | case Device::Type: |
356 | | if idx != 0: |
357 | | return false |
358 | | //Iris::debug ("get device descriptor\n") |
359 | | send (0, reinterpret_cast <char const *> (&device_descriptor), sizeof (device_descriptor), len) |
360 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
361 | | case Device_Qualifier::Type: |
362 | | //if idx != 0: |
363 | | // return false |
364 | | //send (0, reinterpret_cast <char const *> (&device_qualifier_descriptor), sizeof (device_qualifier_descriptor), len) |
365 | | //return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
366 | | //break |
367 | | return ~0 |
368 | | // The 6 is an arbitrary number, except that String <6> is instantiated already. |
369 | | case String <6>::Type: |
370 | | switch idx: |
371 | | case 0: |
372 | | //Iris::debug ("get language descriptor\n") |
373 | | send (0, reinterpret_cast <char const *> (&s_langs), sizeof (s_langs), len) |
374 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
375 | | case 1: |
376 | | //Iris::debug ("get manufacturer descriptor\n") |
377 | | send (0, reinterpret_cast <char const *> (&s_manufacturer), sizeof (s_manufacturer), len) |
378 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
379 | | case 2: |
380 | | //Iris::debug ("get product descriptor\n") |
381 | | send (0, reinterpret_cast <char const *> (&s_product), sizeof (s_product), len) |
382 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
383 | | case 3: |
384 | | //Iris::debug ("get serial descriptor\n") |
385 | | send (0, reinterpret_cast <char const *> (&s_serial), sizeof (s_serial), len) |
386 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
387 | | default: |
388 | | return ~0 |
389 | | default: |
390 | | return ~0 |
391 | | |
392 | | unsigned Udc::handle_setup (Setup *s): |
393 | | switch s->request_type: |
394 | | case STANDARD_TO_DEVICE: |
395 | | UDC_INDEX = 0 |
396 | | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
397 | | switch s->request: |
398 | | case SET_ADDRESS: |
399 | | UDC_FADDR = s->value |
400 | | Iris::debug ("set address %x\n", s->value) |
401 | | return 0 |
402 | | case SET_CONFIGURATION: |
403 | | if s->value >= 2: |
404 | | return ~0 |
405 | | configuration = s->value |
406 | | Iris::debug ("set configuration %x\n", s->value) |
407 | | return 0 |
408 | | case SET_INTERFACE: |
409 | | if s->value != 0: |
410 | | return ~0 |
411 | | Iris::debug ("set interface %x\n", s->value) |
412 | | return 0 |
413 | | default: |
414 | | return ~0 |
415 | | case STANDARD_FROM_DEVICE: |
416 | | UDC_INDEX = 0 |
417 | | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
418 | | switch s->request: |
419 | | case GET_STATUS: |
420 | | Iris::debug ("get status\t") |
421 | | send (0, "\0\0", 2, s->length) |
422 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
423 | | case GET_DESCRIPTOR: |
424 | | return get_descriptor ((s->value >> 8) & 0xff, s->value & 0xff, s->length) |
425 | | case GET_CONFIGURATION: |
426 | | Iris::debug ("get configuration\t") |
427 | | send (0, &configuration, 1, s->length) |
428 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
429 | | case GET_INTERFACE: |
430 | | Iris::debug ("get interface\t") |
431 | | send (0, "\0", 1, s->length) |
432 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
433 | | default: |
434 | | return ~0 |
435 | | case STANDARD_TO_ENDPOINT: |
436 | | switch s->request: |
437 | | case CLEAR_FEATURE: |
438 | | switch s->value: |
439 | | case ENDPOINT_HALT: |
440 | | switch s->index: |
441 | | case 0x82: |
442 | | //Iris::debug ("in ep halt reset\n") |
443 | | UDC_INDEX = 2 |
444 | | UDC_INCSR = (UDC_INCSR & ~UDC_INCSR_SENDSTALL) | UDC_INCSR_CDT |
445 | | stalling = false |
446 | | send_csw () |
447 | | break |
448 | | case 1: |
449 | | //Iris::panic (0, "halt reset on out endpoint") |
450 | | UDC_INDEX = 1 |
451 | | UDC_OUTCSR |= UDC_OUTCSR_CDT |
452 | | break |
453 | | default: |
454 | | return ~0 |
455 | | return UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
456 | | default: |
457 | | return ~0 |
458 | | default: |
459 | | return ~0 |
460 | | case CLASS_FROM_INTERFACE: |
461 | | UDC_INDEX = 0 |
462 | | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
463 | | switch s->request: |
464 | | case GET_MAX_LUN: |
465 | | //Iris::debug ("get max lun\t") |
466 | | send (0, "\0", 1, s->length) |
467 | | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
468 | | default: |
469 | | return ~0 |
470 | | case CLASS_TO_INTERFACE: |
471 | | UDC_INDEX = 0 |
472 | | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
473 | | switch s->request: |
474 | | case BULK_ONLY_RESET: |
475 | | Iris::debug ("bulk reset\n") |
476 | | state = IDLE |
477 | | return 0 |
478 | | default: |
479 | | return ~0 |
480 | | default: |
481 | | Iris::debug ("request: %x %x %x %x %x\n", s->request_type, s->request, s->index, s->length, s->value) |
482 | | return ~0 |
483 | | |
484 | | void Udc::irq_in0 (): |
485 | | // Interrupt on endpoint 0. |
486 | | UDC_INDEX = 0 |
487 | | unsigned csr = UDC_CSR0 |
488 | | if csr & UDC_CSR0_SENTSTALL: |
489 | | UDC_CSR0 = 0 |
490 | | //Iris::debug ("stall 0 done\t") |
491 | | if csr & UDC_CSR0_SETUPEND: |
492 | | UDC_CSR0 = UDC_CSR0_SVDSETUPEND |
493 | | Iris::debug ("setup aborted\t") |
494 | | if !(csr & UDC_CSR0_OUTPKTRDY): |
495 | | //Iris::debug ("no packet 0: %x\n", csr) |
496 | | return |
497 | | UDC_INDEX = 0 |
498 | | union { unsigned d[2]; Setup s; } packet |
499 | | packet.d[0] = UDC_FIFO (0) |
500 | | packet.d[1] = UDC_FIFO (0) |
501 | | if !(packet.s.request_type & 0x80) && packet.s.length > 0: |
502 | | // More data will follow; unsupported. |
503 | | Iris::debug ("packet on ep0 too long\n") |
504 | | UDC_CSR0 = UDC_CSR0_SENDSTALL |
505 | | return |
506 | | unsigned ret = handle_setup (&packet.s) |
507 | | UDC_INDEX = 0 |
508 | | if ret == ~0: |
509 | | //Iris::debug ("failed setup: %x %x %x %x %x\n", packet.s.request_type, packet.s.request, packet.s.index, packet.s.length, packet.s.value) |
510 | | UDC_CSR0 = UDC_CSR0_SENDSTALL |
511 | | return |
512 | | if ret: |
513 | | UDC_CSR0 = ret |
514 | | //kdebug ("done in0\n") |
515 | | |
516 | | void Udc::send_csw (): |
517 | | UDC_INDEX = 2 |
518 | | UDC_FIFO (2) = 0x53425355 |
519 | | UDC_FIFO (2) = tag |
520 | | UDC_FIFO (2) = residue |
521 | | UDC_FIFO8 (2) = status |
522 | | UDC_INCSR |= UDC_INCSR_INPKTRDY |
523 | | state = SENT_CSW |
524 | | status = 0 |
525 | | residue = 0 |
526 | | //kdebug ("sent csw\n") |
527 | | |
528 | | void Udc::stall (unsigned error): |
529 | | if stalling: |
530 | | Iris::debug ("already stalling!\n") |
531 | | UDC_INCSR |= UDC_INCSR_SENDSTALL |
532 | | stalling = true |
533 | | state = STALL |
534 | | |
535 | | unsigned Udc::big_endian (unsigned src): |
536 | | return src >> 24 | src >> 8 & 0xff00 | src << 8 & 0xff0000 | src << 24 |
537 | | |
538 | | void Udc::handle_rx (): |
539 | | buffer_page.set_flags (Iris::Page::FRAME) |
540 | | UDC_INDEX = 1 |
541 | | if !(UDC_OUTCSR & UDC_OUTCSR_OUTPKTRDY): |
542 | | Iris::panic (0, "no packet ready after out interrupt during rx") |
543 | | if UDC_OUTCOUNT != max_packet_size_bulk: |
544 | | Iris::panic (UDC_OUTCOUNT, "invalid packet size during rx") |
545 | | for unsigned t = 0; t < max_packet_size_bulk; t += 4: |
546 | | ((unsigned *)buffer)[(t + data_done) >> 2] = UDC_FIFO (1) |
547 | | UDC_OUTCSR &= ~UDC_OUTCSR_OUTPKTRDY |
548 | | data_done += max_packet_size_bulk |
549 | | if data_done == 1 << block_bits: |
550 | | //Iris::debug ("writing block %x\n", lba) |
551 | | block.set_block (lba << block_bits, buffer_page, 1 << block_bits) |
552 | | data_done = 0 |
553 | | --blocks |
554 | | ++lba |
555 | | if blocks == 0: |
556 | | send_csw () |
557 | | return |
558 | | |
559 | | void Udc::handle_tx (): |
560 | | if blocks == 0: |
561 | | send_csw () |
562 | | return |
563 | | if data_done == 0: |
564 | | // read block lba. |
565 | | buffer_page.set_flags (Iris::Page::FRAME) |
566 | | block.get_block (lba << block_bits, 1 << block_bits, 0, buffer_page) |
567 | | UDC_INDEX = 2 |
568 | | for unsigned t = 0; t < max_packet_size_bulk; t += 4: |
569 | | UDC_FIFO (2) = ((unsigned *)buffer)[(data_done + t) >> 2] |
570 | | data_done += max_packet_size_bulk |
571 | | if data_done == 1 << block_bits: |
572 | | data_done = 0 |
573 | | ++lba |
574 | | --blocks |
575 | | UDC_INCSR |= UDC_INCSR_INPKTRDY |
576 | | |
577 | | void Udc::handle_cbw (): |
578 | | UDC_INDEX = 1 |
579 | | unsigned csr = UDC_OUTCSR |
580 | | unsigned size = UDC_OUTCOUNT |
581 | | if csr & UDC_OUTCSR_SENDSTALL: |
582 | | // When stalling, do nothing else. |
583 | | //kdebug ("not responding to out during stall\n") |
584 | | UDC_OUTCSR = csr & ~UDC_OUTCSR_SENTSTALL |
585 | | return |
586 | | if !(csr & UDC_OUTCSR_OUTPKTRDY): |
587 | | // No packet; this shouldn't happen. |
588 | | Iris::panic (0, "no packet") |
589 | | return |
590 | | // expect a new cbw. |
591 | | if size != 31: |
592 | | Iris::debug ("count %d != 31\n", size) |
593 | | stall (2) |
594 | | return |
595 | | union Cbw: |
596 | | unsigned u[8] |
597 | | char b[32] |
598 | | CBW cbw |
599 | | Cbw cbw |
600 | | for unsigned i = 0; i < 7; ++i: |
601 | | cbw.u[i] = UDC_FIFO (1) |
602 | | for unsigned i = 28; i < 31; ++i: |
603 | | cbw.b[i] = UDC_FIFO8 (1) |
604 | | UDC_OUTCSR = csr & ~UDC_OUTCSR_OUTPKTRDY |
605 | | tag = cbw.cbw.tag |
606 | | if cbw.cbw.sig != 0x43425355 || cbw.cbw.lun != 0 || cbw.cbw.size == 0 || cbw.cbw.size > 16: |
607 | | Iris::debug ("wrong cbw: sig %x lun %d size %d\n", cbw.cbw.sig, cbw.cbw.lun, cbw.cbw.size) |
608 | | stall (2) |
609 | | return |
610 | | //kdebug ("bulk cbw\t") |
611 | | #if 0 |
612 | | Iris::debug ("cbw:") |
613 | | for unsigned i = 0; i < cbw.cbw.size; ++i: |
614 | | kdebug_char (' ') |
615 | | kdebug_num (cbw.cbw.data[i], 2) |
616 | | Iris::debug ("\n") |
617 | | #endif |
618 | | UDC_INDEX = 2 |
619 | | bool to_host = cbw.cbw.flags & 0x80 |
620 | | switch cbw.cbw.data[0]: |
621 | | case CBW::TEST_UNIT_READY: |
622 | | if to_host || cbw.cbw.length != 0: |
623 | | stall (2) |
624 | | return |
625 | | //Iris::debug ("sending ready response\t") |
626 | | send_csw () |
627 | | break |
628 | | case CBW::REQUEST_SENSE: |
629 | | //Iris::debug ("sense requested\n") |
630 | | send_padded ("\xf0\x00\x05\x00\x00\x00\x00\x00", 8, cbw.cbw.length) |
631 | | break |
632 | | case CBW::FORMAT_UNIT: |
633 | | Iris::panic (0, "FORMAT_UNIT isn't implemented") |
634 | | case CBW::INQUIRY: |
635 | | if !to_host: |
636 | | stall (2) |
637 | | return |
638 | | //Iris::debug ("sending inquiry response\t") |
639 | | // TODO: find out why these bytes are messed up. |
640 | | send_padded ("\x00\x00\x04\x02\x1f\x00\x00\x00shevek iris usb stick \x00\x00\x04\x02", 36, cbw.cbw.length) |
641 | | break |
642 | | case CBW::RESERVE6: |
643 | | Iris::panic (0, "RESERVE6 isn't implemented") |
644 | | case CBW::RELEASE6: |
645 | | Iris::panic (0, "RELEASE6 isn't implemented") |
646 | | case CBW::SEND_DIAGNOSTIC: |
647 | | Iris::panic (0, "SEND_DIAGNOSTIC isn't implemented") |
648 | | case CBW::READ_CAPACITY: |
649 | | if !to_host: |
650 | | stall (2) |
651 | | return |
652 | | unsigned capacity[2] |
653 | | capacity[0] = big_endian ((block.get_size ().value () >> block_bits) - 1) |
654 | | capacity[1] = big_endian (1 << block_bits) |
655 | | //Iris::debug ("sending capacity: %x * %x\t", capacity[0], capacity[1]) |
656 | | send_padded ((char *)capacity, 8, cbw.cbw.length) |
657 | | break |
658 | | case CBW::READ10: |
659 | | if !to_host: |
660 | | stall (2) |
661 | | return |
662 | | lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5] |
663 | | blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8] |
664 | | data_done = 0 |
665 | | state = TX |
666 | | handle_tx () |
667 | | break |
668 | | case CBW::WRITE10: |
669 | | if to_host: |
670 | | stall (2) |
671 | | return |
672 | | lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5] |
673 | | blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8] |
674 | | if blocks == 0: |
675 | | send_csw () |
676 | | break |
677 | | state = RX |
678 | | data_done = 0 |
679 | | buffer_page.set_flags (Iris::Page::FRAME) |
680 | | break |
681 | | case CBW::RESERVE10: |
682 | | Iris::panic (0, "RESERVE10 isn't implemented") |
683 | | case CBW::RELEASE10: |
684 | | Iris::panic (0, "RELEASE10 isn't implemented") |
685 | | default: |
686 | | #if 0 |
687 | | Iris::debug ("unknown cbw:") |
688 | | for unsigned i = 0; i < cbw.cbw.size; ++i: |
689 | | kdebug_char (' ') |
690 | | kdebug_num (cbw.cbw.data[i], 2) |
691 | | Iris::debug ("\n") |
692 | | #endif |
693 | | residue = cbw.cbw.length |
694 | | stall (1) |
695 | | return |
696 | | |
697 | | void Udc::interrupt (): |
698 | | //Iris::debug ("interrupt, state = %d\n", state) |
699 | | while true: |
700 | | bool action = false |
701 | | unsigned usb = UDC_INTRUSB |
702 | | unsigned in = UDC_INTRIN |
703 | | unsigned out = UDC_INTROUT |
704 | | if usb & 4: |
705 | | //Iris::debug ("reset\n") |
706 | | reset () |
707 | | action = true |
708 | | if state == STALL && in & 4: |
709 | | // This must be handled here, because the state can be changed by the control request. |
710 | | //Iris::debug ("stalling\n") |
711 | | in &= ~4 |
712 | | if in & 1: |
713 | | //Iris::debug ("control request\n") |
714 | | irq_in0 () |
715 | | action = true |
716 | | if in & 4: |
717 | | //Iris::debug ("in request\n") |
718 | | // Notification of sent packet (or stall, but we don't do that on the in endpoint). |
719 | | switch state: |
720 | | case SENT_CSW: |
721 | | // csw received. |
722 | | state = IDLE |
723 | | break |
724 | | case TX: |
725 | | handle_tx () |
726 | | break |
727 | | default: |
728 | | Iris::panic (state, "invalid state for data send") |
729 | | stall (2) |
730 | | break |
731 | | action = true |
732 | | if out & 2: |
733 | | //Iris::debug ("out request\n") |
734 | | switch state: |
735 | | case IDLE: |
736 | | handle_cbw () |
737 | | break |
738 | | case RX: |
739 | | handle_rx () |
740 | | break |
741 | | default: |
742 | | stall (2) |
743 | | Iris::panic (0, "invalid state for data receive") |
744 | | break |
745 | | action = true |
746 | | if !action: |
747 | | // No more interrupts to handle; this is normal, because we're looping until this happens. |
748 | | //Iris::debug ("irq done\n") |
749 | | return |
750 | | |
751 | | Iris::Num start (): |
752 | | map_udc () |
753 | | map_gpio () |
754 | | map_cpm () |
755 | | Udc udc |
756 | | |
757 | | Iris::WBlock nand = Iris::my_parent.get_capability <Iris::WBlock> () |
758 | | udc.init (nand) |
759 | | while true: |
760 | | Iris::register_interrupt (IRQ_UDC) |
761 | | Iris::wait () |
762 | | udc.interrupt () |
source/usbmassstorage.ccp |
| 1 | #pypp 0 |
| 2 | // Iris: micro-kernel for a capability-based operating system. |
| 3 | // source/usb-mass-storage.ccp: USB mass storage device driver. |
| 4 | // Copyright 2009-2010 Bas Wijnen <wijnen@debian.org> |
| 5 | // |
| 6 | // This program is free software: you can redistribute it and/or modify |
| 7 | // it under the terms of the GNU General Public License as published by |
| 8 | // the Free Software Foundation, either version 3 of the License, or |
| 9 | // (at your option) any later version. |
| 10 | // |
| 11 | // This program is distributed in the hope that it will be useful, |
| 12 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | // GNU General Public License for more details. |
| 15 | // |
| 16 | // You should have received a copy of the GNU General Public License |
| 17 | // along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | |
| 19 | #include "iris.hh" |
| 20 | #include "devices.hh" |
| 21 | #define ARCH |
| 22 | #include "arch.hh" |
| 23 | |
| 24 | #if 0 |
| 25 | States and expected interrupts: |
| 26 | |
| 27 | IDLE: after reset or csw. |
| 28 | IN interrupt: csw received, do nothing. |
| 29 | OUT interrupt: cbw; handle |
| 30 | -> IDLE (no data; csw sent) |
| 31 | -> TX (send) |
| 32 | -> RX (receive packets) |
| 33 | TX: transmitting data. |
| 34 | IN interrupt: host received data; send more. |
| 35 | -> TX (more to send) |
| 36 | RX: receiving data. |
| 37 | OUT interrupt: host sent data; handle. |
| 38 | -> RX (more to receive) |
| 39 | -> IDLE (done receiving; send csw) |
| 40 | #endif |
| 41 | |
| 42 | extern "C": |
| 43 | void *memset (char *s, int c, unsigned long n): |
| 44 | Iris::debug ("memset called: %x %x->%x\n", s, n, c) |
| 45 | for unsigned i = 0; i < n; ++i: |
| 46 | s[i] = c |
| 47 | return s |
| 48 | |
| 49 | class Udc: |
| 50 | typedef unsigned char u8 |
| 51 | typedef unsigned short u16 |
| 52 | typedef unsigned int u32 |
| 53 | typedef u8 string |
| 54 | // The ugly stuff is because pypp doesn't support __attribute__. |
| 55 | /**/struct Setup { |
| 56 | u8 request_type; |
| 57 | u8 request; |
| 58 | u16 value; |
| 59 | u16 index; |
| 60 | u16 length; |
| 61 | } __attribute__ ((packed)) |
| 62 | /**/struct Device { |
| 63 | static u8 const Type = 1; |
| 64 | u8 length; |
| 65 | u8 type; |
| 66 | u16 usb_version; |
| 67 | u8 dev_class; |
| 68 | u8 subclass; |
| 69 | u8 protocol; |
| 70 | u8 max_packet_size0; |
| 71 | u16 vendor; |
| 72 | u16 product; |
| 73 | u16 dev_version; |
| 74 | string s_manufacturer; |
| 75 | string s_product; |
| 76 | string s_serial; |
| 77 | u8 num_configurations; |
| 78 | } __attribute__ ((packed)) |
| 79 | /**/struct Configuration { |
| 80 | static u8 const Type = 2; |
| 81 | u8 length; |
| 82 | u8 type; |
| 83 | u16 total_length; |
| 84 | u8 num_interfaces; |
| 85 | u8 configuration_value; |
| 86 | u8 configuration; |
| 87 | u8 attributes; |
| 88 | u8 max_power; |
| 89 | } __attribute__ ((packed)) |
| 90 | /**/struct Interface { |
| 91 | static u8 const Type = 4; |
| 92 | u8 length; |
| 93 | u8 type; |
| 94 | u8 interface; |
| 95 | u8 alternate; |
| 96 | u8 num_endpoints; |
| 97 | u8 iface_class; |
| 98 | u8 subclass; |
| 99 | u8 protocol; |
| 100 | string name; |
| 101 | } __attribute__ ((packed)) |
| 102 | /**/struct Endpoint { |
| 103 | static u8 const Type = 5; |
| 104 | u8 length; |
| 105 | u8 type; |
| 106 | u8 address; |
| 107 | u8 attributes; |
| 108 | u16 max_packet_size; |
| 109 | u8 interval; |
| 110 | } __attribute__ ((packed)) |
| 111 | /**/struct Device_Qualifier { |
| 112 | static u8 const Type = 6; |
| 113 | u8 length; |
| 114 | u8 type; |
| 115 | u16 version; |
| 116 | u8 dev_class; |
| 117 | u8 subclass; |
| 118 | u8 protocol; |
| 119 | u8 max_packet_size0; |
| 120 | u8 num_configurations; |
| 121 | u8 reserved; |
| 122 | } __attribute__ ((packed)) |
| 123 | /**/struct Langs { |
| 124 | static u8 const Type = 3; |
| 125 | u8 length; |
| 126 | u8 type; |
| 127 | u8 lang; |
| 128 | } __attribute__ ((packed)) |
| 129 | template <unsigned size> struct String { |
| 130 | static u8 const Type = 3; |
| 131 | u8 length; |
| 132 | u8 type; |
| 133 | u16 data[size]; |
| 134 | } __attribute__ ((packed)) |
| 135 | /**/struct CBW { |
| 136 | u32 sig; |
| 137 | u32 tag; |
| 138 | u32 length; |
| 139 | u8 flags; |
| 140 | u8 lun; |
| 141 | u8 size; |
| 142 | u8 data[16]; |
| 143 | enum Code { |
| 144 | TEST_UNIT_READY = 0x00, |
| 145 | REQUEST_SENSE = 0x03, |
| 146 | FORMAT_UNIT = 0x04, |
| 147 | INQUIRY = 0x12, |
| 148 | RESERVE6 = 0x16, |
| 149 | RELEASE6 = 0x17, |
| 150 | SEND_DIAGNOSTIC = 0x1d, |
| 151 | READ_CAPACITY = 0x25, |
| 152 | READ10 = 0x28, |
| 153 | WRITE10 = 0x2a, |
| 154 | RESERVE10 = 0x56, |
| 155 | RELEASE10 = 0x57 |
| 156 | }; |
| 157 | } __attribute__ ((packed)) |
| 158 | static unsigned const max_packet_size0 = 64 |
| 159 | static unsigned const max_packet_size_bulk = 64 |
| 160 | enum Requests: |
| 161 | GET_STATUS = 0 |
| 162 | CLEAR_FEATURE = 1 |
| 163 | SET_FEATURE = 3 |
| 164 | SET_ADDRESS = 5 |
| 165 | GET_DESCRIPTOR = 6 |
| 166 | SET_DESCRIPTOR = 7 |
| 167 | GET_CONFIGURATION = 8 |
| 168 | SET_CONFIGURATION = 9 |
| 169 | GET_INTERFACE = 10 |
| 170 | SET_INTERFACE = 11 |
| 171 | SYNCH_FRAME = 12 |
| 172 | enum Storage_requests: |
| 173 | BULK_ONLY_RESET = 0xff |
| 174 | GET_MAX_LUN = 0xfe |
| 175 | enum Request_types: |
| 176 | STANDARD_TO_DEVICE = 0 |
| 177 | CLASS_TO_DEVICE = 0x20 |
| 178 | VENDOR_TO_DEVICE = 0x40 |
| 179 | STANDARD_TO_INTERFACE = 1 |
| 180 | CLASS_TO_INTERFACE = 0x21 |
| 181 | VENDOR_TO_INTERFACE = 0x41 |
| 182 | STANDARD_TO_ENDPOINT = 2 |
| 183 | CLASS_TO_ENDPOINT = 0x22 |
| 184 | VENDOR_TO_ENDPOINT = 0x42 |
| 185 | STANDARD_FROM_DEVICE = 0x80 |
| 186 | CLASS_FROM_DEVICE = 0xa0 |
| 187 | VENDOR_FROM_DEVICE = 0xc0 |
| 188 | STANDARD_FROM_INTERFACE = 0x81 |
| 189 | CLASS_FROM_INTERFACE = 0xa1 |
| 190 | VENDOR_FROM_INTERFACE = 0xc1 |
| 191 | STANDARD_FROM_ENDPOINT = 0x82 |
| 192 | CLASS_FROM_ENDPOINT = 0xa2 |
| 193 | VENDOR_FROM_ENDPOINT = 0xc2 |
| 194 | enum Endpoint_types: |
| 195 | CONTROL = 0 |
| 196 | ISOCHRONOUS = 1 |
| 197 | BULK = 2 |
| 198 | INTERRUPT = 3 |
| 199 | enum Endpoint_features: |
| 200 | ENDPOINT_HALT = 0 |
| 201 | /**/struct my_config { |
| 202 | Configuration config; |
| 203 | Interface interface; |
| 204 | Endpoint endpoint[2]; |
| 205 | } __attribute__ ((packed)) |
| 206 | static Device device_descriptor |
| 207 | //static Device_Qualifier device_qualifier_descriptor |
| 208 | static my_config config_descriptor; //, other_config_descriptor |
| 209 | static String <1> s_langs |
| 210 | static String <6> s_manufacturer |
| 211 | static String <16> s_product |
| 212 | static String <12> s_serial |
| 213 | char configuration |
| 214 | unsigned get_descriptor (unsigned type, unsigned idx, unsigned len) |
| 215 | unsigned handle_setup (Setup *s) |
| 216 | void reset () |
| 217 | void irq_in0 () |
| 218 | void handle_rx () |
| 219 | void handle_tx () |
| 220 | void handle_cbw () |
| 221 | void send_csw () |
| 222 | unsigned big_endian (unsigned src) |
| 223 | bool handle_interrupt (bool usb, bool in) |
| 224 | void stall (unsigned error) |
| 225 | bool stalling |
| 226 | enum State: |
| 227 | IDLE |
| 228 | TX |
| 229 | RX |
| 230 | SENT_CSW |
| 231 | STALL |
| 232 | State state |
| 233 | unsigned residue |
| 234 | unsigned status |
| 235 | unsigned tag |
| 236 | unsigned data_done, lba, blocks |
| 237 | unsigned block_bits |
| 238 | Iris::WBlock block |
| 239 | Iris::Page buffer_page |
| 240 | // A random address to map the buffer. |
| 241 | static unsigned const buffer = 0x15000 |
| 242 | public: |
| 243 | void init (Iris::WBlock b) |
| 244 | void log (unsigned c) |
| 245 | void interrupt () |
| 246 | void send (unsigned ep, char const *data, unsigned length, unsigned maxlength) |
| 247 | void send_padded (char const *data, unsigned length, unsigned maxlength) |
| 248 | |
| 249 | Udc::Device Udc::device_descriptor |
| 250 | Udc::my_config Udc::config_descriptor |
| 251 | Udc::String <1> Udc::s_langs |
| 252 | Udc::String <6> Udc::s_manufacturer |
| 253 | Udc::String <16> Udc::s_product |
| 254 | Udc::String <12> Udc::s_serial |
| 255 | |
| 256 | void Udc::reset (): |
| 257 | // Reset. |
| 258 | UDC_TESTMODE = 0 |
| 259 | configuration = 0 |
| 260 | state = IDLE |
| 261 | status = 0 |
| 262 | residue = 0 |
| 263 | // enable interrupt on bus reset. |
| 264 | UDC_INTRUSBE = UDC_INTR_RESET |
| 265 | // enable interrupts on endpoint 0 and in endpoint 2 |
| 266 | UDC_INTRINE = 1 << 0 | 1 << 2 |
| 267 | // and on out endpoint 1. |
| 268 | UDC_INTROUTE = 1 << 1 |
| 269 | // exit suspend mode by reading the interrupt register. |
| 270 | unsigned i = UDC_INTRUSB |
| 271 | // reset all pending endpoint interrupts. |
| 272 | i = UDC_INTRIN |
| 273 | i = UDC_INTROUT |
| 274 | UDC_INDEX = 1 |
| 275 | UDC_OUTMAXP = max_packet_size_bulk |
| 276 | // Do this twice to flush a double-buffered fifo completely. |
| 277 | UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
| 278 | UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF |
| 279 | UDC_INDEX = 2 |
| 280 | UDC_INMAXP = max_packet_size_bulk |
| 281 | UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF |
| 282 | UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF |
| 283 | //Iris::debug ("usb reset\n") |
| 284 | |
| 285 | void Udc::init (Iris::WBlock b): |
| 286 | block = b |
| 287 | block_bits = block.get_align_bits () |
| 288 | // Set up the buffer page. |
| 289 | buffer_page = Iris::my_memory.create_page () |
| 290 | buffer_page.set_flags (Iris::Page::PAYING) |
| 291 | Iris::my_memory.map (buffer_page, buffer) |
| 292 | // Initialize the globals. My method of compiling doesn't handle global constructors. |
| 293 | device_descriptor = (Device){ sizeof (Device), Device::Type, 0x200, 0, 0, 0, max_packet_size0, 0xfffe, 0x0002, 0x100, 1, 2, 3, 1 } |
| 294 | config_descriptor = (my_config){ |
| 295 | (Configuration){ sizeof (Configuration), Configuration::Type, sizeof (my_config), 1, 1, 0, 0xc0, 30 }, |
| 296 | (Interface){ sizeof (Interface), Interface::Type, 0, 0, 2, 0x8, 0x6, 0x50, 0 }, { |
| 297 | (Endpoint){ sizeof (Endpoint), Endpoint::Type, 1, BULK, max_packet_size_bulk, 0 }, |
| 298 | (Endpoint){ sizeof (Endpoint), Endpoint::Type, 0x82, BULK, max_packet_size_bulk, 0 } |
| 299 | } |
| 300 | } |
| 301 | s_langs = (String <1>){ sizeof (String <1>), String <1>::Type, { 0x0409 } } |
| 302 | s_manufacturer = (String <6>){ sizeof (String <6>), String <6>::Type, { 's', 'h', 'e', 'v', 'e', 'k' } } |
| 303 | s_product = (String <16>){ sizeof (String <16>), String <16>::Type, { 'I', 'r', 'i', 's', ' ', 'o', 'n', ' ', 'N', 'a', 'n', 'o', 'N', 'o', 't', 'e' } } |
| 304 | s_serial = (String <12>){ sizeof (String <12>), String <12>::Type, { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B' } } |
| 305 | |
| 306 | cpm_start_udc () |
| 307 | // Disconnect from the bus and don't try to get high-speed. |
| 308 | UDC_POWER = 0 |
| 309 | reset () |
| 310 | // Wait a while. |
| 311 | Iris::sleep (HZ / 10) |
| 312 | // Connect to the host. |
| 313 | UDC_POWER = UDC_POWER_SOFTCONN |
| 314 | |
| 315 | void Udc::send (unsigned ep, char const *data, unsigned length, unsigned maxlength): |
| 316 | if maxlength < length: |
| 317 | length = maxlength |
| 318 | unsigned i |
| 319 | for i = 0; (length - i & ~3) > 0 && i < length; i += 4: |
| 320 | UDC_FIFO (ep) = ((unsigned *)data)[i / 4] |
| 321 | //kdebug_num (((unsigned *)data)[i / 4], 8) |
| 322 | //kdebug (" ") |
| 323 | for ; i < length; ++i: |
| 324 | UDC_FIFO8 (ep) = data[i] |
| 325 | //kdebug_num (data[i], 2) |
| 326 | //kdebug (" ") |
| 327 | |
| 328 | void Udc::send_padded (char const *data, unsigned length, unsigned maxlength): |
| 329 | UDC_INDEX = 2 |
| 330 | unsigned len = length < maxlength ? length : maxlength |
| 331 | residue = maxlength - len |
| 332 | len = (len + 3) & ~3 |
| 333 | send (2, data, len, maxlength) |
| 334 | //Iris::debug ("sending %x, valid %x\n", maxlength, len) |
| 335 | while len + 3 < maxlength: |
| 336 | UDC_FIFO (2) = 0 |
| 337 | len += 4 |
| 338 | //kdebug_char ('-') |
| 339 | while len < maxlength: |
| 340 | UDC_FIFO8 (2) = 0 |
| 341 | ++len |
| 342 | //kdebug_char ('.') |
| 343 | UDC_INCSR |= UDC_INCSR_INPKTRDY |
| 344 | blocks = 0 |
| 345 | state = TX |
| 346 | |
| 347 | unsigned Udc::get_descriptor (unsigned type, unsigned idx, unsigned len): |
| 348 | switch type: |
| 349 | case Configuration::Type: |
| 350 | if idx != 0: |
| 351 | return false |
| 352 | //Iris::debug ("get config descriptor\n") |
| 353 | send (0, reinterpret_cast <char const *> (&config_descriptor), sizeof (config_descriptor), len) |
| 354 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 355 | case Device::Type: |
| 356 | if idx != 0: |
| 357 | return false |
| 358 | //Iris::debug ("get device descriptor\n") |
| 359 | send (0, reinterpret_cast <char const *> (&device_descriptor), sizeof (device_descriptor), len) |
| 360 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 361 | case Device_Qualifier::Type: |
| 362 | //if idx != 0: |
| 363 | // return false |
| 364 | //send (0, reinterpret_cast <char const *> (&device_qualifier_descriptor), sizeof (device_qualifier_descriptor), len) |
| 365 | //return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 366 | //break |
| 367 | return ~0 |
| 368 | // The 6 is an arbitrary number, except that String <6> is instantiated already. |
| 369 | case String <6>::Type: |
| 370 | switch idx: |
| 371 | case 0: |
| 372 | //Iris::debug ("get language descriptor\n") |
| 373 | send (0, reinterpret_cast <char const *> (&s_langs), sizeof (s_langs), len) |
| 374 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 375 | case 1: |
| 376 | //Iris::debug ("get manufacturer descriptor\n") |
| 377 | send (0, reinterpret_cast <char const *> (&s_manufacturer), sizeof (s_manufacturer), len) |
| 378 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 379 | case 2: |
| 380 | //Iris::debug ("get product descriptor\n") |
| 381 | send (0, reinterpret_cast <char const *> (&s_product), sizeof (s_product), len) |
| 382 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 383 | case 3: |
| 384 | //Iris::debug ("get serial descriptor\n") |
| 385 | send (0, reinterpret_cast <char const *> (&s_serial), sizeof (s_serial), len) |
| 386 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 387 | default: |
| 388 | return ~0 |
| 389 | default: |
| 390 | return ~0 |
| 391 | |
| 392 | unsigned Udc::handle_setup (Setup *s): |
| 393 | switch s->request_type: |
| 394 | case STANDARD_TO_DEVICE: |
| 395 | UDC_INDEX = 0 |
| 396 | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
| 397 | switch s->request: |
| 398 | case SET_ADDRESS: |
| 399 | UDC_FADDR = s->value |
| 400 | Iris::debug ("set address %x\n", s->value) |
| 401 | return 0 |
| 402 | case SET_CONFIGURATION: |
| 403 | if s->value >= 2: |
| 404 | return ~0 |
| 405 | configuration = s->value |
| 406 | Iris::debug ("set configuration %x\n", s->value) |
| 407 | return 0 |
| 408 | case SET_INTERFACE: |
| 409 | if s->value != 0: |
| 410 | return ~0 |
| 411 | Iris::debug ("set interface %x\n", s->value) |
| 412 | return 0 |
| 413 | default: |
| 414 | return ~0 |
| 415 | case STANDARD_FROM_DEVICE: |
| 416 | UDC_INDEX = 0 |
| 417 | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
| 418 | switch s->request: |
| 419 | case GET_STATUS: |
| 420 | Iris::debug ("get status\t") |
| 421 | send (0, "\0\0", 2, s->length) |
| 422 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 423 | case GET_DESCRIPTOR: |
| 424 | return get_descriptor ((s->value >> 8) & 0xff, s->value & 0xff, s->length) |
| 425 | case GET_CONFIGURATION: |
| 426 | Iris::debug ("get configuration\t") |
| 427 | send (0, &configuration, 1, s->length) |
| 428 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 429 | case GET_INTERFACE: |
| 430 | Iris::debug ("get interface\t") |
| 431 | send (0, "\0", 1, s->length) |
| 432 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 433 | default: |
| 434 | return ~0 |
| 435 | case STANDARD_TO_ENDPOINT: |
| 436 | switch s->request: |
| 437 | case CLEAR_FEATURE: |
| 438 | switch s->value: |
| 439 | case ENDPOINT_HALT: |
| 440 | switch s->index: |
| 441 | case 0x82: |
| 442 | //Iris::debug ("in ep halt reset\n") |
| 443 | UDC_INDEX = 2 |
| 444 | UDC_INCSR = (UDC_INCSR & ~UDC_INCSR_SENDSTALL) | UDC_INCSR_CDT |
| 445 | stalling = false |
| 446 | send_csw () |
| 447 | break |
| 448 | case 1: |
| 449 | //Iris::panic (0, "halt reset on out endpoint") |
| 450 | UDC_INDEX = 1 |
| 451 | UDC_OUTCSR |= UDC_OUTCSR_CDT |
| 452 | break |
| 453 | default: |
| 454 | return ~0 |
| 455 | return UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
| 456 | default: |
| 457 | return ~0 |
| 458 | default: |
| 459 | return ~0 |
| 460 | case CLASS_FROM_INTERFACE: |
| 461 | UDC_INDEX = 0 |
| 462 | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
| 463 | switch s->request: |
| 464 | case GET_MAX_LUN: |
| 465 | //Iris::debug ("get max lun\t") |
| 466 | send (0, "\0", 1, s->length) |
| 467 | return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND |
| 468 | default: |
| 469 | return ~0 |
| 470 | case CLASS_TO_INTERFACE: |
| 471 | UDC_INDEX = 0 |
| 472 | UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY |
| 473 | switch s->request: |
| 474 | case BULK_ONLY_RESET: |
| 475 | Iris::debug ("bulk reset\n") |
| 476 | state = IDLE |
| 477 | return 0 |
| 478 | default: |
| 479 | return ~0 |
| 480 | default: |
| 481 | Iris::debug ("request: %x %x %x %x %x\n", s->request_type, s->request, s->index, s->length, s->value) |
| 482 | return ~0 |
| 483 | |
| 484 | void Udc::irq_in0 (): |
| 485 | // Interrupt on endpoint 0. |
| 486 | UDC_INDEX = 0 |
| 487 | unsigned csr = UDC_CSR0 |
| 488 | if csr & UDC_CSR0_SENTSTALL: |
| 489 | UDC_CSR0 = 0 |
| 490 | //Iris::debug ("stall 0 done\t") |
| 491 | if csr & UDC_CSR0_SETUPEND: |
| 492 | UDC_CSR0 = UDC_CSR0_SVDSETUPEND |
| 493 | Iris::debug ("setup aborted\t") |
| 494 | if !(csr & UDC_CSR0_OUTPKTRDY): |
| 495 | //Iris::debug ("no packet 0: %x\n", csr) |
| 496 | return |
| 497 | UDC_INDEX = 0 |
| 498 | union { unsigned d[2]; Setup s; } packet |
| 499 | packet.d[0] = UDC_FIFO (0) |
| 500 | packet.d[1] = UDC_FIFO (0) |
| 501 | if !(packet.s.request_type & 0x80) && packet.s.length > 0: |
| 502 | // More data will follow; unsupported. |
| 503 | Iris::debug ("packet on ep0 too long\n") |
| 504 | UDC_CSR0 = UDC_CSR0_SENDSTALL |
| 505 | return |
| 506 | unsigned ret = handle_setup (&packet.s) |
| 507 | UDC_INDEX = 0 |
| 508 | if ret == ~0: |
| 509 | //Iris::debug ("failed setup: %x %x %x %x %x\n", packet.s.request_type, packet.s.request, packet.s.index, packet.s.length, packet.s.value) |
| 510 | UDC_CSR0 = UDC_CSR0_SENDSTALL |
| 511 | return |
| 512 | if ret: |
| 513 | UDC_CSR0 = ret |
| 514 | //kdebug ("done in0\n") |
| 515 | |
| 516 | void Udc::send_csw (): |
| 517 | UDC_INDEX = 2 |
| 518 | UDC_FIFO (2) = 0x53425355 |
| 519 | UDC_FIFO (2) = tag |
| 520 | UDC_FIFO (2) = residue |
| 521 | UDC_FIFO8 (2) = status |
| 522 | UDC_INCSR |= UDC_INCSR_INPKTRDY |
| 523 | state = SENT_CSW |
| 524 | status = 0 |
| 525 | residue = 0 |
| 526 | //kdebug ("sent csw\n") |
| 527 | |
| 528 | void Udc::stall (unsigned error): |
| 529 | if stalling: |
| 530 | Iris::debug ("already stalling!\n") |
| 531 | UDC_INCSR |= UDC_INCSR_SENDSTALL |
| 532 | stalling = true |
| 533 | state = STALL |
| 534 | |
| 535 | unsigned Udc::big_endian (unsigned src): |
| 536 | return src >> 24 | src >> 8 & 0xff00 | src << 8 & 0xff0000 | src << 24 |
| 537 | |
| 538 | void Udc::handle_rx (): |
| 539 | buffer_page.set_flags (Iris::Page::FRAME) |
| 540 | UDC_INDEX = 1 |
| 541 | if !(UDC_OUTCSR & UDC_OUTCSR_OUTPKTRDY): |
| 542 | Iris::panic (0, "no packet ready after out interrupt during rx") |
| 543 | if UDC_OUTCOUNT != max_packet_size_bulk: |
| 544 | Iris::panic (UDC_OUTCOUNT, "invalid packet size during rx") |
| 545 | for unsigned t = 0; t < max_packet_size_bulk; t += 4: |
| 546 | ((unsigned *)buffer)[(t + data_done) >> 2] = UDC_FIFO (1) |
| 547 | UDC_OUTCSR &= ~UDC_OUTCSR_OUTPKTRDY |
| 548 | data_done += max_packet_size_bulk |
| 549 | if data_done == 1 << block_bits: |
| 550 | //Iris::debug ("writing block %x\n", lba) |
| 551 | block.set_block (lba << block_bits, buffer_page, 1 << block_bits) |
| 552 | data_done = 0 |
| 553 | --blocks |
| 554 | ++lba |
| 555 | if blocks == 0: |
| 556 | send_csw () |
| 557 | return |
| 558 | |
| 559 | void Udc::handle_tx (): |
| 560 | if blocks == 0: |
| 561 | send_csw () |
| 562 | return |
| 563 | if data_done == 0: |
| 564 | // read block lba. |
| 565 | buffer_page.set_flags (Iris::Page::FRAME) |
| 566 | block.get_block (lba << block_bits, 1 << block_bits, 0, buffer_page) |
| 567 | UDC_INDEX = 2 |
| 568 | for unsigned t = 0; t < max_packet_size_bulk; t += 4: |
| 569 | UDC_FIFO (2) = ((unsigned *)buffer)[(data_done + t) >> 2] |
| 570 | data_done += max_packet_size_bulk |
| 571 | if data_done == 1 << block_bits: |
| 572 | data_done = 0 |
| 573 | ++lba |
| 574 | --blocks |
| 575 | UDC_INCSR |= UDC_INCSR_INPKTRDY |
| 576 | |
| 577 | void Udc::handle_cbw (): |
| 578 | UDC_INDEX = 1 |
| 579 | unsigned csr = UDC_OUTCSR |
| 580 | unsigned size = UDC_OUTCOUNT |
| 581 | if csr & UDC_OUTCSR_SENDSTALL: |
| 582 | // When stalling, do nothing else. |
| 583 | //kdebug ("not responding to out during stall\n") |
| 584 | UDC_OUTCSR = csr & ~UDC_OUTCSR_SENTSTALL |
| 585 | return |
| 586 | if !(csr & UDC_OUTCSR_OUTPKTRDY): |
| 587 | // No packet; this shouldn't happen. |
| 588 | Iris::panic (0, "no packet") |
| 589 | return |
| 590 | // expect a new cbw. |
| 591 | if size != 31: |
| 592 | Iris::debug ("count %d != 31\n", size) |
| 593 | stall (2) |
| 594 | return |
| 595 | union Cbw: |
| 596 | unsigned u[8] |
| 597 | char b[32] |
| 598 | CBW cbw |
| 599 | Cbw cbw |
| 600 | for unsigned i = 0; i < 7; ++i: |
| 601 | cbw.u[i] = UDC_FIFO (1) |
| 602 | for unsigned i = 28; i < 31; ++i: |
| 603 | cbw.b[i] = UDC_FIFO8 (1) |
| 604 | UDC_OUTCSR = csr & ~UDC_OUTCSR_OUTPKTRDY |
| 605 | tag = cbw.cbw.tag |
| 606 | if cbw.cbw.sig != 0x43425355 || cbw.cbw.lun != 0 || cbw.cbw.size == 0 || cbw.cbw.size > 16: |
| 607 | Iris::debug ("wrong cbw: sig %x lun %d size %d\n", cbw.cbw.sig, cbw.cbw.lun, cbw.cbw.size) |
| 608 | stall (2) |
| 609 | return |
| 610 | //kdebug ("bulk cbw\t") |
| 611 | #if 0 |
| 612 | Iris::debug ("cbw:") |
| 613 | for unsigned i = 0; i < cbw.cbw.size; ++i: |
| 614 | kdebug_char (' ') |
| 615 | kdebug_num (cbw.cbw.data[i], 2) |
| 616 | Iris::debug ("\n") |
| 617 | #endif |
| 618 | UDC_INDEX = 2 |
| 619 | bool to_host = cbw.cbw.flags & 0x80 |
| 620 | switch cbw.cbw.data[0]: |
| 621 | case CBW::TEST_UNIT_READY: |
| 622 | if to_host || cbw.cbw.length != 0: |
| 623 | stall (2) |
| 624 | return |
| 625 | //Iris::debug ("sending ready response\t") |
| 626 | send_csw () |
| 627 | break |
| 628 | case CBW::REQUEST_SENSE: |
| 629 | //Iris::debug ("sense requested\n") |
| 630 | send_padded ("\xf0\x00\x05\x00\x00\x00\x00\x00", 8, cbw.cbw.length) |
| 631 | break |
| 632 | case CBW::FORMAT_UNIT: |
| 633 | Iris::panic (0, "FORMAT_UNIT isn't implemented") |
| 634 | case CBW::INQUIRY: |
| 635 | if !to_host: |
| 636 | stall (2) |
| 637 | return |
| 638 | //Iris::debug ("sending inquiry response\t") |
| 639 | // TODO: find out why these bytes are messed up. |
| 640 | send_padded ("\x00\x00\x04\x02\x1f\x00\x00\x00shevek iris usb stick \x00\x00\x04\x02", 36, cbw.cbw.length) |
| 641 | break |
| 642 | case CBW::RESERVE6: |
| 643 | Iris::panic (0, "RESERVE6 isn't implemented") |
| 644 | case CBW::RELEASE6: |
| 645 | Iris::panic (0, "RELEASE6 isn't implemented") |
| 646 | case CBW::SEND_DIAGNOSTIC: |
| 647 | Iris::panic (0, "SEND_DIAGNOSTIC isn't implemented") |
| 648 | case CBW::READ_CAPACITY: |
| 649 | if !to_host: |
| 650 | stall (2) |
| 651 | return |
| 652 | unsigned capacity[2] |
| 653 | capacity[0] = big_endian ((block.get_size ().value () >> block_bits) - 1) |
| 654 | capacity[1] = big_endian (1 << block_bits) |
| 655 | //Iris::debug ("sending capacity: %x * %x\t", capacity[0], capacity[1]) |
| 656 | send_padded ((char *)capacity, 8, cbw.cbw.length) |
| 657 | break |
| 658 | case CBW::READ10: |
| 659 | if !to_host: |
| 660 | stall (2) |
| 661 | return |
| 662 | lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5] |
| 663 | blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8] |
| 664 | data_done = 0 |
| 665 | state = TX |
| 666 | handle_tx () |
| 667 | break |
| 668 | case CBW::WRITE10: |
| 669 | if to_host: |
| 670 | stall (2) |
| 671 | return |
| 672 | lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5] |
| 673 | blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8] |
| 674 | if blocks == 0: |
| 675 | send_csw () |
| 676 | break |
| 677 | state = RX |
| 678 | data_done = 0 |
| 679 | buffer_page.set_flags (Iris::Page::FRAME) |
| 680 | break |
| 681 | case CBW::RESERVE10: |
| 682 | Iris::panic (0, "RESERVE10 isn't implemented") |
| 683 | case CBW::RELEASE10: |
| 684 | Iris::panic (0, "RELEASE10 isn't implemented") |
| 685 | default: |
| 686 | #if 0 |
| 687 | Iris::debug ("unknown cbw:") |
| 688 | for unsigned i = 0; i < cbw.cbw.size; ++i: |
| 689 | kdebug_char (' ') |
| 690 | kdebug_num (cbw.cbw.data[i], 2) |
| 691 | Iris::debug ("\n") |
| 692 | #endif |
| 693 | residue = cbw.cbw.length |
| 694 | stall (1) |
| 695 | return |
| 696 | |
| 697 | void Udc::interrupt (): |
| 698 | //Iris::debug ("interrupt, state = %d\n", state) |
| 699 | while true: |
| 700 | bool action = false |
| 701 | unsigned usb = UDC_INTRUSB |
| 702 | unsigned in = UDC_INTRIN |
| 703 | unsigned out = UDC_INTROUT |
| 704 | if usb & 4: |
| 705 | //Iris::debug ("reset\n") |
| 706 | reset () |
| 707 | action = true |
| 708 | if state == STALL && in & 4: |
| 709 | // This must be handled here, because the state can be changed by the control request. |
| 710 | //Iris::debug ("stalling\n") |
| 711 | in &= ~4 |
| 712 | if in & 1: |
| 713 | //Iris::debug ("control request\n") |
| 714 | irq_in0 () |
| 715 | action = true |
| 716 | if in & 4: |
| 717 | //Iris::debug ("in request\n") |
| 718 | // Notification of sent packet (or stall, but we don't do that on the in endpoint). |
| 719 | switch state: |
| 720 | case SENT_CSW: |
| 721 | // csw received. |
| 722 | state = IDLE |
| 723 | break |
| 724 | case TX: |
| 725 | handle_tx () |
| 726 | break |
| 727 | default: |
| 728 | Iris::panic (state, "invalid state for data send") |
| 729 | stall (2) |
| 730 | break |
| 731 | action = true |
| 732 | if out & 2: |
| 733 | //Iris::debug ("out request\n") |
| 734 | switch state: |
| 735 | case IDLE: |
| 736 | handle_cbw () |
| 737 | break |
| 738 | case RX: |
| 739 | handle_rx () |
| 740 | break |
| 741 | default: |
| 742 | stall (2) |
| 743 | Iris::panic (0, "invalid state for data receive") |
| 744 | break |
| 745 | action = true |
| 746 | if !action: |
| 747 | // No more interrupts to handle; this is normal, because we're looping until this happens. |
| 748 | //Iris::debug ("irq done\n") |
| 749 | return |
| 750 | |
| 751 | Iris::Num start (): |
| 752 | map_udc () |
| 753 | map_gpio () |
| 754 | map_cpm () |
| 755 | Udc udc |
| 756 | |
| 757 | Iris::WBlock nand = Iris::my_parent.get_capability <Iris::WBlock> () |
| 758 | udc.init (nand) |
| 759 | while true: |
| 760 | Iris::register_interrupt (IRQ_UDC) |
| 761 | Iris::wait () |
| 762 | udc.interrupt () |