Root/
| 1 | cclk: cpu clock. Fastest clock in the system. |
| 2 | hclk: high-speed peripheral bus clock. |
| 3 | pclk: peripheral bus clock. |
| 4 | mclk: memory clock, for emc. |
| 5 | ldclk: lcd device clock. |
| 6 | lpclk: lcd pixel clock. |
| 7 | cim_mclk: clock output for cim. |
| 8 | cim_pclk: clock input for cim. |
| 9 | i2sclk: codec clock. |
| 10 | mscclk: msc clock. |
| 11 | ssiclk: ssi clock. |
| 12 | exclk: 12MHz clock output, used by uart, i2c, ssi, tcu, usb2.0-phy. |
| 13 | rtclk: 32768Hz clock input for rtc. |
| 14 | |
| 15 | cclk: 252M |
| 16 | hclk: 84M |
| 17 | pclk: 84M |
| 18 | mclk: 84M |
| 19 | ldclk: 84M; must not be larger than 150M |
| 20 | lpclk: 25295340 (70Hz screen refresh) |
| 21 | cim_mclk: not used. |
| 22 | cim_pclk: not used. |
| 23 | i2sclk: must be 12M |
| 24 | mscclk: must not be larger than 400k during init; not larger than 25M later. |
| 25 | ssiclk: not used. |
| 26 | exclk: 12M, not adjustable. |
| 27 | rtclk: 32768, not adjustable. |
| 28 | |
| 29 | usb clock, for host and device, must be 48M. |
| 30 | |
| 31 | restrictions: |
| 32 | - cclk must be i*hclk |
| 33 | - i must not be 24 or 32 |
| 34 | - hclk = mclk or hclk = 2*mclk |
| 35 | - mclk = k*pclk |
| 36 | |
| 37 | so: |
| 38 | - pclk is set |
| 39 | - mclk = k*pclk |
| 40 | - hclk = l*mclk = l*k*pclk; l = 1 or 2 |
| 41 | - cclk = i*hclk = i*l*k*pclk; i != 24 or 32 |
| 42 | |
| 43 | In the code: |
| 44 | m = 42 |
| 45 | n = 2 |
| 46 | no = 1 |
| 47 | So clkout = 12M * 21 = 252M; this is the pll clock frequency. |
| 48 |
Branches:
master
