Root/
| 1 | #pypp 0 |
| 2 | // Iris: micro-kernel for a capability-based operating system. |
| 3 | // nanonote/jz4740.ccp: Chip features. Most of this file is |
| 4 | // copied from the Linux source files include/asm-mips/jz4740/{ops,regs}.h, |
| 5 | // which don't have a copyright statement or license in the header. |
| 6 | // Copyright 2009 Bas Wijnen <wijnen@debian.org> |
| 7 | // |
| 8 | // This program is free software: you can redistribute it and/or modify |
| 9 | // it under the terms of the GNU General Public License as published by |
| 10 | // the Free Software Foundation, either version 3 of the License, or |
| 11 | // (at your option) any later version. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 20 | |
| 21 | #ifndef __JZ4740_HH__ |
| 22 | #define __JZ4740_HH__ |
| 23 | |
| 24 | // Main clock, for cpu, serial port, and with divisors for most other hardware |
| 25 | #define JZ_EXTAL 12000000 /* 12 MHz */ |
| 26 | // RTC clock |
| 27 | #define RTC_CLOCK 32768 /* 32.768 KHz */ |
| 28 | // Interrupt source used for system timer |
| 29 | #define TIMER_INTERRUPT IRQ_TCU0 |
| 30 | |
| 31 | // Physical addresses are where they really are. |
| 32 | #define CPM_PHYSICAL 0x10000000 |
| 33 | #define INTC_PHYSICAL 0x10001000 |
| 34 | #define TCU_PHYSICAL 0x10002000 |
| 35 | #define WDT_PHYSICAL 0x10002000 |
| 36 | #define RTC_PHYSICAL 0x10003000 |
| 37 | #define GPIO_PHYSICAL 0x10010000 |
| 38 | #define AIC_PHYSICAL 0x10020000 |
| 39 | #define MSC_PHYSICAL 0x10021000 |
| 40 | #define UART0_PHYSICAL 0x10030000 |
| 41 | #define I2C_PHYSICAL 0x10042000 |
| 42 | #define SSI_PHYSICAL 0x10043000 |
| 43 | #define SADC_PHYSICAL 0x10070000 |
| 44 | #define EMC_PHYSICAL 0x13010000 |
| 45 | #define DMAC_PHYSICAL 0x13020000 |
| 46 | #define UHC_PHYSICAL 0x13030000 |
| 47 | #define UDC_PHYSICAL 0x13040000 |
| 48 | #define LCD_PHYSICAL 0x13050000 |
| 49 | #define SLCD_PHYSICAL 0x13050000 |
| 50 | #define CIM_PHYSICAL 0x13060000 |
| 51 | #define ETH_PHYSICAL 0x13100000 |
| 52 | |
| 53 | #ifdef __KERNEL__ |
| 54 | // In kernel space you need to add 0xa0000000 to see them unmapped uncached in kseg2. |
| 55 | #define CPM_BASE (0xa0000000 + CPM_PHYSICAL) |
| 56 | #define INTC_BASE (0xa0000000 + INTC_PHYSICAL) |
| 57 | #define TCU_BASE (0xa0000000 + TCU_PHYSICAL) |
| 58 | #define WDT_BASE (0xa0000000 + WDT_PHYSICAL) |
| 59 | #define RTC_BASE (0xa0000000 + RTC_PHYSICAL) |
| 60 | #define GPIO_BASE (0xa0000000 + GPIO_PHYSICAL) |
| 61 | #define AIC_BASE (0xa0000000 + AIC_PHYSICAL) |
| 62 | #define MSC_BASE (0xa0000000 + MSC_PHYSICAL) |
| 63 | #define UART0_BASE (0xa0000000 + UART0_PHYSICAL) |
| 64 | #define I2C_BASE (0xa0000000 + I2C_PHYSICAL) |
| 65 | #define SSI_BASE (0xa0000000 + SSI_PHYSICAL) |
| 66 | #define SADC_BASE (0xa0000000 + SADC_PHYSICAL) |
| 67 | #define EMC_BASE (0xa0000000 + EMC_PHYSICAL) |
| 68 | #define DMAC_BASE (0xa0000000 + DMAC_PHYSICAL) |
| 69 | #define UHC_BASE (0xa0000000 + UHC_PHYSICAL) |
| 70 | #define UDC_BASE (0xa0000000 + UDC_PHYSICAL) |
| 71 | #define LCD_BASE (0xa0000000 + LCD_PHYSICAL) |
| 72 | #define SLCD_BASE (0xa0000000 + SLCD_PHYSICAL) |
| 73 | #define CIM_BASE (0xa0000000 + CIM_PHYSICAL) |
| 74 | #define ETH_BASE (0xa0000000 + ETH_PHYSICAL) |
| 75 | |
| 76 | // udelay should not be called from the kernel. |
| 77 | #define udelay(x) dpanic (x, "udelay called") |
| 78 | |
| 79 | #else |
| 80 | // In user space, they just need a mapping. |
| 81 | #define UNMAPPED_BASE 0x00000000 |
| 82 | |
| 83 | #define CPM_BASE 0x00001000 |
| 84 | #define INTC_BASE 0x00002000 |
| 85 | #define TCU_BASE 0x00003000 |
| 86 | #define WDT_BASE 0x00004000 |
| 87 | #define RTC_BASE 0x00005000 |
| 88 | #define GPIO_BASE 0x00006000 |
| 89 | #define AIC_BASE 0x00007000 |
| 90 | #define MSC_BASE 0x00008000 |
| 91 | #define UART0_BASE 0x00009000 |
| 92 | #define I2C_BASE 0x0000a000 |
| 93 | #define SSI_BASE 0x0000b000 |
| 94 | #define SADC_BASE 0x0000c000 |
| 95 | #define EMC_BASE 0x0000d000 |
| 96 | #define DMAC_BASE 0x0000e000 |
| 97 | #define UHC_BASE 0x0000f000 |
| 98 | #define UDC_BASE 0x00010000 |
| 99 | #define LCD_BASE 0x00011000 |
| 100 | #define SLCD_BASE 0x00012000 |
| 101 | #define CIM_BASE 0x00013000 |
| 102 | #define ETH_BASE 0x00014000 |
| 103 | |
| 104 | // Default lcd framebuffer mapping space. |
| 105 | #define LCD_FRAMEBUFFER_BASE ((unsigned *)0x00015000) |
| 106 | |
| 107 | // Map IO memory (requires a priviledged Iris::my_thread capability). |
| 108 | #include <iris.hh> |
| 109 | static void __map_io (unsigned physical, unsigned mapping): |
| 110 | Iris::Page p = Iris::my_memory.create_page () |
| 111 | // false means not cachable; false means don't free when done. |
| 112 | p.alloc_physical (physical, false, false) |
| 113 | Iris::my_memory.map (p, mapping) |
| 114 | Iris::free_cap (p) |
| 115 | |
| 116 | #define map_cpm() do { __map_io (CPM_PHYSICAL, CPM_BASE); } while (0) |
| 117 | #define map_intc() do { __map_io (INTC_PHYSICAL, INTC_BASE); } while (0) |
| 118 | #define map_tcu() do { __map_io (TCU_PHYSICAL, TCU_BASE); } while (0) |
| 119 | #define map_wdt() do { __map_io (WDT_PHYSICAL, WDT_BASE); } while (0) |
| 120 | #define map_rtc() do { __map_io (RTC_PHYSICAL, RTC_BASE); } while (0) |
| 121 | #define map_gpio() do { __map_io (GPIO_PHYSICAL, GPIO_BASE); } while (0) |
| 122 | #define map_aic() do { __map_io (AIC_PHYSICAL, AIC_BASE); } while (0) |
| 123 | #define map_msc() do { __map_io (MSC_PHYSICAL, MSC_BASE); } while (0) |
| 124 | #define map_uart0() do { __map_io (UART0_PHYSICAL, UART0_BASE); } while (0) |
| 125 | #define map_i2c() do { __map_io (I2C_PHYSICAL, I2C_BASE); } while (0) |
| 126 | #define map_ssi() do { __map_io (SSI_PHYSICAL, SSI_BASE); } while (0) |
| 127 | #define map_sadc() do { __map_io (SADC_PHYSICAL, SADC_BASE); } while (0) |
| 128 | #define map_emc() do { __map_io (EMC_PHYSICAL, EMC_BASE); } while (0) |
| 129 | #define map_dmac() do { __map_io (DMAC_PHYSICAL, DMAC_BASE); } while (0) |
| 130 | #define map_uhc() do { __map_io (UHC_PHYSICAL, UHC_BASE); } while (0) |
| 131 | #define map_udc() do { __map_io (UDC_PHYSICAL, UDC_BASE); } while (0) |
| 132 | #define map_lcd() do { __map_io (LCD_PHYSICAL, LCD_BASE); } while (0) |
| 133 | #define map_slcd() do { __map_io (SLCD_PHYSICAL, SLCD_BASE); } while (0) |
| 134 | #define map_cim() do { __map_io (CIM_PHYSICAL, CIM_BASE); } while (0) |
| 135 | #define map_eth() do { __map_io (ETH_PHYSICAL, ETH_BASE); } while (0) |
| 136 | |
| 137 | // udelay implementation |
| 138 | void cdelay (unsigned cs): |
| 139 | Iris::my_receiver.set_alarm (cs + 1) |
| 140 | Iris::Cap ().call () |
| 141 | |
| 142 | #endif |
| 143 | |
| 144 | #define REG8(x) (*(volatile unsigned char *)(x)) |
| 145 | #define REG16(x) (*(volatile unsigned short *)(x)) |
| 146 | #define REG32(x) (*(volatile unsigned *)(x)) |
| 147 | |
| 148 | //************************************************************************ |
| 149 | // INTC (Interrupt Controller) |
| 150 | //************************************************************************ |
| 151 | #define INTC_ISR REG32 (INTC_BASE + 0x00) |
| 152 | #define INTC_IMR REG32 (INTC_BASE + 0x04) |
| 153 | #define INTC_IMSR REG32 (INTC_BASE + 0x08) |
| 154 | #define INTC_IMCR REG32 (INTC_BASE + 0x0c) |
| 155 | #define INTC_IPR REG32 (INTC_BASE + 0x10) |
| 156 | |
| 157 | #define IRQ_I2C 1 |
| 158 | #define IRQ_UHC 3 |
| 159 | #define IRQ_UART0 9 |
| 160 | #define IRQ_SADC 12 |
| 161 | #define IRQ_MSC 14 |
| 162 | #define IRQ_RTC 15 |
| 163 | #define IRQ_SSI 16 |
| 164 | #define IRQ_CIM 17 |
| 165 | #define IRQ_AIC 18 |
| 166 | #define IRQ_DMAC 20 |
| 167 | #define IRQ_TCU2 21 |
| 168 | #define IRQ_TCU1 22 |
| 169 | #define IRQ_TCU0 23 |
| 170 | #define IRQ_UDC 24 |
| 171 | #define IRQ_GPIO3 25 |
| 172 | #define IRQ_GPIO2 26 |
| 173 | #define IRQ_GPIO1 27 |
| 174 | #define IRQ_GPIO0 28 |
| 175 | #define IRQ_IPU 29 |
| 176 | #define IRQ_LCD 30 |
| 177 | |
| 178 | |
| 179 | //************************************************************************ |
| 180 | // RTC |
| 181 | //************************************************************************ |
| 182 | #define RTC_RCR REG32 (RTC_BASE + 0x00) // RTC Control Register |
| 183 | #define RTC_RSR REG32 (RTC_BASE + 0x04) // RTC Second Register |
| 184 | #define RTC_RSAR REG32 (RTC_BASE + 0x08) // RTC Second Alarm Register |
| 185 | #define RTC_RGR REG32 (RTC_BASE + 0x0c) // RTC Regulator Register |
| 186 | |
| 187 | #define RTC_HCR REG32 (RTC_BASE + 0x20) // Hibernate Control Register |
| 188 | #define RTC_HWFCR REG32 (RTC_BASE + 0x24) // Hibernate Wakeup Filter Counter Reg |
| 189 | #define RTC_HRCR REG32 (RTC_BASE + 0x28) // Hibernate Reset Counter Register |
| 190 | #define RTC_HWCR REG32 (RTC_BASE + 0x2c) // Hibernate Wakeup Control Register |
| 191 | #define RTC_HWRSR REG32 (RTC_BASE + 0x30) // Hibernate Wakeup Status Register |
| 192 | #define RTC_HSPR REG32 (RTC_BASE + 0x34) // Hibernate Scratch Pattern Register |
| 193 | |
| 194 | // RTC Control Register |
| 195 | #define RTC_RCR_WRDY_BIT 7 |
| 196 | #define RTC_RCR_WRDY (1 << 7) // Write Ready Flag |
| 197 | #define RTC_RCR_1HZ_BIT 6 |
| 198 | #define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) // 1Hz Flag |
| 199 | #define RTC_RCR_1HZIE (1 << 5) // 1Hz Interrupt Enable |
| 200 | #define RTC_RCR_AF_BIT 4 |
| 201 | #define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) // Alarm Flag |
| 202 | #define RTC_RCR_AIE (1 << 3) // Alarm Interrupt Enable |
| 203 | #define RTC_RCR_AE (1 << 2) // Alarm Enable |
| 204 | #define RTC_RCR_RTCE (1 << 0) // RTC Enable |
| 205 | |
| 206 | // RTC Regulator Register |
| 207 | #define RTC_RGR_LOCK (1 << 31) // Lock Bit |
| 208 | #define RTC_RGR_ADJC_BIT 16 |
| 209 | #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) |
| 210 | #define RTC_RGR_NC1HZ_BIT 0 |
| 211 | #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) |
| 212 | |
| 213 | // Hibernate Control Register |
| 214 | #define RTC_HCR_PD (1 << 0) // Power Down |
| 215 | |
| 216 | // Hibernate Wakeup Filter Counter Register |
| 217 | #define RTC_HWFCR_BIT 5 |
| 218 | #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) |
| 219 | |
| 220 | // Hibernate Reset Counter Register |
| 221 | #define RTC_HRCR_BIT 5 |
| 222 | #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) |
| 223 | |
| 224 | // Hibernate Wakeup Control Register |
| 225 | #define RTC_HWCR_EALM (1 << 0) // RTC alarm wakeup enable |
| 226 | |
| 227 | // Hibernate Wakeup Status Register |
| 228 | #define RTC_HWRSR_HR (1 << 5) // Hibernate reset |
| 229 | #define RTC_HWRSR_PPR (1 << 4) // PPR reset |
| 230 | #define RTC_HWRSR_PIN (1 << 1) // Wakeup pin status bit |
| 231 | #define RTC_HWRSR_ALM (1 << 0) // RTC alarm status bit |
| 232 | |
| 233 | |
| 234 | //************************************************************************ |
| 235 | // CPM (Clock reset and Power control Management) |
| 236 | //************************************************************************ |
| 237 | #define CPM_CPCCR REG32 (CPM_BASE+0x00) |
| 238 | #define CPM_CPPCR REG32 (CPM_BASE+0x10) |
| 239 | #define CPM_I2SCDR REG32 (CPM_BASE+0x60) |
| 240 | #define CPM_LPCDR REG32 (CPM_BASE+0x64) |
| 241 | #define CPM_MSCCDR REG32 (CPM_BASE+0x68) |
| 242 | #define CPM_UHCCDR REG32 (CPM_BASE+0x6C) |
| 243 | #define CPM_SSICDR REG32 (CPM_BASE+0x74) |
| 244 | |
| 245 | #define CPM_LCR REG32 (CPM_BASE+0x04) |
| 246 | #define CPM_CLKGR REG32 (CPM_BASE+0x20) |
| 247 | #define CPM_SCR REG32 (CPM_BASE+0x24) |
| 248 | |
| 249 | #define CPM_HCR REG32 (CPM_BASE+0x30) |
| 250 | #define CPM_HWFCR REG32 (CPM_BASE+0x34) |
| 251 | #define CPM_HRCR REG32 (CPM_BASE+0x38) |
| 252 | #define CPM_HWCR REG32 (CPM_BASE+0x3c) |
| 253 | #define CPM_HWSR REG32 (CPM_BASE+0x40) |
| 254 | #define CPM_HSPR REG32 (CPM_BASE+0x44) |
| 255 | |
| 256 | #define CPM_RSR REG32 (CPM_BASE+0x08) |
| 257 | |
| 258 | |
| 259 | // Clock Control Register |
| 260 | #define CPM_CPCCR_I2CS (1 << 31) |
| 261 | #define CPM_CPCCR_CLKOEN (1 << 30) |
| 262 | #define CPM_CPCCR_UCS (1 << 29) |
| 263 | #define CPM_CPCCR_UDIV_BIT 23 |
| 264 | #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) |
| 265 | #define CPM_CPCCR_CE (1 << 22) |
| 266 | #define CPM_CPCCR_PCS (1 << 21) |
| 267 | #define CPM_CPCCR_LDIV_BIT 16 |
| 268 | #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) |
| 269 | #define CPM_CPCCR_MDIV_BIT 12 |
| 270 | #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) |
| 271 | #define CPM_CPCCR_PDIV_BIT 8 |
| 272 | #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) |
| 273 | #define CPM_CPCCR_HDIV_BIT 4 |
| 274 | #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) |
| 275 | #define CPM_CPCCR_CDIV_BIT 0 |
| 276 | #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) |
| 277 | |
| 278 | // I2S Clock Divider Register |
| 279 | #define CPM_I2SCDR_I2SDIV_BIT 0 |
| 280 | #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) |
| 281 | |
| 282 | // LCD Pixel Clock Divider Register |
| 283 | #define CPM_LPCDR_PIXDIV_BIT 0 |
| 284 | #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) |
| 285 | |
| 286 | // MSC Clock Divider Register |
| 287 | #define CPM_MSCCDR_MSCDIV_BIT 0 |
| 288 | #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) |
| 289 | |
| 290 | // UHC Clock Divider Register |
| 291 | #define CPM_UHCCDR_UHCDIV_BIT 0 |
| 292 | #define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT) |
| 293 | |
| 294 | // SSI Clock Divider Register |
| 295 | #define CPM_SSICDR_SCS (1<<31) // SSI clock source selection, 0:EXCLK, 1: PLL |
| 296 | #define CPM_SSICDR_SSIDIV_BIT 0 |
| 297 | #define CPM_SSICDR_SSIDIV_MASK (0xf << CPM_SSICDR_SSIDIV_BIT) |
| 298 | |
| 299 | // PLL Control Register |
| 300 | #define CPM_CPPCR_PLLM_BIT 23 |
| 301 | #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) |
| 302 | #define CPM_CPPCR_PLLN_BIT 18 |
| 303 | #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) |
| 304 | #define CPM_CPPCR_PLLOD_BIT 16 |
| 305 | #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) |
| 306 | #define CPM_CPPCR_PLLS (1 << 10) |
| 307 | #define CPM_CPPCR_PLLBP (1 << 9) |
| 308 | #define CPM_CPPCR_PLLEN (1 << 8) |
| 309 | #define CPM_CPPCR_PLLST_BIT 0 |
| 310 | #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) |
| 311 | |
| 312 | // Low Power Control Register |
| 313 | #define CPM_LCR_DOZE_DUTY_BIT 3 |
| 314 | #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) |
| 315 | #define CPM_LCR_DOZE_ON (1 << 2) |
| 316 | #define CPM_LCR_LPM_BIT 0 |
| 317 | #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) |
| 318 | #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) |
| 319 | #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) |
| 320 | |
| 321 | // Clock Gate Register |
| 322 | #define CPM_CLKGR_UART1 (1 << 15) |
| 323 | #define CPM_CLKGR_UHC (1 << 14) |
| 324 | #define CPM_CLKGR_IPU (1 << 13) |
| 325 | #define CPM_CLKGR_DMAC (1 << 12) |
| 326 | #define CPM_CLKGR_UDC (1 << 11) |
| 327 | #define CPM_CLKGR_LCD (1 << 10) |
| 328 | #define CPM_CLKGR_CIM (1 << 9) |
| 329 | #define CPM_CLKGR_SADC (1 << 8) |
| 330 | #define CPM_CLKGR_MSC (1 << 7) |
| 331 | #define CPM_CLKGR_AIC1 (1 << 6) |
| 332 | #define CPM_CLKGR_AIC2 (1 << 5) |
| 333 | #define CPM_CLKGR_SSI (1 << 4) |
| 334 | #define CPM_CLKGR_I2C (1 << 3) |
| 335 | #define CPM_CLKGR_RTC (1 << 2) |
| 336 | #define CPM_CLKGR_TCU (1 << 1) |
| 337 | #define CPM_CLKGR_UART0 (1 << 0) |
| 338 | |
| 339 | // Sleep Control Register |
| 340 | #define CPM_SCR_O1ST_BIT 8 |
| 341 | #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) |
| 342 | #define CPM_SCR_USBPHY_ENABLE (1 << 6) |
| 343 | #define CPM_SCR_OSC_ENABLE (1 << 4) |
| 344 | |
| 345 | // Hibernate Control Register |
| 346 | #define CPM_HCR_PD (1 << 0) |
| 347 | |
| 348 | // Wakeup Filter Counter Register in Hibernate Mode |
| 349 | #define CPM_HWFCR_TIME_BIT 0 |
| 350 | #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) |
| 351 | |
| 352 | // Reset Counter Register in Hibernate Mode |
| 353 | #define CPM_HRCR_TIME_BIT 0 |
| 354 | #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) |
| 355 | |
| 356 | // Wakeup Control Register in Hibernate Mode |
| 357 | #define CPM_HWCR_WLE_LOW (0 << 2) |
| 358 | #define CPM_HWCR_WLE_HIGH (1 << 2) |
| 359 | #define CPM_HWCR_PIN_WAKEUP (1 << 1) |
| 360 | #define CPM_HWCR_RTC_WAKEUP (1 << 0) |
| 361 | |
| 362 | // Wakeup Status Register in Hibernate Mode |
| 363 | #define CPM_HWSR_WSR_PIN (1 << 1) |
| 364 | #define CPM_HWSR_WSR_RTC (1 << 0) |
| 365 | |
| 366 | // Reset Status Register |
| 367 | #define CPM_RSR_HR (1 << 2) |
| 368 | #define CPM_RSR_WR (1 << 1) |
| 369 | #define CPM_RSR_PR (1 << 0) |
| 370 | |
| 371 | |
| 372 | //************************************************************************ |
| 373 | // TCU (Timer Counter Unit) |
| 374 | //************************************************************************ |
| 375 | #define TCU_TSR REG32 (TCU_BASE + 0x1C) // Timer Stop Register |
| 376 | #define TCU_TSSR REG32 (TCU_BASE + 0x2C) // Timer Stop Set Register |
| 377 | #define TCU_TSCR REG32 (TCU_BASE + 0x3C) // Timer Stop Clear Register |
| 378 | #define TCU_TER REG8 (TCU_BASE + 0x10) // Timer Counter Enable Register |
| 379 | #define TCU_TESR REG8 (TCU_BASE + 0x14) // Timer Counter Enable Set Register |
| 380 | #define TCU_TECR REG8 (TCU_BASE + 0x18) // Timer Counter Enable Clear Register |
| 381 | #define TCU_TFR REG32 (TCU_BASE + 0x20) // Timer Flag Register |
| 382 | #define TCU_TFSR REG32 (TCU_BASE + 0x24) // Timer Flag Set Register |
| 383 | #define TCU_TFCR REG32 (TCU_BASE + 0x28) // Timer Flag Clear Register |
| 384 | #define TCU_TMR REG32 (TCU_BASE + 0x30) // Timer Mask Register |
| 385 | #define TCU_TMSR REG32 (TCU_BASE + 0x34) // Timer Mask Set Register |
| 386 | #define TCU_TMCR REG32 (TCU_BASE + 0x38) // Timer Mask Clear Register |
| 387 | |
| 388 | // n = 0,1,2,3,4,5 |
| 389 | #define TCU_TDFR(n) REG16 (TCU_BASE + (0x40 + (n)*0x10)) // Timer Data Full Reg |
| 390 | #define TCU_TDHR(n) REG16 (TCU_BASE + (0x44 + (n)*0x10)) // Timer Data Half Reg |
| 391 | #define TCU_TCNT(n) REG16 (TCU_BASE + (0x48 + (n)*0x10)) // Timer Counter Reg |
| 392 | #define TCU_TCSR(n) REG16 (TCU_BASE + (0x4C + (n)*0x10)) // Timer Control Reg |
| 393 | |
| 394 | // Register definitions |
| 395 | #define TCU_TCSR_PWM_SD (1 << 9) |
| 396 | #define TCU_TCSR_PWM_INITL_HIGH (1 << 8) |
| 397 | #define TCU_TCSR_PWM_EN (1 << 7) |
| 398 | #define TCU_TCSR_PRESCALE_BIT 3 |
| 399 | #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) |
| 400 | #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) |
| 401 | #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) |
| 402 | #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) |
| 403 | #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) |
| 404 | #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) |
| 405 | #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) |
| 406 | #define TCU_TCSR_EXT_EN (1 << 2) |
| 407 | #define TCU_TCSR_RTC_EN (1 << 1) |
| 408 | #define TCU_TCSR_PCK_EN (1 << 0) |
| 409 | |
| 410 | #define TCU_TER_TCEN(n) (1 << (n)) |
| 411 | #define TCU_TESR_TCST(n) (1 << (n)) |
| 412 | #define TCU_TECR_TCCL(n) (1 << (n)) |
| 413 | #define TCU_TFR_HFLAG(n) (1 << ((n) + 16)) |
| 414 | #define TCU_TFR_FFLAG(n) (1 << (n)) |
| 415 | #define TCU_TFSR_HFLAG(n) (1 << ((n) + 16)) |
| 416 | #define TCU_TFSR_FFLAG(n) (1 << (n)) |
| 417 | #define TCU_TFCR_HFLAG(n) (1 << ((n) + 16)) |
| 418 | #define TCU_TFCR_FFLAG(n) (1 << (n)) |
| 419 | #define TCU_TMR_HMASK(n) (1 << ((n) + 16)) |
| 420 | #define TCU_TMR_FMASK(n) (1 << (n)) |
| 421 | #define TCU_TMSR_HMST(n) (1 << ((n) + 16)) |
| 422 | #define TCU_TMSR_FMST(n) (1 << (n)) |
| 423 | #define TCU_TMCR_HMCL(n) (1 << ((n) + 16)) |
| 424 | #define TCU_TMCR_FMCL(n) (1 << (n)) |
| 425 | #define TCU_TSR_WDTS (1 << 16) |
| 426 | #define TCU_TSR_STOP(n) (1 << (n)) |
| 427 | #define TCU_TSSR_WDTSS (1 << 16) |
| 428 | #define TCU_TSSR_STPS(n) (1 << (n)) |
| 429 | #define TCU_TSSR_WDTSC (1 << 16) |
| 430 | #define TCU_TSSR_STPC(n) (1 << (n)) |
| 431 | |
| 432 | |
| 433 | //************************************************************************ |
| 434 | // WDT (WatchDog Timer) |
| 435 | //************************************************************************ |
| 436 | #define WDT_TDR REG16 (WDT_BASE + 0x00) |
| 437 | #define WDT_TCER REG8 (WDT_BASE + 0x04) |
| 438 | #define WDT_TCNT REG16 (WDT_BASE + 0x08) |
| 439 | #define WDT_TCSR REG16 (WDT_BASE + 0x0C) |
| 440 | |
| 441 | // Register definition |
| 442 | #define WDT_TCSR_PRESCALE_BIT 3 |
| 443 | #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) |
| 444 | #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) |
| 445 | #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) |
| 446 | #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) |
| 447 | #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) |
| 448 | #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) |
| 449 | #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) |
| 450 | #define WDT_TCSR_EXT_EN (1 << 2) |
| 451 | #define WDT_TCSR_RTC_EN (1 << 1) |
| 452 | #define WDT_TCSR_PCK_EN (1 << 0) |
| 453 | |
| 454 | #define WDT_TCER_TCEN (1 << 0) |
| 455 | |
| 456 | |
| 457 | //************************************************************************ |
| 458 | // DMAC (DMA Controller) |
| 459 | //************************************************************************ |
| 460 | |
| 461 | #define MAX_DMA_NUM 6 // max 6 channels |
| 462 | |
| 463 | #define DMAC_DSAR(n) REG32 (DMAC_BASE + (0x00 + (n) * 0x20)) // DMA source address |
| 464 | #define DMAC_DTAR(n) REG32 (DMAC_BASE + (0x04 + (n) * 0x20)) // DMA target address |
| 465 | #define DMAC_DTCR(n) REG32 (DMAC_BASE + (0x08 + (n) * 0x20)) // DMA transfer count |
| 466 | #define DMAC_DRSR(n) REG32 (DMAC_BASE + (0x0c + (n) * 0x20)) // DMA request source |
| 467 | #define DMAC_DCCSR(n) REG32 (DMAC_BASE + (0x10 + (n) * 0x20)) // DMA control/status |
| 468 | #define DMAC_DCMD(n) REG32 (DMAC_BASE + (0x14 + (n) * 0x20)) // DMA command |
| 469 | #define DMAC_DDA(n) REG32 (DMAC_BASE + (0x18 + (n) * 0x20)) // DMA descriptor address |
| 470 | #define DMAC_DMACR REG32 (DMAC_BASE + 0x0300) // DMA control register |
| 471 | #define DMAC_DMAIPR REG32 (DMAC_BASE + 0x0304) // DMA interrupt pending |
| 472 | #define DMAC_DMADBR REG32 (DMAC_BASE + 0x0308) // DMA doorbell |
| 473 | #define DMAC_DMADBSR REG32 (DMAC_BASE + 0x030C) // DMA doorbell set |
| 474 | |
| 475 | // DMA request source register |
| 476 | #define DMAC_DRSR_RS_BIT 0 |
| 477 | #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) |
| 478 | #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) |
| 479 | #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) |
| 480 | #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) |
| 481 | #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) |
| 482 | #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) |
| 483 | #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) |
| 484 | #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) |
| 485 | #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) |
| 486 | #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) |
| 487 | #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) |
| 488 | #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) |
| 489 | #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) |
| 490 | |
| 491 | // DMA channel control/status register |
| 492 | #define DMAC_DCCSR_NDES (1 << 31) // descriptor (0) or not (1) ? |
| 493 | #define DMAC_DCCSR_CDOA_BIT 16 // copy of DMA offset address |
| 494 | #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) |
| 495 | #define DMAC_DCCSR_INV (1 << 6) // descriptor invalid |
| 496 | #define DMAC_DCCSR_AR (1 << 4) // address error |
| 497 | #define DMAC_DCCSR_TT (1 << 3) // transfer terminated |
| 498 | #define DMAC_DCCSR_HLT (1 << 2) // DMA halted |
| 499 | #define DMAC_DCCSR_CT (1 << 1) // count terminated |
| 500 | #define DMAC_DCCSR_EN (1 << 0) // channel enable bit |
| 501 | |
| 502 | // DMA channel command register |
| 503 | #define DMAC_DCMD_SAI (1 << 23) // source address increment |
| 504 | #define DMAC_DCMD_DAI (1 << 22) // dest address increment |
| 505 | #define DMAC_DCMD_RDIL_BIT 16 // request detection interval length |
| 506 | #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) |
| 507 | #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) |
| 508 | #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) |
| 509 | #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) |
| 510 | #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) |
| 511 | #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) |
| 512 | #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) |
| 513 | #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) |
| 514 | #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) |
| 515 | #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) |
| 516 | #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) |
| 517 | #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) |
| 518 | #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) |
| 519 | #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) |
| 520 | #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) |
| 521 | #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) |
| 522 | #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) |
| 523 | #define DMAC_DCMD_SWDH_BIT 14 // source port width |
| 524 | #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) |
| 525 | #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) |
| 526 | #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) |
| 527 | #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) |
| 528 | #define DMAC_DCMD_DWDH_BIT 12 // dest port width |
| 529 | #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) |
| 530 | #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) |
| 531 | #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) |
| 532 | #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) |
| 533 | #define DMAC_DCMD_DS_BIT 8 // transfer data size of a data unit |
| 534 | #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) |
| 535 | #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) |
| 536 | #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) |
| 537 | #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) |
| 538 | #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) |
| 539 | #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) |
| 540 | #define DMAC_DCMD_TM (1 << 7) // transfer mode: 0-single 1-block |
| 541 | #define DMAC_DCMD_DES_V (1 << 4) // descriptor valid flag |
| 542 | #define DMAC_DCMD_DES_VM (1 << 3) // descriptor valid mask: 1:support V-bit |
| 543 | #define DMAC_DCMD_DES_VIE (1 << 2) // DMA valid error interrupt enable |
| 544 | #define DMAC_DCMD_TIE (1 << 1) // DMA transfer interrupt enable |
| 545 | #define DMAC_DCMD_LINK (1 << 0) // descriptor link enable |
| 546 | |
| 547 | // DMA descriptor address register |
| 548 | #define DMAC_DDA_BASE_BIT 12 // descriptor base address |
| 549 | #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) |
| 550 | #define DMAC_DDA_OFFSET_BIT 4 // descriptor offset address |
| 551 | #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) |
| 552 | |
| 553 | // DMA control register |
| 554 | #define DMAC_DMACR_PR_BIT 8 // channel priority mode |
| 555 | #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) |
| 556 | #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) |
| 557 | #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) |
| 558 | #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) |
| 559 | #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) // round robin |
| 560 | #define DMAC_DMACR_HLT (1 << 3) // DMA halt flag |
| 561 | #define DMAC_DMACR_AR (1 << 2) // address error flag |
| 562 | #define DMAC_DMACR_DMAE (1 << 0) // DMA enable bit |
| 563 | #define DMAC_DMADBR_DB (1 << 5) // doorbell |
| 564 | #define DMAC_DMADBSR_DBS (1 << 5) // enable doorbell |
| 565 | #define DMAC_DMAIPR_CIRQ(n) (1 << n) // irq pending status for channel n |
| 566 | |
| 567 | |
| 568 | //************************************************************************ |
| 569 | // GPIO (General-Purpose I/O Ports) |
| 570 | //************************************************************************ |
| 571 | #define MAX_GPIO_NUM 128 |
| 572 | |
| 573 | //n = 0,1,2,3 |
| 574 | #define GPIO_PXPIN(n) REG32 (GPIO_BASE + (0x00 + (n)*0x100)) // PIN Level Register |
| 575 | #define GPIO_PXDAT(n) REG32 (GPIO_BASE + (0x10 + (n)*0x100)) // Port Data Register 1: interrupt pending |
| 576 | #define GPIO_PXDATS(n) REG32 (GPIO_BASE + (0x14 + (n)*0x100)) // Port Data Set Register |
| 577 | #define GPIO_PXDATC(n) REG32 (GPIO_BASE + (0x18 + (n)*0x100)) // Port Data Clear Register |
| 578 | #define GPIO_PXIM(n) REG32 (GPIO_BASE + (0x20 + (n)*0x100)) // Interrupt Mask Register 1: mask pin interrupt |
| 579 | #define GPIO_PXIMS(n) REG32 (GPIO_BASE + (0x24 + (n)*0x100)) // Interrupt Mask Set Reg |
| 580 | #define GPIO_PXIMC(n) REG32 (GPIO_BASE + (0x28 + (n)*0x100)) // Interrupt Mask Clear Reg |
| 581 | #define GPIO_PXPE(n) REG32 (GPIO_BASE + (0x30 + (n)*0x100)) // Pull Enable Register 1: disable pull up/down |
| 582 | #define GPIO_PXPES(n) REG32 (GPIO_BASE + (0x34 + (n)*0x100)) // Pull Enable Set Reg. |
| 583 | #define GPIO_PXPEC(n) REG32 (GPIO_BASE + (0x38 + (n)*0x100)) // Pull Enable Clear Reg. |
| 584 | #define GPIO_PXFUN(n) REG32 (GPIO_BASE + (0x40 + (n)*0x100)) // Function Register 0: gpio; 1: function |
| 585 | #define GPIO_PXFUNS(n) REG32 (GPIO_BASE + (0x44 + (n)*0x100)) // Function Set Register |
| 586 | #define GPIO_PXFUNC(n) REG32 (GPIO_BASE + (0x48 + (n)*0x100)) // Function Clear Register |
| 587 | #define GPIO_PXSEL(n) REG32 (GPIO_BASE + (0x50 + (n)*0x100)) // Select Register 0: gpio/fun0; 1: intr/fun1 |
| 588 | #define GPIO_PXSELS(n) REG32 (GPIO_BASE + (0x54 + (n)*0x100)) // Select Set Register |
| 589 | #define GPIO_PXSELC(n) REG32 (GPIO_BASE + (0x58 + (n)*0x100)) // Select Clear Register |
| 590 | #define GPIO_PXDIR(n) REG32 (GPIO_BASE + (0x60 + (n)*0x100)) // Direction Register 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig |
| 591 | #define GPIO_PXDIRS(n) REG32 (GPIO_BASE + (0x64 + (n)*0x100)) // Direction Set Register |
| 592 | #define GPIO_PXDIRC(n) REG32 (GPIO_BASE + (0x68 + (n)*0x100)) // Direction Clear Register |
| 593 | #define GPIO_PXTRG(n) REG32 (GPIO_BASE + (0x70 + (n)*0x100)) // Trigger Register 0:level-trigger, 1:edge-trigger |
| 594 | #define GPIO_PXTRGS(n) REG32 (GPIO_BASE + (0x74 + (n)*0x100)) // Trigger Set Register |
| 595 | #define GPIO_PXTRGC(n) REG32 (GPIO_BASE + (0x78 + (n)*0x100)) // Trigger Set Register |
| 596 | #define GPIO_PXFLG(n) REG32 (GPIO_BASE + (0x80 + (n)*0x100)) // Port Flag Register interrupt flag |
| 597 | #define GPIO_PXFLGC(n) REG32 (GPIO_BASE + (0x14 + (n)*0x100)) // Port Flag Clear Register |
| 598 | |
| 599 | |
| 600 | //************************************************************************ |
| 601 | // UART |
| 602 | //************************************************************************ |
| 603 | |
| 604 | #define IRDA_BASE UART0_BASE |
| 605 | #define UART_BASE UART0_BASE |
| 606 | #define UART_OFF 0x1000 |
| 607 | |
| 608 | // Register Offset |
| 609 | #define OFF_RDR (0x00) // R 8b H'xx |
| 610 | #define OFF_TDR (0x00) // W 8b H'xx |
| 611 | #define OFF_DLLR (0x00) // RW 8b H'00 |
| 612 | #define OFF_DLHR (0x04) // RW 8b H'00 |
| 613 | #define OFF_IER (0x04) // RW 8b H'00 |
| 614 | #define OFF_ISR (0x08) // R 8b H'01 |
| 615 | #define OFF_FCR (0x08) // W 8b H'00 |
| 616 | #define OFF_LCR (0x0C) // RW 8b H'00 |
| 617 | #define OFF_MCR (0x10) // RW 8b H'00 |
| 618 | #define OFF_LSR (0x14) // R 8b H'00 |
| 619 | #define OFF_MSR (0x18) // R 8b H'00 |
| 620 | #define OFF_SPR (0x1C) // RW 8b H'00 |
| 621 | #define OFF_SIRCR (0x20) // RW 8b H'00, UART0 |
| 622 | #define OFF_UMR (0x24) // RW 8b H'00, UART M Register |
| 623 | #define OFF_UACR (0x28) // RW 8b H'00, UART Add Cycle Register |
| 624 | |
| 625 | // Register Address |
| 626 | #define UART0_RDR REG8 (UART0_BASE + OFF_RDR) |
| 627 | #define UART0_TDR REG8 (UART0_BASE + OFF_TDR) |
| 628 | #define UART0_DLLR REG8 (UART0_BASE + OFF_DLLR) |
| 629 | #define UART0_DLHR REG8 (UART0_BASE + OFF_DLHR) |
| 630 | #define UART0_IER REG8 (UART0_BASE + OFF_IER) |
| 631 | #define UART0_ISR REG8 (UART0_BASE + OFF_ISR) |
| 632 | #define UART0_FCR REG8 (UART0_BASE + OFF_FCR) |
| 633 | #define UART0_LCR REG8 (UART0_BASE + OFF_LCR) |
| 634 | #define UART0_MCR REG8 (UART0_BASE + OFF_MCR) |
| 635 | #define UART0_LSR REG8 (UART0_BASE + OFF_LSR) |
| 636 | #define UART0_MSR REG8 (UART0_BASE + OFF_MSR) |
| 637 | #define UART0_SPR REG8 (UART0_BASE + OFF_SPR) |
| 638 | #define UART0_SIRCR REG8 (UART0_BASE + OFF_SIRCR) |
| 639 | #define UART0_UMR REG8 (UART0_BASE + OFF_UMR) |
| 640 | #define UART0_UACR REG8 (UART0_BASE + OFF_UACR) |
| 641 | |
| 642 | // UART Interrupt Enable Register |
| 643 | #define UARTIER_RIE (1 << 0) // 0: receive fifo full interrupt disable |
| 644 | #define UARTIER_TIE (1 << 1) // 0: transmit fifo empty interrupt disable |
| 645 | #define UARTIER_RLIE (1 << 2) // 0: receive line status interrupt disable |
| 646 | #define UARTIER_MIE (1 << 3) // 0: modem status interrupt disable |
| 647 | #define UARTIER_RTIE (1 << 4) // 0: receive timeout interrupt disable |
| 648 | |
| 649 | // UART Interrupt Status Register |
| 650 | #define UARTISR_IP (1 << 0) // 0: interrupt is pending 1: no interrupt |
| 651 | #define UARTISR_IID (7 << 1) // Source of Interrupt |
| 652 | #define UARTISR_IID_MSI (0 << 1) // Modem status interrupt |
| 653 | #define UARTISR_IID_THRI (1 << 1) // Transmitter holding register empty |
| 654 | #define UARTISR_IID_RDI (2 << 1) // Receiver data interrupt |
| 655 | #define UARTISR_IID_RLSI (3 << 1) // Receiver line status interrupt |
| 656 | #define UARTISR_IID_RTO (6 << 1) // Receive timeout |
| 657 | #define UARTISR_FFMS (3 << 6) // FIFO mode select, set when UARTFCR.FE is set to 1 |
| 658 | #define UARTISR_FFMS_NO_FIFO (0 << 6) |
| 659 | #define UARTISR_FFMS_FIFO_MODE (3 << 6) |
| 660 | |
| 661 | // UART FIFO Control Register |
| 662 | #define UARTFCR_FE (1 << 0) // 0: non-FIFO mode 1: FIFO mode |
| 663 | #define UARTFCR_RFLS (1 << 1) // write 1 to flush receive FIFO |
| 664 | #define UARTFCR_TFLS (1 << 2) // write 1 to flush transmit FIFO |
| 665 | #define UARTFCR_DMS (1 << 3) // 0: disable DMA mode |
| 666 | #define UARTFCR_UUE (1 << 4) // 0: disable UART |
| 667 | #define UARTFCR_RTRG (3 << 6) // Receive FIFO Data Trigger |
| 668 | #define UARTFCR_RTRG_1 (0 << 6) |
| 669 | #define UARTFCR_RTRG_4 (1 << 6) |
| 670 | #define UARTFCR_RTRG_8 (2 << 6) |
| 671 | #define UARTFCR_RTRG_15 (3 << 6) |
| 672 | |
| 673 | // UART Line Control Register |
| 674 | #define UARTLCR_WLEN (3 << 0) // word length |
| 675 | #define UARTLCR_WLEN_5 (0 << 0) |
| 676 | #define UARTLCR_WLEN_6 (1 << 0) |
| 677 | #define UARTLCR_WLEN_7 (2 << 0) |
| 678 | #define UARTLCR_WLEN_8 (3 << 0) |
| 679 | #define UARTLCR_STOP (1 << 2) // 0: 1 stop bit when word length is 5,6,7,8 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 |
| 680 | #define UARTLCR_STOP1 (0 << 2) |
| 681 | #define UARTLCR_STOP2 (1 << 2) |
| 682 | #define UARTLCR_PE (1 << 3) // 0: parity disable |
| 683 | #define UARTLCR_PROE (1 << 4) // 0: even parity 1: odd parity |
| 684 | #define UARTLCR_SPAR (1 << 5) // 0: sticky parity disable |
| 685 | #define UARTLCR_SBRK (1 << 6) // write 0 normal, write 1 send break |
| 686 | #define UARTLCR_DLAB (1 << 7) // 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR |
| 687 | |
| 688 | // UART Line Status Register |
| 689 | #define UARTLSR_DR (1 << 0) // 0: receive FIFO is empty 1: receive data is ready |
| 690 | #define UARTLSR_ORER (1 << 1) // 0: no overrun error |
| 691 | #define UARTLSR_PER (1 << 2) // 0: no parity error |
| 692 | #define UARTLSR_FER (1 << 3) // 0; no framing error |
| 693 | #define UARTLSR_BRK (1 << 4) // 0: no break detected 1: receive a break signal |
| 694 | #define UARTLSR_TDRQ (1 << 5) // 1: transmit FIFO half "empty" |
| 695 | #define UARTLSR_TEMT (1 << 6) // 1: transmit FIFO and shift registers empty |
| 696 | #define UARTLSR_RFER (1 << 7) // 0: no receive error 1: receive error in FIFO mode |
| 697 | |
| 698 | // UART Modem Control Register |
| 699 | #define UARTMCR_RTS (1 << 1) // 0: RTS_ output high, 1: RTS_ output low |
| 700 | #define UARTMCR_LOOP (1 << 4) // 0: normal 1: loopback mode |
| 701 | #define UARTMCR_MCE (1 << 7) // 0: modem function is disable |
| 702 | |
| 703 | // UART Modem Status Register |
| 704 | #define UARTMSR_CCTS (1 << 0) // 1: a change on CTS_ pin |
| 705 | #define UARTMSR_CTS (1 << 4) // 0: CTS_ pin is high |
| 706 | |
| 707 | // Slow IrDA Control Register |
| 708 | #define SIRCR_TSIRE (1 << 0) // 0: transmitter is in UART mode 1: SIR mode |
| 709 | #define SIRCR_RSIRE (1 << 1) // 0: receiver is in UART mode 1: SIR mode |
| 710 | #define SIRCR_TPWS (1 << 2) // 0: transmit 0 pulse width is 3/16 of bit length 1: 0 pulse width is 1.6us for 115.2Kbps |
| 711 | #define SIRCR_TDPL (1 << 3) // 0: encoder generates a positive pulse for 0 |
| 712 | #define SIRCR_RDPL (1 << 4) // 0: decoder interprets positive pulse as 0 |
| 713 | |
| 714 | |
| 715 | //************************************************************************ |
| 716 | // AIC (AC97/I2S Controller) |
| 717 | //************************************************************************ |
| 718 | #define AIC_FR REG32 (AIC_BASE + 0x000) |
| 719 | #define AIC_CR REG32 (AIC_BASE + 0x004) |
| 720 | #define AIC_ACCR1 REG32 (AIC_BASE + 0x008) |
| 721 | #define AIC_ACCR2 REG32 (AIC_BASE + 0x00C) |
| 722 | #define AIC_I2SCR REG32 (AIC_BASE + 0x010) |
| 723 | #define AIC_SR REG32 (AIC_BASE + 0x014) |
| 724 | #define AIC_ACSR REG32 (AIC_BASE + 0x018) |
| 725 | #define AIC_I2SSR REG32 (AIC_BASE + 0x01C) |
| 726 | #define AIC_ACCAR REG32 (AIC_BASE + 0x020) |
| 727 | #define AIC_ACCDR REG32 (AIC_BASE + 0x024) |
| 728 | #define AIC_ACSAR REG32 (AIC_BASE + 0x028) |
| 729 | #define AIC_ACSDR REG32 (AIC_BASE + 0x02C) |
| 730 | #define AIC_I2SDIV REG32 (AIC_BASE + 0x030) |
| 731 | #define AIC_DR REG32 (AIC_BASE + 0x034) |
| 732 | |
| 733 | // AIC Controller Configuration Register (AIC_FR) |
| 734 | |
| 735 | #define AIC_FR_RFTH_BIT 12 // Receive FIFO Threshold |
| 736 | #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) |
| 737 | #define AIC_FR_TFTH_BIT 8 // Transmit FIFO Threshold |
| 738 | #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) |
| 739 | #define AIC_FR_LSMP (1 << 6) // Play Zero sample or last sample |
| 740 | #define AIC_FR_ICDC (1 << 5) // External(0) or Internal CODEC(1) |
| 741 | #define AIC_FR_AUSEL (1 << 4) // AC97(0) or I2S/MSB-justified(1) |
| 742 | #define AIC_FR_RST (1 << 3) // AIC registers reset |
| 743 | #define AIC_FR_BCKD (1 << 2) // I2S BIT_CLK direction, 0:input,1:output |
| 744 | #define AIC_FR_SYNCD (1 << 1) // I2S SYNC direction, 0:input,1:output |
| 745 | #define AIC_FR_ENB (1 << 0) // AIC enable bit |
| 746 | |
| 747 | // AIC Controller Common Control Register (AIC_CR) |
| 748 | |
| 749 | #define AIC_CR_OSS_BIT 19 // Output Sample Size from memory (AIC V2 only) |
| 750 | #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) |
| 751 | #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) |
| 752 | #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) |
| 753 | #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) |
| 754 | #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) |
| 755 | #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) |
| 756 | #define AIC_CR_ISS_BIT 16 // Input Sample Size from memory (AIC V2 only) |
| 757 | #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) |
| 758 | #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) |
| 759 | #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) |
| 760 | #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) |
| 761 | #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) |
| 762 | #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) |
| 763 | #define AIC_CR_RDMS (1 << 15) // Receive DMA enable |
| 764 | #define AIC_CR_TDMS (1 << 14) // Transmit DMA enable |
| 765 | #define AIC_CR_M2S (1 << 11) // Mono to Stereo enable |
| 766 | #define AIC_CR_ENDSW (1 << 10) // Endian switch enable |
| 767 | #define AIC_CR_AVSTSU (1 << 9) // Signed <-> Unsigned toggle enable |
| 768 | #define AIC_CR_FLUSH (1 << 8) // Flush FIFO |
| 769 | #define AIC_CR_EROR (1 << 6) // Enable ROR interrupt |
| 770 | #define AIC_CR_ETUR (1 << 5) // Enable TUR interrupt |
| 771 | #define AIC_CR_ERFS (1 << 4) // Enable RFS interrupt |
| 772 | #define AIC_CR_ETFS (1 << 3) // Enable TFS interrupt |
| 773 | #define AIC_CR_ENLBF (1 << 2) // Enable Loopback Function |
| 774 | #define AIC_CR_ERPL (1 << 1) // Enable Playback Function |
| 775 | #define AIC_CR_EREC (1 << 0) // Enable Record Function |
| 776 | |
| 777 | // AIC Controller AC-link Control Register 1 (AIC_ACCR1) |
| 778 | |
| 779 | #define AIC_ACCR1_RS_BIT 16 // Receive Valid Slots |
| 780 | #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) |
| 781 | #define AIC_ACCR1_RS_SLOT12 (1 << 25) // Slot 12 valid bit |
| 782 | #define AIC_ACCR1_RS_SLOT11 (1 << 24) // Slot 11 valid bit |
| 783 | #define AIC_ACCR1_RS_SLOT10 (1 << 23) // Slot 10 valid bit |
| 784 | #define AIC_ACCR1_RS_SLOT9 (1 << 22) // Slot 9 valid bit, LFE |
| 785 | #define AIC_ACCR1_RS_SLOT8 (1 << 21) // Slot 8 valid bit, Surround Right |
| 786 | #define AIC_ACCR1_RS_SLOT7 (1 << 20) // Slot 7 valid bit, Surround Left |
| 787 | #define AIC_ACCR1_RS_SLOT6 (1 << 19) // Slot 6 valid bit, PCM Center |
| 788 | #define AIC_ACCR1_RS_SLOT5 (1 << 18) // Slot 5 valid bit |
| 789 | #define AIC_ACCR1_RS_SLOT4 (1 << 17) // Slot 4 valid bit, PCM Right |
| 790 | #define AIC_ACCR1_RS_SLOT3 (1 << 16) // Slot 3 valid bit, PCM Left |
| 791 | #define AIC_ACCR1_XS_BIT 0 // Transmit Valid Slots |
| 792 | #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) |
| 793 | #define AIC_ACCR1_XS_SLOT12 (1 << 9) // Slot 12 valid bit |
| 794 | #define AIC_ACCR1_XS_SLOT11 (1 << 8) // Slot 11 valid bit |
| 795 | #define AIC_ACCR1_XS_SLOT10 (1 << 7) // Slot 10 valid bit |
| 796 | #define AIC_ACCR1_XS_SLOT9 (1 << 6) // Slot 9 valid bit, LFE |
| 797 | #define AIC_ACCR1_XS_SLOT8 (1 << 5) // Slot 8 valid bit, Surround Right |
| 798 | #define AIC_ACCR1_XS_SLOT7 (1 << 4) // Slot 7 valid bit, Surround Left |
| 799 | #define AIC_ACCR1_XS_SLOT6 (1 << 3) // Slot 6 valid bit, PCM Center |
| 800 | #define AIC_ACCR1_XS_SLOT5 (1 << 2) // Slot 5 valid bit |
| 801 | #define AIC_ACCR1_XS_SLOT4 (1 << 1) // Slot 4 valid bit, PCM Right |
| 802 | #define AIC_ACCR1_XS_SLOT3 (1 << 0) // Slot 3 valid bit, PCM Left |
| 803 | |
| 804 | // AIC Controller AC-link Control Register 2 (AIC_ACCR2) |
| 805 | |
| 806 | #define AIC_ACCR2_ERSTO (1 << 18) // Enable RSTO interrupt |
| 807 | #define AIC_ACCR2_ESADR (1 << 17) // Enable SADR interrupt |
| 808 | #define AIC_ACCR2_ECADT (1 << 16) // Enable CADT interrupt |
| 809 | #define AIC_ACCR2_OASS_BIT 8 // Output Sample Size for AC-link |
| 810 | #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) |
| 811 | #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) // Output Audio Sample Size is 20-bit |
| 812 | #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) // Output Audio Sample Size is 18-bit |
| 813 | #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) // Output Audio Sample Size is 16-bit |
| 814 | #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) // Output Audio Sample Size is 8-bit |
| 815 | #define AIC_ACCR2_IASS_BIT 6 // Output Sample Size for AC-link |
| 816 | #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) |
| 817 | #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) // Input Audio Sample Size is 20-bit |
| 818 | #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) // Input Audio Sample Size is 18-bit |
| 819 | #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) // Input Audio Sample Size is 16-bit |
| 820 | #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) // Input Audio Sample Size is 8-bit |
| 821 | #define AIC_ACCR2_SO (1 << 3) // SDATA_OUT output value |
| 822 | #define AIC_ACCR2_SR (1 << 2) // RESET# pin level |
| 823 | #define AIC_ACCR2_SS (1 << 1) // SYNC pin level |
| 824 | #define AIC_ACCR2_SA (1 << 0) // SYNC and SDATA_OUT alternation |
| 825 | |
| 826 | // AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) |
| 827 | |
| 828 | #define AIC_I2SCR_STPBK (1 << 12) // Stop BIT_CLK for I2S/MSB-justified |
| 829 | #define AIC_I2SCR_WL_BIT 1 // Input/Output Sample Size for I2S/MSB-justified |
| 830 | #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) |
| 831 | #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) // Word Length is 24 bit |
| 832 | #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) // Word Length is 20 bit |
| 833 | #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) // Word Length is 18 bit |
| 834 | #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) // Word Length is 16 bit |
| 835 | #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) // Word Length is 8 bit |
| 836 | #define AIC_I2SCR_AMSL (1 << 0) // 0:I2S, 1:MSB-justified |
| 837 | |
| 838 | // AIC Controller FIFO Status Register (AIC_SR) |
| 839 | |
| 840 | #define AIC_SR_RFL_BIT 24 // Receive FIFO Level |
| 841 | #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) |
| 842 | #define AIC_SR_TFL_BIT 8 // Transmit FIFO level |
| 843 | #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) |
| 844 | #define AIC_SR_ROR (1 << 6) // Receive FIFO Overrun |
| 845 | #define AIC_SR_TUR (1 << 5) // Transmit FIFO Underrun |
| 846 | #define AIC_SR_RFS (1 << 4) // Receive FIFO Service Request |
| 847 | #define AIC_SR_TFS (1 << 3) // Transmit FIFO Service Request |
| 848 | |
| 849 | // AIC Controller AC-link Status Register (AIC_ACSR) |
| 850 | |
| 851 | #define AIC_ACSR_SLTERR (1 << 21) // Slot Error Flag |
| 852 | #define AIC_ACSR_CRDY (1 << 20) // External CODEC Ready Flag |
| 853 | #define AIC_ACSR_CLPM (1 << 19) // External CODEC low power mode flag |
| 854 | #define AIC_ACSR_RSTO (1 << 18) // External CODEC regs read status timeout |
| 855 | #define AIC_ACSR_SADR (1 << 17) // External CODEC regs status addr and data received |
| 856 | #define AIC_ACSR_CADT (1 << 16) // Command Address and Data Transmitted |
| 857 | |
| 858 | // AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) |
| 859 | |
| 860 | #define AIC_I2SSR_BSY (1 << 2) // AIC Busy in I2S/MSB-justified format |
| 861 | |
| 862 | // AIC Controller AC97 codec Command Address Register (AIC_ACCAR) |
| 863 | |
| 864 | #define AIC_ACCAR_CAR_BIT 0 |
| 865 | #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) |
| 866 | |
| 867 | // AIC Controller AC97 codec Command Data Register (AIC_ACCDR) |
| 868 | |
| 869 | #define AIC_ACCDR_CDR_BIT 0 |
| 870 | #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) |
| 871 | |
| 872 | // AIC Controller AC97 codec Status Address Register (AIC_ACSAR) |
| 873 | |
| 874 | #define AIC_ACSAR_SAR_BIT 0 |
| 875 | #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) |
| 876 | |
| 877 | // AIC Controller AC97 codec Status Data Register (AIC_ACSDR) |
| 878 | |
| 879 | #define AIC_ACSDR_SDR_BIT 0 |
| 880 | #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) |
| 881 | |
| 882 | // AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) |
| 883 | |
| 884 | #define AIC_I2SDIV_DIV_BIT 0 |
| 885 | #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) |
| 886 | #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) // BIT_CLK of 3.072MHz |
| 887 | #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) // BIT_CLK of 2.836MHz |
| 888 | #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) // BIT_CLK of 1.418MHz |
| 889 | #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) // BIT_CLK of 1.024MHz |
| 890 | #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) // BIT_CLK of 708.92KHz |
| 891 | #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) // BIT_CLK of 512.00KHz |
| 892 | |
| 893 | |
| 894 | //************************************************************************ |
| 895 | // ICDC (Internal CODEC) |
| 896 | //************************************************************************ |
| 897 | #define ICDC_CR REG32 (ICDC_BASE + 0x0400) // ICDC Control Register |
| 898 | #define ICDC_APWAIT REG32 (ICDC_BASE + 0x0404) // Anti-Pop WAIT Stage Timing Control Register |
| 899 | #define ICDC_APPRE REG32 (ICDC_BASE + 0x0408) // Anti-Pop HPEN-PRE Stage Timing Control Register |
| 900 | #define ICDC_APHPEN REG32 (ICDC_BASE + 0x040C) // Anti-Pop HPEN Stage Timing Control Register |
| 901 | #define ICDC_APSR REG32 (ICDC_BASE + 0x0410) // Anti-Pop Status Register |
| 902 | #define ICDC_CDCCR1 REG32 (ICDC_BASE + 0x0080) |
| 903 | #define ICDC_CDCCR2 REG32 (ICDC_BASE + 0x0084) |
| 904 | |
| 905 | // ICDC Control Register |
| 906 | #define ICDC_CR_LINVOL_BIT 24 // LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 |
| 907 | #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) |
| 908 | #define ICDC_CR_ASRATE_BIT 20 // Audio Sample Rate |
| 909 | #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) |
| 910 | #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) |
| 911 | #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) |
| 912 | #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) |
| 913 | #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) |
| 914 | #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) |
| 915 | #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) |
| 916 | #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) |
| 917 | #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) |
| 918 | #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) |
| 919 | #define ICDC_CR_MICBG_BIT 18 // MIC Boost Gain |
| 920 | #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) |
| 921 | #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) |
| 922 | #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) |
| 923 | #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) |
| 924 | #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) |
| 925 | #define ICDC_CR_HPVOL_BIT 16 // Headphone Volume Gain |
| 926 | #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) |
| 927 | #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) |
| 928 | #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) |
| 929 | #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) |
| 930 | #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) |
| 931 | #define ICDC_CR_ELINEIN (1 << 13) // Enable LINE Input |
| 932 | #define ICDC_CR_EMIC (1 << 12) // Enable MIC Input |
| 933 | #define ICDC_CR_SW1ON (1 << 11) // Switch 1 in CODEC is on |
| 934 | #define ICDC_CR_EADC (1 << 10) // Enable ADC |
| 935 | #define ICDC_CR_SW2ON (1 << 9) // Switch 2 in CODEC is on |
| 936 | #define ICDC_CR_EDAC (1 << 8) // Enable DAC |
| 937 | #define ICDC_CR_HPMUTE (1 << 5) // Headphone Mute |
| 938 | #define ICDC_CR_HPTON (1 << 4) // Headphone Amplifier Trun On |
| 939 | #define ICDC_CR_HPTOFF (1 << 3) // Headphone Amplifier Trun Off |
| 940 | #define ICDC_CR_TAAP (1 << 2) // Turn Around of the Anti-Pop Procedure |
| 941 | #define ICDC_CR_EAP (1 << 1) // Enable Anti-Pop Procedure |
| 942 | #define ICDC_CR_SUSPD (1 << 0) // CODEC Suspend |
| 943 | |
| 944 | // Anti-Pop WAIT Stage Timing Control Register |
| 945 | #define ICDC_APWAIT_WAITSN_BIT 0 |
| 946 | #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) |
| 947 | |
| 948 | // Anti-Pop HPEN-PRE Stage Timing Control Register |
| 949 | #define ICDC_APPRE_PRESN_BIT 0 |
| 950 | #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) |
| 951 | |
| 952 | // Anti-Pop HPEN Stage Timing Control Register |
| 953 | #define ICDC_APHPEN_HPENSN_BIT 0 |
| 954 | #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) |
| 955 | |
| 956 | // Anti-Pop Status Register |
| 957 | #define ICDC_SR_HPST_BIT 14 // Headphone Amplifier State |
| 958 | #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) |
| 959 | #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) // HP amplifier is off |
| 960 | #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) // wait state in turn-on |
| 961 | #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) // pre-enable state in turn-on |
| 962 | #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) // HP enable state in turn-on |
| 963 | #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) // HP enable state in turn-off |
| 964 | #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) // pre-enable state in turn-off |
| 965 | #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) // wait state in turn-off |
| 966 | #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) // HP amplifier is on |
| 967 | #define ICDC_SR_SNCNT_BIT 0 // Sample Number Counter |
| 968 | #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) |
| 969 | |
| 970 | |
| 971 | //************************************************************************ |
| 972 | // I2C |
| 973 | //************************************************************************ |
| 974 | #define I2C_DR REG8 (I2C_BASE + 0x000) |
| 975 | #define I2C_CR REG8 (I2C_BASE + 0x004) |
| 976 | #define I2C_SR REG8 (I2C_BASE + 0x008) |
| 977 | #define I2C_GR REG16 (I2C_BASE + 0x00C) |
| 978 | |
| 979 | // I2C Control Register (I2C_CR) |
| 980 | |
| 981 | #define I2C_CR_IEN (1 << 4) |
| 982 | #define I2C_CR_STA (1 << 3) |
| 983 | #define I2C_CR_STO (1 << 2) |
| 984 | #define I2C_CR_AC (1 << 1) |
| 985 | #define I2C_CR_I2CE (1 << 0) |
| 986 | |
| 987 | // I2C Status Register (I2C_SR) |
| 988 | |
| 989 | #define I2C_SR_STX (1 << 4) |
| 990 | #define I2C_SR_BUSY (1 << 3) |
| 991 | #define I2C_SR_TEND (1 << 2) |
| 992 | #define I2C_SR_DRF (1 << 1) |
| 993 | #define I2C_SR_ACKF (1 << 0) |
| 994 | |
| 995 | |
| 996 | //************************************************************************ |
| 997 | // SSI |
| 998 | //************************************************************************ |
| 999 | #define SSI_DR REG32 (SSI_BASE + 0x000) |
| 1000 | #define SSI_CR0 REG16 (SSI_BASE + 0x004) |
| 1001 | #define SSI_CR1 REG32 (SSI_BASE + 0x008) |
| 1002 | #define SSI_SR REG32 (SSI_BASE + 0x00C) |
| 1003 | #define SSI_ITR REG16 (SSI_BASE + 0x010) |
| 1004 | #define SSI_ICR REG8 (SSI_BASE + 0x014) |
| 1005 | #define SSI_GR REG16 (SSI_BASE + 0x018) |
| 1006 | |
| 1007 | // SSI Data Register (SSI_DR) |
| 1008 | |
| 1009 | #define SSI_DR_GPC_BIT 0 |
| 1010 | #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) |
| 1011 | |
| 1012 | // SSI Control Register 0 (SSI_CR0) |
| 1013 | |
| 1014 | #define SSI_CR0_SSIE (1 << 15) |
| 1015 | #define SSI_CR0_TIE (1 << 14) |
| 1016 | #define SSI_CR0_RIE (1 << 13) |
| 1017 | #define SSI_CR0_TEIE (1 << 12) |
| 1018 | #define SSI_CR0_REIE (1 << 11) |
| 1019 | #define SSI_CR0_LOOP (1 << 10) |
| 1020 | #define SSI_CR0_RFINE (1 << 9) |
| 1021 | #define SSI_CR0_RFINC (1 << 8) |
| 1022 | #define SSI_CR0_FSEL (1 << 6) |
| 1023 | #define SSI_CR0_TFLUSH (1 << 2) |
| 1024 | #define SSI_CR0_RFLUSH (1 << 1) |
| 1025 | #define SSI_CR0_DISREV (1 << 0) |
| 1026 | |
| 1027 | // SSI Control Register 1 (SSI_CR1) |
| 1028 | |
| 1029 | #define SSI_CR1_FRMHL_BIT 30 |
| 1030 | #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) |
| 1031 | #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) // SSI_CE_ is low valid and SSI_CE2_ is low valid |
| 1032 | #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) // SSI_CE_ is high valid and SSI_CE2_ is low valid |
| 1033 | #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) // SSI_CE_ is low valid and SSI_CE2_ is high valid |
| 1034 | #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) // SSI_CE_ is high valid and SSI_CE2_ is high valid |
| 1035 | #define SSI_CR1_TFVCK_BIT 28 |
| 1036 | #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) |
| 1037 | #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) |
| 1038 | #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) |
| 1039 | #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) |
| 1040 | #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) |
| 1041 | #define SSI_CR1_TCKFI_BIT 26 |
| 1042 | #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) |
| 1043 | #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) |
| 1044 | #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) |
| 1045 | #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) |
| 1046 | #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) |
| 1047 | #define SSI_CR1_LFST (1 << 25) |
| 1048 | #define SSI_CR1_ITFRM (1 << 24) |
| 1049 | #define SSI_CR1_UNFIN (1 << 23) |
| 1050 | #define SSI_CR1_MULTS (1 << 22) |
| 1051 | #define SSI_CR1_FMAT_BIT 20 |
| 1052 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) |
| 1053 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) // Motorola's SPI format |
| 1054 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) // TI's SSP format |
| 1055 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) // National Microwire 1 format |
| 1056 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) // National Microwire 2 format |
| 1057 | #define SSI_CR1_TTRG_BIT 16 |
| 1058 | #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) |
| 1059 | #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) |
| 1060 | #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) |
| 1061 | #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) |
| 1062 | #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) |
| 1063 | #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) |
| 1064 | #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) |
| 1065 | #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) |
| 1066 | #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) |
| 1067 | #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) |
| 1068 | #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) |
| 1069 | #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) |
| 1070 | #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) |
| 1071 | #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) |
| 1072 | #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) |
| 1073 | #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) |
| 1074 | #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) |
| 1075 | #define SSI_CR1_MCOM_BIT 12 |
| 1076 | #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) |
| 1077 | #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) // 1-bit command selected |
| 1078 | #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) // 2-bit command selected |
| 1079 | #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) // 3-bit command selected |
| 1080 | #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) // 4-bit command selected |
| 1081 | #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) // 5-bit command selected |
| 1082 | #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) // 6-bit command selected |
| 1083 | #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) // 7-bit command selected |
| 1084 | #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) // 8-bit command selected |
| 1085 | #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) // 9-bit command selected |
| 1086 | #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) // 10-bit command selected |
| 1087 | #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) // 11-bit command selected |
| 1088 | #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) // 12-bit command selected |
| 1089 | #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) // 13-bit command selected |
| 1090 | #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) // 14-bit command selected |
| 1091 | #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) // 15-bit command selected |
| 1092 | #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) // 16-bit command selected |
| 1093 | #define SSI_CR1_RTRG_BIT 8 |
| 1094 | #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) |
| 1095 | #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) |
| 1096 | #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) |
| 1097 | #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) |
| 1098 | #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) |
| 1099 | #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) |
| 1100 | #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) |
| 1101 | #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) |
| 1102 | #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) |
| 1103 | #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) |
| 1104 | #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) |
| 1105 | #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) |
| 1106 | #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) |
| 1107 | #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) |
| 1108 | #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) |
| 1109 | #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) |
| 1110 | #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) |
| 1111 | #define SSI_CR1_FLEN_BIT 4 |
| 1112 | #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) |
| 1113 | #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) |
| 1114 | #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) |
| 1115 | #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) |
| 1116 | #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) |
| 1117 | #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) |
| 1118 | #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) |
| 1119 | #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) |
| 1120 | #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) |
| 1121 | #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) |
| 1122 | #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) |
| 1123 | #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) |
| 1124 | #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) |
| 1125 | #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) |
| 1126 | #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) |
| 1127 | #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) |
| 1128 | #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) |
| 1129 | #define SSI_CR1_PHA (1 << 1) |
| 1130 | #define SSI_CR1_POL (1 << 0) |
| 1131 | |
| 1132 | // SSI Status Register (SSI_SR) |
| 1133 | |
| 1134 | #define SSI_SR_TFIFONUM_BIT 16 |
| 1135 | #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) |
| 1136 | #define SSI_SR_RFIFONUM_BIT 8 |
| 1137 | #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) |
| 1138 | #define SSI_SR_END (1 << 7) |
| 1139 | #define SSI_SR_BUSY (1 << 6) |
| 1140 | #define SSI_SR_TFF (1 << 5) |
| 1141 | #define SSI_SR_RFE (1 << 4) |
| 1142 | #define SSI_SR_TFHE (1 << 3) |
| 1143 | #define SSI_SR_RFHF (1 << 2) |
| 1144 | #define SSI_SR_UNDR (1 << 1) |
| 1145 | #define SSI_SR_OVER (1 << 0) |
| 1146 | |
| 1147 | // SSI Interval Time Control Register (SSI_ITR) |
| 1148 | |
| 1149 | #define SSI_ITR_CNTCLK (1 << 15) |
| 1150 | #define SSI_ITR_IVLTM_BIT 0 |
| 1151 | #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) |
| 1152 | |
| 1153 | |
| 1154 | //************************************************************************ |
| 1155 | // MSC |
| 1156 | //************************************************************************ |
| 1157 | #define MSC_STRPCL REG16 (MSC_BASE + 0x000) |
| 1158 | #define MSC_STAT REG32 (MSC_BASE + 0x004) |
| 1159 | #define MSC_CLKRT REG16 (MSC_BASE + 0x008) |
| 1160 | #define MSC_CMDAT REG32 (MSC_BASE + 0x00C) |
| 1161 | #define MSC_RESTO REG16 (MSC_BASE + 0x010) |
| 1162 | #define MSC_RDTO REG16 (MSC_BASE + 0x014) |
| 1163 | #define MSC_BLKLEN REG16 (MSC_BASE + 0x018) |
| 1164 | #define MSC_NOB REG16 (MSC_BASE + 0x01C) |
| 1165 | #define MSC_SNOB REG16 (MSC_BASE + 0x020) |
| 1166 | #define MSC_IMASK REG16 (MSC_BASE + 0x024) |
| 1167 | #define MSC_IREG REG16 (MSC_BASE + 0x028) |
| 1168 | #define MSC_CMD REG8 (MSC_BASE + 0x02C) |
| 1169 | #define MSC_ARG REG32 (MSC_BASE + 0x030) |
| 1170 | #define MSC_RES REG16 (MSC_BASE + 0x034) |
| 1171 | #define MSC_RXFIFO REG32 (MSC_BASE + 0x038) |
| 1172 | #define MSC_TXFIFO REG32 (MSC_BASE + 0x03C) |
| 1173 | |
| 1174 | // MSC Clock and Control Register (MSC_STRPCL) |
| 1175 | |
| 1176 | #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) |
| 1177 | #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) |
| 1178 | #define MSC_STRPCL_START_READWAIT (1 << 5) |
| 1179 | #define MSC_STRPCL_STOP_READWAIT (1 << 4) |
| 1180 | #define MSC_STRPCL_RESET (1 << 3) |
| 1181 | #define MSC_STRPCL_START_OP (1 << 2) |
| 1182 | #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 |
| 1183 | #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) |
| 1184 | #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) // Stop MMC/SD clock |
| 1185 | #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) // Start MMC/SD clock |
| 1186 | |
| 1187 | // MSC Status Register (MSC_STAT) |
| 1188 | |
| 1189 | #define MSC_STAT_IS_RESETTING (1 << 15) |
| 1190 | #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) |
| 1191 | #define MSC_STAT_PRG_DONE (1 << 13) |
| 1192 | #define MSC_STAT_DATA_TRAN_DONE (1 << 12) |
| 1193 | #define MSC_STAT_END_CMD_RES (1 << 11) |
| 1194 | #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) |
| 1195 | #define MSC_STAT_IS_READWAIT (1 << 9) |
| 1196 | #define MSC_STAT_CLK_EN (1 << 8) |
| 1197 | #define MSC_STAT_DATA_FIFO_FULL (1 << 7) |
| 1198 | #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) |
| 1199 | #define MSC_STAT_CRC_RES_ERR (1 << 5) |
| 1200 | #define MSC_STAT_CRC_READ_ERROR (1 << 4) |
| 1201 | #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 |
| 1202 | #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) |
| 1203 | #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) // No error on transmission of data |
| 1204 | #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) // Card observed erroneous transmission of data |
| 1205 | #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) // No CRC status is sent back |
| 1206 | #define MSC_STAT_TIME_OUT_RES (1 << 1) |
| 1207 | #define MSC_STAT_TIME_OUT_READ (1 << 0) |
| 1208 | |
| 1209 | // MSC Bus Clock Control Register (MSC_CLKRT) |
| 1210 | |
| 1211 | #define MSC_CLKRT_CLK_RATE_BIT 0 |
| 1212 | #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) |
| 1213 | #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) // CLK_SRC |
| 1214 | #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) // 1/2 of CLK_SRC |
| 1215 | #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) // 1/4 of CLK_SRC |
| 1216 | #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) // 1/8 of CLK_SRC |
| 1217 | #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) // 1/16 of CLK_SRC |
| 1218 | #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) // 1/32 of CLK_SRC |
| 1219 | #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) // 1/64 of CLK_SRC |
| 1220 | #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) // 1/128 of CLK_SRC |
| 1221 | |
| 1222 | // MSC Command Sequence Control Register (MSC_CMDAT) |
| 1223 | |
| 1224 | #define MSC_CMDAT_IO_ABORT (1 << 11) |
| 1225 | #define MSC_CMDAT_BUS_WIDTH_BIT 9 |
| 1226 | #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 1227 | #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) // 1-bit data bus |
| 1228 | #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) // 4-bit data bus |
| 1229 | #define MSC_CMDAT_DMA_EN (1 << 8) |
| 1230 | #define MSC_CMDAT_INIT (1 << 7) |
| 1231 | #define MSC_CMDAT_BUSY (1 << 6) |
| 1232 | #define MSC_CMDAT_STREAM_BLOCK (1 << 5) |
| 1233 | #define MSC_CMDAT_WRITE (1 << 4) |
| 1234 | #define MSC_CMDAT_READ (0 << 4) |
| 1235 | #define MSC_CMDAT_DATA_EN (1 << 3) |
| 1236 | #define MSC_CMDAT_RESPONSE_BIT 0 |
| 1237 | #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) |
| 1238 | #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) // No response |
| 1239 | #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) // Format R1 and R1b |
| 1240 | #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) // Format R2 |
| 1241 | #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) // Format R3 |
| 1242 | #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) // Format R4 |
| 1243 | #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) // Format R5 |
| 1244 | #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) // Format R6 |
| 1245 | #define MSC_CMDAT_RESPONSE_R7 (0x7 << MSC_CMDAT_RESPONSE_BIT) // Format R7 |
| 1246 | |
| 1247 | #define MSC_CMDAT_DMA_EN (1 << 8) |
| 1248 | #define MSC_CMDAT_INIT (1 << 7) |
| 1249 | #define MSC_CMDAT_BUSY (1 << 6) |
| 1250 | #define MSC_CMDAT_STREAM (1 << 5) |
| 1251 | #define MSC_CMDAT_WRITE (1 << 4) |
| 1252 | #define MSC_CMDAT_DATA_EN (1 << 3) |
| 1253 | |
| 1254 | // MSC Interrupts Mask Register (MSC_IMASK) |
| 1255 | |
| 1256 | #define MSC_IMASK_SDIO (1 << 7) |
| 1257 | #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) |
| 1258 | #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) |
| 1259 | #define MSC_IMASK_END_CMD_RES (1 << 2) |
| 1260 | #define MSC_IMASK_PRG_DONE (1 << 1) |
| 1261 | #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) |
| 1262 | |
| 1263 | |
| 1264 | // MSC Interrupts Status Register (MSC_IREG) |
| 1265 | |
| 1266 | #define MSC_IREG_SDIO (1 << 7) |
| 1267 | #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) |
| 1268 | #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) |
| 1269 | #define MSC_IREG_END_CMD_RES (1 << 2) |
| 1270 | #define MSC_IREG_PRG_DONE (1 << 1) |
| 1271 | #define MSC_IREG_DATA_TRAN_DONE (1 << 0) |
| 1272 | |
| 1273 | |
| 1274 | //************************************************************************ |
| 1275 | // EMC (External Memory Controller) |
| 1276 | //************************************************************************ |
| 1277 | #define EMC_SMCR(n) REG32 (EMC_BASE + 0x10 + 4 * (n)) // Static Memory Control Register n (n = 0,1,2,3,4) |
| 1278 | #define EMC_SACR(n) REG32 (EMC_BASE + 0x30 + 4 * (n)) // Static Memory Bank n Addr Config Reg (n = 0,1,2,3,4) |
| 1279 | |
| 1280 | #define EMC_NFCSR REG32 (EMC_BASE + 0x050) // NAND Flash Control/Status Register |
| 1281 | #define EMC_NFECR REG32 (EMC_BASE + 0x100) // NAND Flash ECC Control Register |
| 1282 | #define EMC_NFECC REG32 (EMC_BASE + 0x104) // NAND Flash ECC Data Register |
| 1283 | #define EMC_NFPAR(n) REG32 (EMC_BASE + 0x108 + 4 * (n)) // NAND Flash RS Parity n Register (n = 0,1,2) |
| 1284 | #define EMC_NFINTS REG32 (EMC_BASE + 0x114) // NAND Flash Interrupt Status Register |
| 1285 | #define EMC_NFINTE REG32 (EMC_BASE + 0x118) // NAND Flash Interrupt Enable Register |
| 1286 | #define EMC_NFERR(n) REG32 (EMC_BASE + 0x11c + 4 * (n)) // NAND Flash RS Error Report n Register (n = 0,1,2,3) |
| 1287 | |
| 1288 | #define EMC_DMCR REG32 (EMC_BASE + 0x80) // DRAM Control Register |
| 1289 | #define EMC_RTCSR REG16 (EMC_BASE + 0x84) // Refresh Time Control/Status Register |
| 1290 | #define EMC_RTCNT REG16 (EMC_BASE + 0x88) // Refresh Timer Counter |
| 1291 | #define EMC_RTCOR REG16 (EMC_BASE + 0x8c) // Refresh Time Constant Register |
| 1292 | #define EMC_DMAR0 REG32 (EMC_BASE + 0x90) // SDRAM Bank 0 Addr Config Register |
| 1293 | #define EMC_SDMR0 (EMC_BASE + 0xa000) // Mode Register of SDRAM bank 0. Very weird: uses address bus for data. Data bus is ignored, thus no REG |
| 1294 | #define EMC_BCR REG32 (EMC_BASE + 0x00) // Bus Control Register |
| 1295 | |
| 1296 | // Static Memory Control Register |
| 1297 | #define EMC_SMCR_STRV_BIT 24 |
| 1298 | #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) |
| 1299 | #define EMC_SMCR_TAW_BIT 20 |
| 1300 | #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) |
| 1301 | #define EMC_SMCR_TBP_BIT 16 |
| 1302 | #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) |
| 1303 | #define EMC_SMCR_TAH_BIT 12 |
| 1304 | #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) |
| 1305 | #define EMC_SMCR_TAS_BIT 8 |
| 1306 | #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) |
| 1307 | #define EMC_SMCR_BW_BIT 6 |
| 1308 | #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) |
| 1309 | #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) |
| 1310 | #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) |
| 1311 | #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) |
| 1312 | #define EMC_SMCR_BCM (1 << 3) |
| 1313 | #define EMC_SMCR_BL_BIT 1 |
| 1314 | #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) |
| 1315 | #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) |
| 1316 | #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) |
| 1317 | #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) |
| 1318 | #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) |
| 1319 | #define EMC_SMCR_SMT (1 << 0) |
| 1320 | |
| 1321 | // Static Memory Bank Addr Config Reg |
| 1322 | #define EMC_SACR_BASE_BIT 8 |
| 1323 | #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) |
| 1324 | #define EMC_SACR_MASK_BIT 0 |
| 1325 | #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) |
| 1326 | |
| 1327 | // NAND Flash Control/Status Register |
| 1328 | #define EMC_NFCSR_NFCE4 (1 << 7) // NAND Flash Enable |
| 1329 | #define EMC_NFCSR_NFE4 (1 << 6) // NAND Flash FCE# Assertion Enable |
| 1330 | #define EMC_NFCSR_NFCE3 (1 << 5) |
| 1331 | #define EMC_NFCSR_NFE3 (1 << 4) |
| 1332 | #define EMC_NFCSR_NFCE2 (1 << 3) |
| 1333 | #define EMC_NFCSR_NFE2 (1 << 2) |
| 1334 | #define EMC_NFCSR_NFCE1 (1 << 1) |
| 1335 | #define EMC_NFCSR_NFE1 (1 << 0) |
| 1336 | |
| 1337 | // NAND Flash ECC Control Register |
| 1338 | #define EMC_NFECR_PRDY (1 << 4) // Parity Ready |
| 1339 | #define EMC_NFECR_RS_DECODING (0 << 3) // RS is in decoding phase |
| 1340 | #define EMC_NFECR_RS_ENCODING (1 << 3) // RS is in encoding phase |
| 1341 | #define EMC_NFECR_HAMMING (0 << 2) // Select HAMMING Correction Algorithm |
| 1342 | #define EMC_NFECR_RS (1 << 2) // Select RS Correction Algorithm |
| 1343 | #define EMC_NFECR_ERST (1 << 1) // ECC Reset |
| 1344 | #define EMC_NFECR_ECCE (1 << 0) // ECC Enable |
| 1345 | |
| 1346 | // NAND Flash ECC Data Register |
| 1347 | #define EMC_NFECC_ECC2_BIT 16 |
| 1348 | #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) |
| 1349 | #define EMC_NFECC_ECC1_BIT 8 |
| 1350 | #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) |
| 1351 | #define EMC_NFECC_ECC0_BIT 0 |
| 1352 | #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) |
| 1353 | |
| 1354 | // NAND Flash Interrupt Status Register |
| 1355 | #define EMC_NFINTS_ERRCNT_BIT 29 // Error Count |
| 1356 | #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) |
| 1357 | #define EMC_NFINTS_PADF (1 << 4) // Padding Finished |
| 1358 | #define EMC_NFINTS_DECF (1 << 3) // Decoding Finished |
| 1359 | #define EMC_NFINTS_ENCF (1 << 2) // Encoding Finished |
| 1360 | #define EMC_NFINTS_UNCOR (1 << 1) // Uncorrectable Error Occurred |
| 1361 | #define EMC_NFINTS_ERR (1 << 0) // Error Occurred |
| 1362 | |
| 1363 | // NAND Flash Interrupt Enable Register |
| 1364 | #define EMC_NFINTE_PADFE (1 << 4) // Padding Finished Interrupt Enable |
| 1365 | #define EMC_NFINTE_DECFE (1 << 3) // Decoding Finished Interrupt Enable |
| 1366 | #define EMC_NFINTE_ENCFE (1 << 2) // Encoding Finished Interrupt Enable |
| 1367 | #define EMC_NFINTE_UNCORE (1 << 1) // Uncorrectable Error Occurred Intr Enable |
| 1368 | #define EMC_NFINTE_ERRE (1 << 0) // Error Occurred Interrupt |
| 1369 | |
| 1370 | // NAND Flash RS Error Report Register |
| 1371 | #define EMC_NFERR_INDEX_BIT 16 // Error Symbol Index |
| 1372 | #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) |
| 1373 | #define EMC_NFERR_MASK_BIT 0 // Error Symbol Value |
| 1374 | #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) |
| 1375 | |
| 1376 | |
| 1377 | // DRAM Control Register |
| 1378 | #define EMC_DMCR_BW_BIT 31 |
| 1379 | #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) |
| 1380 | #define EMC_DMCR_CA_BIT 26 |
| 1381 | #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) |
| 1382 | #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) |
| 1383 | #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) |
| 1384 | #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) |
| 1385 | #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) |
| 1386 | #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) |
| 1387 | #define EMC_DMCR_RMODE (1 << 25) |
| 1388 | #define EMC_DMCR_RFSH (1 << 24) |
| 1389 | #define EMC_DMCR_MRSET (1 << 23) |
| 1390 | #define EMC_DMCR_RA_BIT 20 |
| 1391 | #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) |
| 1392 | #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) |
| 1393 | #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) |
| 1394 | #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) |
| 1395 | #define EMC_DMCR_BA_BIT 19 |
| 1396 | #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) |
| 1397 | #define EMC_DMCR_PDM (1 << 18) |
| 1398 | #define EMC_DMCR_EPIN (1 << 17) |
| 1399 | #define EMC_DMCR_TRAS_BIT 13 |
| 1400 | #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) |
| 1401 | #define EMC_DMCR_RCD_BIT 11 |
| 1402 | #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) |
| 1403 | #define EMC_DMCR_TPC_BIT 8 |
| 1404 | #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) |
| 1405 | #define EMC_DMCR_TRWL_BIT 5 |
| 1406 | #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) |
| 1407 | #define EMC_DMCR_TRC_BIT 2 |
| 1408 | #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) |
| 1409 | #define EMC_DMCR_TCL_BIT 0 |
| 1410 | #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) |
| 1411 | |
| 1412 | // Refresh Time Control/Status Register |
| 1413 | #define EMC_RTCSR_CMF (1 << 7) |
| 1414 | #define EMC_RTCSR_CKS_BIT 0 |
| 1415 | #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) |
| 1416 | #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) |
| 1417 | #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) |
| 1418 | #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) |
| 1419 | #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) |
| 1420 | #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) |
| 1421 | #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) |
| 1422 | #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) |
| 1423 | #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) |
| 1424 | |
| 1425 | // SDRAM Bank Address Configuration Register |
| 1426 | #define EMC_DMAR_BASE_BIT 8 |
| 1427 | #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) |
| 1428 | #define EMC_DMAR_MASK_BIT 0 |
| 1429 | #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) |
| 1430 | |
| 1431 | // Mode Register of SDRAM bank 0 |
| 1432 | #define EMC_SDMR_BM (1 << 9) // Write Burst Mode |
| 1433 | #define EMC_SDMR_OM_BIT 7 // Operating Mode |
| 1434 | #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) |
| 1435 | #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) |
| 1436 | #define EMC_SDMR_CAS_BIT 4 // CAS Latency |
| 1437 | #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) |
| 1438 | #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) |
| 1439 | #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) |
| 1440 | #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) |
| 1441 | #define EMC_SDMR_BT_BIT 3 // Burst Type |
| 1442 | #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) |
| 1443 | #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) // Sequential |
| 1444 | #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) // Interleave |
| 1445 | #define EMC_SDMR_BL_BIT 0 // Burst Length |
| 1446 | #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) |
| 1447 | #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) |
| 1448 | #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) |
| 1449 | #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) |
| 1450 | #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) |
| 1451 | |
| 1452 | #define EMC_SDMR_CAS2_16BIT (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| 1453 | #define EMC_SDMR_CAS2_32BIT (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| 1454 | #define EMC_SDMR_CAS3_16BIT (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| 1455 | #define EMC_SDMR_CAS3_32BIT (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| 1456 | |
| 1457 | |
| 1458 | //************************************************************************ |
| 1459 | // CIM |
| 1460 | //************************************************************************ |
| 1461 | #define CIM_CFG REG32 (CIM_BASE + 0x0000) |
| 1462 | #define CIM_CTRL REG32 (CIM_BASE + 0x0004) |
| 1463 | #define CIM_STATE REG32 (CIM_BASE + 0x0008) |
| 1464 | #define CIM_IID REG32 (CIM_BASE + 0x000C) |
| 1465 | #define CIM_RXFIFO REG32 (CIM_BASE + 0x0010) |
| 1466 | #define CIM_DA REG32 (CIM_BASE + 0x0020) |
| 1467 | #define CIM_FA REG32 (CIM_BASE + 0x0024) |
| 1468 | #define CIM_FID REG32 (CIM_BASE + 0x0028) |
| 1469 | #define CIM_CMD REG32 (CIM_BASE + 0x002C) |
| 1470 | |
| 1471 | // CIM Configuration Register (CIM_CFG) |
| 1472 | |
| 1473 | #define CIM_CFG_INV_DAT (1 << 15) |
| 1474 | #define CIM_CFG_VSP (1 << 14) |
| 1475 | #define CIM_CFG_HSP (1 << 13) |
| 1476 | #define CIM_CFG_PCP (1 << 12) |
| 1477 | #define CIM_CFG_DUMMY_ZERO (1 << 9) |
| 1478 | #define CIM_CFG_EXT_VSYNC (1 << 8) |
| 1479 | #define CIM_CFG_PACK_BIT 4 |
| 1480 | #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) |
| 1481 | #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) |
| 1482 | #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) |
| 1483 | #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) |
| 1484 | #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) |
| 1485 | #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) |
| 1486 | #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) |
| 1487 | #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) |
| 1488 | #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) |
| 1489 | #define CIM_CFG_DSM_BIT 0 |
| 1490 | #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) |
| 1491 | #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) // CCIR656 Progressive Mode |
| 1492 | #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) // CCIR656 Interlace Mode |
| 1493 | #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) // Gated Clock Mode |
| 1494 | #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) // Non-Gated Clock Mode |
| 1495 | |
| 1496 | // CIM Control Register (CIM_CTRL) |
| 1497 | |
| 1498 | #define CIM_CTRL_MCLKDIV_BIT 24 |
| 1499 | #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) |
| 1500 | #define CIM_CTRL_FRC_BIT 16 |
| 1501 | #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) |
| 1502 | #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) // Sample every frame |
| 1503 | #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) // Sample 1/2 frame |
| 1504 | #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) // Sample 1/3 frame |
| 1505 | #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) // Sample 1/4 frame |
| 1506 | #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) // Sample 1/5 frame |
| 1507 | #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) // Sample 1/6 frame |
| 1508 | #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) // Sample 1/7 frame |
| 1509 | #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) // Sample 1/8 frame |
| 1510 | #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) // Sample 1/9 frame |
| 1511 | #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) // Sample 1/10 frame |
| 1512 | #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) // Sample 1/11 frame |
| 1513 | #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) // Sample 1/12 frame |
| 1514 | #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) // Sample 1/13 frame |
| 1515 | #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) // Sample 1/14 frame |
| 1516 | #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) // Sample 1/15 frame |
| 1517 | #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) // Sample 1/16 frame |
| 1518 | #define CIM_CTRL_VDDM (1 << 13) |
| 1519 | #define CIM_CTRL_DMA_SOFM (1 << 12) |
| 1520 | #define CIM_CTRL_DMA_EOFM (1 << 11) |
| 1521 | #define CIM_CTRL_DMA_STOPM (1 << 10) |
| 1522 | #define CIM_CTRL_RXF_TRIGM (1 << 9) |
| 1523 | #define CIM_CTRL_RXF_OFM (1 << 8) |
| 1524 | #define CIM_CTRL_RXF_TRIG_BIT 4 |
| 1525 | #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) |
| 1526 | #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) // RXFIFO Trigger Value is 4 |
| 1527 | #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) // RXFIFO Trigger Value is 8 |
| 1528 | #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) // RXFIFO Trigger Value is 12 |
| 1529 | #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) // RXFIFO Trigger Value is 16 |
| 1530 | #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) // RXFIFO Trigger Value is 20 |
| 1531 | #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) // RXFIFO Trigger Value is 24 |
| 1532 | #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) // RXFIFO Trigger Value is 28 |
| 1533 | #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) // RXFIFO Trigger Value is 32 |
| 1534 | #define CIM_CTRL_DMA_EN (1 << 2) |
| 1535 | #define CIM_CTRL_RXF_RST (1 << 1) |
| 1536 | #define CIM_CTRL_ENA (1 << 0) |
| 1537 | |
| 1538 | // CIM State Register (CIM_STATE) |
| 1539 | |
| 1540 | #define CIM_STATE_DMA_SOF (1 << 6) |
| 1541 | #define CIM_STATE_DMA_EOF (1 << 5) |
| 1542 | #define CIM_STATE_DMA_STOP (1 << 4) |
| 1543 | #define CIM_STATE_RXF_OF (1 << 3) |
| 1544 | #define CIM_STATE_RXF_TRIG (1 << 2) |
| 1545 | #define CIM_STATE_RXF_EMPTY (1 << 1) |
| 1546 | #define CIM_STATE_VDD (1 << 0) |
| 1547 | |
| 1548 | // CIM DMA Command Register (CIM_CMD) |
| 1549 | |
| 1550 | #define CIM_CMD_SOFINT (1 << 31) |
| 1551 | #define CIM_CMD_EOFINT (1 << 30) |
| 1552 | #define CIM_CMD_STOP (1 << 28) |
| 1553 | #define CIM_CMD_LEN_BIT 0 |
| 1554 | #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) |
| 1555 | |
| 1556 | |
| 1557 | //************************************************************************ |
| 1558 | // SADC (Smart A/D Controller) |
| 1559 | //************************************************************************ |
| 1560 | |
| 1561 | #define SADC_ENA REG8 (SADC_BASE + 0x00) // ADC Enable Register |
| 1562 | #define SADC_CFG REG32 (SADC_BASE + 0x04) // ADC Configure Register |
| 1563 | #define SADC_CTRL REG8 (SADC_BASE + 0x08) // ADC Control Register |
| 1564 | #define SADC_STATE REG8 (SADC_BASE + 0x0C) // ADC Status Register*/ |
| 1565 | #define SADC_SAMETIME REG16 (SADC_BASE + 0x10) // ADC Same Point Time Register |
| 1566 | #define SADC_WAITTIME REG16 (SADC_BASE + 0x14) // ADC Wait Time Register |
| 1567 | #define SADC_TSDAT REG32 (SADC_BASE + 0x18) // ADC Touch Screen Data Register |
| 1568 | #define SADC_BATDAT REG16 (SADC_BASE + 0x1C) // ADC PBAT Data Register |
| 1569 | #define SADC_SADDAT REG16 (SADC_BASE + 0x20) // ADC SADCIN Data Register |
| 1570 | |
| 1571 | // ADC Enable Register |
| 1572 | #define SADC_ENA_ADEN (1 << 7) // Touch Screen Enable |
| 1573 | #define SADC_ENA_TSEN (1 << 2) // Touch Screen Enable |
| 1574 | #define SADC_ENA_PBATEN (1 << 1) // PBAT Enable |
| 1575 | #define SADC_ENA_SADCINEN (1 << 0) // SADCIN Enable |
| 1576 | |
| 1577 | // ADC Configure Register |
| 1578 | #define SADC_CFG_EXIN (1 << 30) |
| 1579 | #define SADC_CFG_CLKOUT_NUM_BIT 16 |
| 1580 | #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) |
| 1581 | #define SADC_CFG_TS_DMA (1 << 15) // Touch Screen DMA Enable |
| 1582 | #define SADC_CFG_XYZ_BIT 13 // XYZ selection |
| 1583 | #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) |
| 1584 | #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) |
| 1585 | #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) |
| 1586 | #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) |
| 1587 | #define SADC_CFG_SNUM_BIT 10 // Sample Number |
| 1588 | #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) |
| 1589 | #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) |
| 1590 | #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) |
| 1591 | #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) |
| 1592 | #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) |
| 1593 | #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) |
| 1594 | #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) |
| 1595 | #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) |
| 1596 | #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) |
| 1597 | #define SADC_CFG_CLKDIV_BIT 5 // AD Converter frequency clock divider |
| 1598 | #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) |
| 1599 | #define SADC_CFG_PBAT_HIGH (0 << 4) // PBAT >= 2.5V |
| 1600 | #define SADC_CFG_PBAT_LOW (1 << 4) // PBAT < 2.5V |
| 1601 | #define SADC_CFG_CMD_BIT 0 // ADC Command |
| 1602 | #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) |
| 1603 | #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) // X Single-End |
| 1604 | #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) // Y Single-End |
| 1605 | #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) // X Differential |
| 1606 | #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) // Y Differential |
| 1607 | #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) // Z1 Differential |
| 1608 | #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) // Z2 Differential |
| 1609 | #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) // Z3 Differential |
| 1610 | #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) // Z4 Differential |
| 1611 | #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) // Touch Pressure |
| 1612 | #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) // PBAT >= 2.5V |
| 1613 | #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) // PBAT < 2.5V |
| 1614 | #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) // Measure SADCIN |
| 1615 | #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) // INT_PEN Enable |
| 1616 | |
| 1617 | // ADC Control Register |
| 1618 | #define SADC_CTRL_PENDM (1 << 4) // Pen Down Interrupt Mask |
| 1619 | #define SADC_CTRL_PENUM (1 << 3) // Pen Up Interrupt Mask |
| 1620 | #define SADC_CTRL_TSRDYM (1 << 2) // Touch Screen Data Ready Interrupt Mask |
| 1621 | #define SADC_CTRL_PBATRDYM (1 << 1) // PBAT Data Ready Interrupt Mask |
| 1622 | #define SADC_CTRL_SRDYM (1 << 0) // SADCIN Data Ready Interrupt Mask |
| 1623 | |
| 1624 | // ADC Status Register |
| 1625 | #define SADC_STATE_TSBUSY (1 << 7) // TS A/D is working |
| 1626 | #define SADC_STATE_PBATBUSY (1 << 6) // PBAT A/D is working |
| 1627 | #define SADC_STATE_SBUSY (1 << 5) // SADCIN A/D is working |
| 1628 | #define SADC_STATE_PEND (1 << 4) // Pen Down Interrupt Flag |
| 1629 | #define SADC_STATE_PENU (1 << 3) // Pen Up Interrupt Flag |
| 1630 | #define SADC_STATE_TSRDY (1 << 2) // Touch Screen Data Ready Interrupt Flag |
| 1631 | #define SADC_STATE_PBATRDY (1 << 1) // PBAT Data Ready Interrupt Flag |
| 1632 | #define SADC_STATE_SRDY (1 << 0) // SADCIN Data Ready Interrupt Flag |
| 1633 | |
| 1634 | // ADC Touch Screen Data Register |
| 1635 | #define SADC_TSDAT_DATA0_BIT 0 |
| 1636 | #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) |
| 1637 | #define SADC_TSDAT_TYPE0 (1 << 15) |
| 1638 | #define SADC_TSDAT_DATA1_BIT 16 |
| 1639 | #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) |
| 1640 | #define SADC_TSDAT_TYPE1 (1 << 31) |
| 1641 | |
| 1642 | |
| 1643 | //************************************************************************ |
| 1644 | // SLCD (Smart LCD Controller) |
| 1645 | //************************************************************************ |
| 1646 | |
| 1647 | #define SLCD_CFG REG32 (SLCD_BASE + 0xA0) // SLCD Configure Register |
| 1648 | #define SLCD_CTRL REG8 (SLCD_BASE + 0xA4) // SLCD Control Register |
| 1649 | #define SLCD_STATE REG8 (SLCD_BASE + 0xA8) // SLCD Status Register |
| 1650 | #define SLCD_DATA REG32 (SLCD_BASE + 0xAC) // SLCD Data Register |
| 1651 | #define SLCD_FIFO REG32 (SLCD_BASE + 0xB0) // SLCD FIFO Register |
| 1652 | |
| 1653 | // SLCD Configure Register |
| 1654 | #define SLCD_CFG_BURST_BIT 14 |
| 1655 | #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) |
| 1656 | #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) |
| 1657 | #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) |
| 1658 | #define SLCD_CFG_DWIDTH_BIT 10 |
| 1659 | #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) |
| 1660 | #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) |
| 1661 | #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) |
| 1662 | #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) |
| 1663 | #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) |
| 1664 | #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT) |
| 1665 | #define SLCD_CFG_CWIDTH_16BIT (0 << 8) |
| 1666 | #define SLCD_CFG_CWIDTH_8BIT (1 << 8) |
| 1667 | #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) |
| 1668 | #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) |
| 1669 | #define SLCD_CFG_RS_CMD_LOW (0 << 3) |
| 1670 | #define SLCD_CFG_RS_CMD_HIGH (1 << 3) |
| 1671 | #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) |
| 1672 | #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) |
| 1673 | #define SLCD_CFG_TYPE_PARALLEL (0 << 0) |
| 1674 | #define SLCD_CFG_TYPE_SERIAL (1 << 0) |
| 1675 | |
| 1676 | // SLCD Control Register |
| 1677 | #define SLCD_CTRL_DMA_EN (1 << 0) |
| 1678 | |
| 1679 | // SLCD Status Register |
| 1680 | #define SLCD_STATE_BUSY (1 << 0) |
| 1681 | |
| 1682 | // SLCD Data Register |
| 1683 | #define SLCD_DATA_RS_DATA (0 << 31) |
| 1684 | #define SLCD_DATA_RS_COMMAND (1 << 31) |
| 1685 | |
| 1686 | // SLCD FIFO Register |
| 1687 | #define SLCD_FIFO_RS_DATA (0 << 31) |
| 1688 | #define SLCD_FIFO_RS_COMMAND (1 << 31) |
| 1689 | |
| 1690 | |
| 1691 | //************************************************************************ |
| 1692 | // LCD (LCD Controller) |
| 1693 | //************************************************************************ |
| 1694 | #define LCD_CFG REG32 (LCD_BASE + 0x00) // LCD Configure Register |
| 1695 | #define LCD_VSYNC REG32 (LCD_BASE + 0x04) // Vertical Synchronize Register |
| 1696 | #define LCD_HSYNC REG32 (LCD_BASE + 0x08) // Horizontal Synchronize Register |
| 1697 | #define LCD_VAT REG32 (LCD_BASE + 0x0c) // Virtual Area Setting Register |
| 1698 | #define LCD_DAH REG32 (LCD_BASE + 0x10) // Display Area Horizontal Start/End Point |
| 1699 | #define LCD_DAV REG32 (LCD_BASE + 0x14) // Display Area Vertical Start/End Point |
| 1700 | #define LCD_PS REG32 (LCD_BASE + 0x18) // PS Signal Setting |
| 1701 | #define LCD_CLS REG32 (LCD_BASE + 0x1c) // CLS Signal Setting |
| 1702 | #define LCD_SPL REG32 (LCD_BASE + 0x20) // SPL Signal Setting |
| 1703 | #define LCD_REV REG32 (LCD_BASE + 0x24) // REV Signal Setting |
| 1704 | #define LCD_CTRL REG32 (LCD_BASE + 0x30) // LCD Control Register |
| 1705 | #define LCD_STATE REG32 (LCD_BASE + 0x34) // LCD Status Register |
| 1706 | #define LCD_IID REG32 (LCD_BASE + 0x38) // Interrupt ID Register |
| 1707 | #define LCD_DA0 REG32 (LCD_BASE + 0x40) // Descriptor Address Register 0 |
| 1708 | #define LCD_SA0 REG32 (LCD_BASE + 0x44) // Source Address Register 0 |
| 1709 | #define LCD_FID0 REG32 (LCD_BASE + 0x48) // Frame ID Register 0 |
| 1710 | #define LCD_CMD0 REG32 (LCD_BASE + 0x4c) // DMA Command Register 0 |
| 1711 | #define LCD_DA1 REG32 (LCD_BASE + 0x50) // Descriptor Address Register 1 |
| 1712 | #define LCD_SA1 REG32 (LCD_BASE + 0x54) // Source Address Register 1 |
| 1713 | #define LCD_FID1 REG32 (LCD_BASE + 0x58) // Frame ID Register 1 |
| 1714 | #define LCD_CMD1 REG32 (LCD_BASE + 0x5c) // DMA Command Register 1 |
| 1715 | |
| 1716 | // LCD Configure Register |
| 1717 | #define LCD_CFG_LCDPIN_BIT 31 // LCD pins selection |
| 1718 | #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) |
| 1719 | #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) |
| 1720 | #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) |
| 1721 | #define LCD_CFG_PSM (1 << 23) // PS signal mode |
| 1722 | #define LCD_CFG_CLSM (1 << 22) // CLS signal mode |
| 1723 | #define LCD_CFG_SPLM (1 << 21) // SPL signal mode |
| 1724 | #define LCD_CFG_REVM (1 << 20) // REV signal mode |
| 1725 | #define LCD_CFG_HSYNM (1 << 19) // HSYNC signal mode |
| 1726 | #define LCD_CFG_PCLKM (1 << 18) // PCLK signal mode |
| 1727 | #define LCD_CFG_INVDAT (1 << 17) // Inverse output data |
| 1728 | #define LCD_CFG_SYNDIR_IN (1 << 16) // VSYNC&HSYNC direction |
| 1729 | #define LCD_CFG_PSP (1 << 15) // PS pin reset state |
| 1730 | #define LCD_CFG_CLSP (1 << 14) // CLS pin reset state |
| 1731 | #define LCD_CFG_SPLP (1 << 13) // SPL pin reset state |
| 1732 | #define LCD_CFG_REVP (1 << 12) // REV pin reset state |
| 1733 | #define LCD_CFG_HSP (1 << 11) // HSYNC pority:0-active high,1-active low |
| 1734 | #define LCD_CFG_PCP (1 << 10) // PCLK pority:0-rising,1-falling |
| 1735 | #define LCD_CFG_DEP (1 << 9) // DE pority:0-active high,1-active low |
| 1736 | #define LCD_CFG_VSP (1 << 8) // VSYNC pority:0-rising,1-falling |
| 1737 | #define LCD_CFG_PDW_BIT 4 // STN pins utilization |
| 1738 | #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) |
| 1739 | #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) // LCD_D[0] |
| 1740 | #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) // LCD_D[0:1] |
| 1741 | #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) // LCD_D[0:3]/LCD_D[8:11] |
| 1742 | #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) // LCD_D[0:7]/LCD_D[8:15] |
| 1743 | #define LCD_CFG_MODE_BIT 0 // Display Device Mode Select |
| 1744 | #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) |
| 1745 | #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) // 16,18 bit TFT |
| 1746 | #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) |
| 1747 | #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) |
| 1748 | #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) |
| 1749 | #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) |
| 1750 | #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) |
| 1751 | #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) |
| 1752 | #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) |
| 1753 | #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) |
| 1754 | #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) |
| 1755 | #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) |
| 1756 | #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) |
| 1757 | // JZ47XX defines |
| 1758 | #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) |
| 1759 | #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) |
| 1760 | #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) |
| 1761 | |
| 1762 | |
| 1763 | |
| 1764 | // Vertical Synchronize Register |
| 1765 | #define LCD_VSYNC_VPS_BIT 16 // VSYNC pulse start in line clock, fixed to 0 |
| 1766 | #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
| 1767 | #define LCD_VSYNC_VPE_BIT 0 // VSYNC pulse end in line clock |
| 1768 | #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
| 1769 | |
| 1770 | // Horizontal Synchronize Register |
| 1771 | #define LCD_HSYNC_HPS_BIT 16 // HSYNC pulse start position in dot clock |
| 1772 | #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) |
| 1773 | #define LCD_HSYNC_HPE_BIT 0 // HSYNC pulse end position in dot clock |
| 1774 | #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) |
| 1775 | |
| 1776 | // Virtual Area Setting Register |
| 1777 | #define LCD_VAT_HT_BIT 16 // Horizontal Total size in dot clock |
| 1778 | #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) |
| 1779 | #define LCD_VAT_VT_BIT 0 // Vertical Total size in dot clock |
| 1780 | #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) |
| 1781 | |
| 1782 | // Display Area Horizontal Start/End Point Register |
| 1783 | #define LCD_DAH_HDS_BIT 16 // Horizontal display area start in dot clock |
| 1784 | #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) |
| 1785 | #define LCD_DAH_HDE_BIT 0 // Horizontal display area end in dot clock |
| 1786 | #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) |
| 1787 | |
| 1788 | // Display Area Vertical Start/End Point Register |
| 1789 | #define LCD_DAV_VDS_BIT 16 // Vertical display area start in line clock |
| 1790 | #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) |
| 1791 | #define LCD_DAV_VDE_BIT 0 // Vertical display area end in line clock |
| 1792 | #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) |
| 1793 | |
| 1794 | // PS Signal Setting |
| 1795 | #define LCD_PS_PSS_BIT 16 // PS signal start position in dot clock |
| 1796 | #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) |
| 1797 | #define LCD_PS_PSE_BIT 0 // PS signal end position in dot clock |
| 1798 | #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) |
| 1799 | |
| 1800 | // CLS Signal Setting |
| 1801 | #define LCD_CLS_CLSS_BIT 16 // CLS signal start position in dot clock |
| 1802 | #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) |
| 1803 | #define LCD_CLS_CLSE_BIT 0 // CLS signal end position in dot clock |
| 1804 | #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) |
| 1805 | |
| 1806 | // SPL Signal Setting |
| 1807 | #define LCD_SPL_SPLS_BIT 16 // SPL signal start position in dot clock |
| 1808 | #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) |
| 1809 | #define LCD_SPL_SPLE_BIT 0 // SPL signal end position in dot clock |
| 1810 | #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) |
| 1811 | |
| 1812 | // REV Signal Setting |
| 1813 | #define LCD_REV_REVS_BIT 16 // REV signal start position in dot clock |
| 1814 | #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) |
| 1815 | |
| 1816 | // LCD Control Register |
| 1817 | #define LCD_CTRL_BST_BIT 28 // Burst Length Selection |
| 1818 | #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) |
| 1819 | #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) // 4-word |
| 1820 | #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) // 8-word |
| 1821 | #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) // 16-word |
| 1822 | #define LCD_CTRL_RGB565 (0 << 27) // RGB565 mode |
| 1823 | #define LCD_CTRL_RGB555 (1 << 27) // RGB555 mode |
| 1824 | #define LCD_CTRL_OFUP (1 << 26) // Output FIFO underrun protection enable |
| 1825 | #define LCD_CTRL_FRC_BIT 24 // STN FRC Algorithm Selection |
| 1826 | #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) |
| 1827 | #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) // 16 grayscale |
| 1828 | #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) // 4 grayscale |
| 1829 | #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) // 2 grayscale |
| 1830 | #define LCD_CTRL_PDD_BIT 16 // Load Palette Delay Counter |
| 1831 | #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) |
| 1832 | #define LCD_CTRL_EOFM (1 << 13) // EOF interrupt mask |
| 1833 | #define LCD_CTRL_SOFM (1 << 12) // SOF interrupt mask |
| 1834 | #define LCD_CTRL_OFUM (1 << 11) // Output FIFO underrun interrupt mask |
| 1835 | #define LCD_CTRL_IFUM0 (1 << 10) // Input FIFO 0 underrun interrupt mask |
| 1836 | #define LCD_CTRL_IFUM1 (1 << 9) // Input FIFO 1 underrun interrupt mask |
| 1837 | #define LCD_CTRL_LDDM (1 << 8) // LCD disable done interrupt mask |
| 1838 | #define LCD_CTRL_QDM (1 << 7) // LCD quick disable done interrupt mask |
| 1839 | #define LCD_CTRL_BEDN (1 << 6) // Endian selection |
| 1840 | #define LCD_CTRL_PEDN (1 << 5) // Endian in byte:0-msb first, 1-lsb first |
| 1841 | #define LCD_CTRL_DIS (1 << 4) // Disable indicate bit |
| 1842 | #define LCD_CTRL_ENA (1 << 3) // LCD enable bit |
| 1843 | #define LCD_CTRL_BPP_BIT 0 // Bits Per Pixel |
| 1844 | #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) |
| 1845 | #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) // 1 bpp |
| 1846 | #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) // 2 bpp |
| 1847 | #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) // 4 bpp |
| 1848 | #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) // 8 bpp |
| 1849 | #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) // 15/16 bpp |
| 1850 | #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) // 18/24/32 bpp |
| 1851 | |
| 1852 | // LCD Status Register |
| 1853 | #define LCD_STATE_QD (1 << 7) // Quick Disable Done |
| 1854 | #define LCD_STATE_EOF (1 << 5) // EOF Flag |
| 1855 | #define LCD_STATE_SOF (1 << 4) // SOF Flag |
| 1856 | #define LCD_STATE_OFU (1 << 3) // Output FIFO Underrun |
| 1857 | #define LCD_STATE_IFU0 (1 << 2) // Input FIFO 0 Underrun |
| 1858 | #define LCD_STATE_IFU1 (1 << 1) // Input FIFO 1 Underrun |
| 1859 | #define LCD_STATE_LDD (1 << 0) // LCD Disabled |
| 1860 | |
| 1861 | // DMA Command Register |
| 1862 | #define LCD_CMD_SOFINT (1 << 31) |
| 1863 | #define LCD_CMD_EOFINT (1 << 30) |
| 1864 | #define LCD_CMD_PAL (1 << 28) |
| 1865 | #define LCD_CMD_LEN_BIT 0 |
| 1866 | #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) |
| 1867 | |
| 1868 | |
| 1869 | //************************************************************************ |
| 1870 | // USB Device |
| 1871 | //************************************************************************ |
| 1872 | #define UDC_FADDR REG8 (UDC_BASE + 0x00) // Function Address 8-bit |
| 1873 | #define UDC_POWER REG8 (UDC_BASE + 0x01) // Power Managemetn 8-bit |
| 1874 | #define UDC_INTRIN REG16 (UDC_BASE + 0x02) // Interrupt IN 16-bit |
| 1875 | #define UDC_INTROUT REG16 (UDC_BASE + 0x04) // Interrupt OUT 16-bit |
| 1876 | #define UDC_INTRINE REG16 (UDC_BASE + 0x06) // Intr IN enable 16-bit |
| 1877 | #define UDC_INTROUTE REG16 (UDC_BASE + 0x08) // Intr OUT enable 16-bit |
| 1878 | #define UDC_INTRUSB REG8 (UDC_BASE + 0x0a) // Interrupt USB 8-bit |
| 1879 | #define UDC_INTRUSBE REG8 (UDC_BASE + 0x0b) // Interrupt USB Enable 8-bit |
| 1880 | #define UDC_FRAME REG16 (UDC_BASE + 0x0c) // Frame number 16-bit |
| 1881 | #define UDC_INDEX REG8 (UDC_BASE + 0x0e) // Index register 8-bit |
| 1882 | #define UDC_TESTMODE REG8 (UDC_BASE + 0x0f) // USB test mode 8-bit |
| 1883 | |
| 1884 | #define UDC_CSR0 REG8 (UDC_BASE + 0x12) // EP0 CSR 8-bit |
| 1885 | #define UDC_INMAXP REG16 (UDC_BASE + 0x10) // EP1-2 IN Max Pkt Size 16-bit |
| 1886 | #define UDC_INCSR REG16 (UDC_BASE + 0x12) // EP1-2 IN CSR LSB 8/16bit |
| 1887 | #define UDC_INCSRH REG8 (UDC_BASE + 0x13) // EP1-2 IN CSR MSB 8-bit |
| 1888 | #define UDC_OUTMAXP REG16 (UDC_BASE + 0x14) // EP1 OUT Max Pkt Size 16-bit |
| 1889 | #define UDC_OUTCSR REG16 (UDC_BASE + 0x16) // EP1 OUT CSR LSB 8/16bit |
| 1890 | #define UDC_OUTCSRH REG8 (UDC_BASE + 0x17) // EP1 OUT CSR MSB 8-bit |
| 1891 | #define UDC_OUTCOUNT REG16 (UDC_BASE + 0x18) // bytes in EP0/1 OUT FIFO 16-bit |
| 1892 | |
| 1893 | #define UDC_FIFO(ep) REG32 (UDC_BASE + 0x20 + 4 * (ep)) |
| 1894 | #define UDC_FIFO8(ep) REG8 (UDC_BASE + 0x20 + 4 * (ep)) |
| 1895 | |
| 1896 | #define UDC_EPINFO REG32 (UDC_BASE + 0x78) // Endpoint information |
| 1897 | #define UDC_RAMINFO REG32 (UDC_BASE + 0x79) // RAM information |
| 1898 | |
| 1899 | #define UDC_INTR REG32 (UDC_BASE + 0x200) // DMA pending interrupts |
| 1900 | #define UDC_CNTL1 REG32 (UDC_BASE + 0x204) // DMA channel 1 control |
| 1901 | #define UDC_ADDR1 REG32 (UDC_BASE + 0x208) // DMA channel 1 AHB memory addr |
| 1902 | #define UDC_COUNT1 REG32 (UDC_BASE + 0x20c) // DMA channel 1 byte count |
| 1903 | #define UDC_CNTL2 REG32 (UDC_BASE + 0x214) // DMA channel 2 control |
| 1904 | #define UDC_ADDR2 REG32 (UDC_BASE + 0x218) // DMA channel 2 AHB memory addr |
| 1905 | #define UDC_COUNT2 REG32 (UDC_BASE + 0x21c) // DMA channel 2 byte count |
| 1906 | |
| 1907 | |
| 1908 | // Power register bit masks |
| 1909 | #define UDC_POWER_SUSPENDM 0x01 |
| 1910 | #define UDC_POWER_RESUME 0x04 |
| 1911 | #define UDC_POWER_HSMODE 0x10 |
| 1912 | #define UDC_POWER_HSENAB 0x20 |
| 1913 | #define UDC_POWER_SOFTCONN 0x40 |
| 1914 | |
| 1915 | // Interrupt register bit masks |
| 1916 | #define UDC_INTR_SUSPEND 0x01 |
| 1917 | #define UDC_INTR_RESUME 0x02 |
| 1918 | #define UDC_INTR_RESET 0x04 |
| 1919 | |
| 1920 | #define UDC_INTR_EP0 0x0001 |
| 1921 | #define UDC_INTR_INEP1 0x0002 |
| 1922 | #define UDC_INTR_INEP2 0x0004 |
| 1923 | #define UDC_INTR_OUTEP1 0x0002 |
| 1924 | |
| 1925 | // CSR0 bit masks |
| 1926 | #define UDC_CSR0_OUTPKTRDY 0x01 |
| 1927 | #define UDC_CSR0_INPKTRDY 0x02 |
| 1928 | #define UDC_CSR0_SENTSTALL 0x04 |
| 1929 | #define UDC_CSR0_DATAEND 0x08 |
| 1930 | #define UDC_CSR0_SETUPEND 0x10 |
| 1931 | #define UDC_CSR0_SENDSTALL 0x20 |
| 1932 | #define UDC_CSR0_SVDOUTPKTRDY 0x40 |
| 1933 | #define UDC_CSR0_SVDSETUPEND 0x80 |
| 1934 | |
| 1935 | // Endpoint CSR register bits |
| 1936 | #define UDC_INCSRH_AUTOSET 0x80 |
| 1937 | #define UDC_INCSRH_ISO 0x40 |
| 1938 | #define UDC_INCSRH_MODE 0x20 |
| 1939 | #define UDC_INCSRH_DMAREQENAB 0x10 |
| 1940 | #define UDC_INCSRH_DMAREQMODE 0x04 |
| 1941 | #define UDC_INCSR_CDT 0x40 |
| 1942 | #define UDC_INCSR_SENTSTALL 0x20 |
| 1943 | #define UDC_INCSR_SENDSTALL 0x10 |
| 1944 | #define UDC_INCSR_FF 0x08 |
| 1945 | #define UDC_INCSR_UNDERRUN 0x04 |
| 1946 | #define UDC_INCSR_FFNOTEMPT 0x02 |
| 1947 | #define UDC_INCSR_INPKTRDY 0x01 |
| 1948 | #define UDC_OUTCSRH_AUTOCLR 0x80 |
| 1949 | #define UDC_OUTCSRH_ISO 0x40 |
| 1950 | #define UDC_OUTCSRH_DMAREQENAB 0x20 |
| 1951 | #define UDC_OUTCSRH_DNYT 0x10 |
| 1952 | #define UDC_OUTCSRH_DMAREQMODE 0x08 |
| 1953 | #define UDC_OUTCSR_CDT 0x80 |
| 1954 | #define UDC_OUTCSR_SENTSTALL 0x40 |
| 1955 | #define UDC_OUTCSR_SENDSTALL 0x20 |
| 1956 | #define UDC_OUTCSR_FF 0x10 |
| 1957 | #define UDC_OUTCSR_DATAERR 0x08 |
| 1958 | #define UDC_OUTCSR_OVERRUN 0x04 |
| 1959 | #define UDC_OUTCSR_FFFULL 0x02 |
| 1960 | #define UDC_OUTCSR_OUTPKTRDY 0x01 |
| 1961 | |
| 1962 | // Testmode register bits |
| 1963 | #define UDC_TEST_SE0NAK 0x01 |
| 1964 | #define UDC_TEST_J 0x02 |
| 1965 | #define UDC_TEST_K 0x04 |
| 1966 | #define UDC_TEST_PACKET 0x08 |
| 1967 | |
| 1968 | // DMA control bits |
| 1969 | #define UDC_CNTL_ENA 0x01 |
| 1970 | #define UDC_CNTL_DIR_IN 0x02 |
| 1971 | #define UDC_CNTL_MODE_1 0x04 |
| 1972 | #define UDC_CNTL_INTR_EN 0x08 |
| 1973 | #define UDC_CNTL_EP(n) ((n) << 4) |
| 1974 | #define UDC_CNTL_BURST_0 (0 << 9) |
| 1975 | #define UDC_CNTL_BURST_4 (1 << 9) |
| 1976 | #define UDC_CNTL_BURST_8 (2 << 9) |
| 1977 | #define UDC_CNTL_BURST_16 (3 << 9) |
| 1978 | |
| 1979 | //########################################################################## |
| 1980 | //************************************************************************** |
| 1981 | // GPIO |
| 1982 | //************************************************************************** |
| 1983 | |
| 1984 | //------------------------------------------------------ |
| 1985 | // GPIO Pins Description |
| 1986 | // |
| 1987 | // PORT 0 |
| 1988 | // |
| 1989 | // PIN/BIT N FUNC0 FUNC1 |
| 1990 | // 0 D0 - |
| 1991 | // 1 D1 - |
| 1992 | // 2 D2 - |
| 1993 | // 3 D3 - |
| 1994 | // 4 D4 - |
| 1995 | // 5 D5 - |
| 1996 | // 6 D6 - |
| 1997 | // 7 D7 - |
| 1998 | // 8 D8 - |
| 1999 | // 9 D9 - |
| 2000 | // 10 D10 - |
| 2001 | // 11 D11 - |
| 2002 | // 12 D12 - |
| 2003 | // 13 D13 - |
| 2004 | // 14 D14 - |
| 2005 | // 15 D15 - |
| 2006 | // 16 D16 - |
| 2007 | // 17 D17 - |
| 2008 | // 18 D18 - |
| 2009 | // 19 D19 - |
| 2010 | // 20 D20 - |
| 2011 | // 21 D21 - |
| 2012 | // 22 D22 - |
| 2013 | // 23 D23 - |
| 2014 | // 24 D24 - |
| 2015 | // 25 D25 - |
| 2016 | // 26 D26 - |
| 2017 | // 27 D27 - |
| 2018 | // 28 D28 - |
| 2019 | // 29 D29 - |
| 2020 | // 30 D30 - |
| 2021 | // 31 D31 - |
| 2022 | // |
| 2023 | //------------------------------------------------------ |
| 2024 | // PORT 1 |
| 2025 | // |
| 2026 | // PIN/BIT N FUNC0 FUNC1 |
| 2027 | // 0 A0 - |
| 2028 | // 1 A1 - |
| 2029 | // 2 A2 - |
| 2030 | // 3 A3 - |
| 2031 | // 4 A4 - |
| 2032 | // 5 A5 - |
| 2033 | // 6 A6 - |
| 2034 | // 7 A7 - |
| 2035 | // 8 A8 - |
| 2036 | // 9 A9 - |
| 2037 | // 10 A10 - |
| 2038 | // 11 A11 - |
| 2039 | // 12 A12 - |
| 2040 | // 13 A13 - |
| 2041 | // 14 A14 - |
| 2042 | // 15 A15/CL - |
| 2043 | // 16 A16/AL - |
| 2044 | // 17 LCD_CLS A21 |
| 2045 | // 18 LCD_SPL A22 |
| 2046 | // 19 DCS# - |
| 2047 | // 20 RAS# - |
| 2048 | // 21 CAS# - |
| 2049 | // 22 RDWE#/BUFD# - |
| 2050 | // 23 CKE - |
| 2051 | // 24 CKO - |
| 2052 | // 25 CS1# - |
| 2053 | // 26 CS2# - |
| 2054 | // 27 CS3# - |
| 2055 | // 28 CS4# - |
| 2056 | // 29 RD# - |
| 2057 | // 30 WR# - |
| 2058 | // 31 WE0# - |
| 2059 | // |
| 2060 | // Note: PIN15&16 are CL&AL when connecting to NAND flash. |
| 2061 | //------------------------------------------------------ |
| 2062 | // PORT 2 |
| 2063 | // |
| 2064 | // PIN/BIT N FUNC0 FUNC1 |
| 2065 | // 0 LCD_D0 - |
| 2066 | // 1 LCD_D1 - |
| 2067 | // 2 LCD_D2 - |
| 2068 | // 3 LCD_D3 - |
| 2069 | // 4 LCD_D4 - |
| 2070 | // 5 LCD_D5 - |
| 2071 | // 6 LCD_D6 - |
| 2072 | // 7 LCD_D7 - |
| 2073 | // 8 LCD_D8 - |
| 2074 | // 9 LCD_D9 - |
| 2075 | // 10 LCD_D10 - |
| 2076 | // 11 LCD_D11 - |
| 2077 | // 12 LCD_D12 - |
| 2078 | // 13 LCD_D13 - |
| 2079 | // 14 LCD_D14 - |
| 2080 | // 15 LCD_D15 - |
| 2081 | // 16 LCD_D16 - |
| 2082 | // 17 LCD_D17 - |
| 2083 | // 18 LCD_PCLK - |
| 2084 | // 19 LCD_HSYNC - |
| 2085 | // 20 LCD_VSYNC - |
| 2086 | // 21 LCD_DE - |
| 2087 | // 22 LCD_PS A19 |
| 2088 | // 23 LCD_REV A20 |
| 2089 | // 24 WE1# - |
| 2090 | // 25 WE2# - |
| 2091 | // 26 WE3# - |
| 2092 | // 27 WAIT# - |
| 2093 | // 28 FRE# - |
| 2094 | // 29 FWE# - |
| 2095 | // 30(NOTE:FRB#) - - |
| 2096 | // 31 - - |
| 2097 | // |
| 2098 | // NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. |
| 2099 | //------------------------------------------------------ |
| 2100 | // PORT 3 |
| 2101 | // |
| 2102 | // PIN/BIT N FUNC0 FUNC1 |
| 2103 | // 0 CIM_D0 - |
| 2104 | // 1 CIM_D1 - |
| 2105 | // 2 CIM_D2 - |
| 2106 | // 3 CIM_D3 - |
| 2107 | // 4 CIM_D4 - |
| 2108 | // 5 CIM_D5 - |
| 2109 | // 6 CIM_D6 - |
| 2110 | // 7 CIM_D7 - |
| 2111 | // 8 MSC_CMD - |
| 2112 | // 9 MSC_CLK - |
| 2113 | // 10 MSC_D0 - |
| 2114 | // 11 MSC_D1 - |
| 2115 | // 12 MSC_D2 - |
| 2116 | // 13 MSC_D3 - |
| 2117 | // 14 CIM_MCLK - |
| 2118 | // 15 CIM_PCLK - |
| 2119 | // 16 CIM_VSYNC - |
| 2120 | // 17 CIM_HSYNC - |
| 2121 | // 18 SSI_CLK SCLK_RSTN |
| 2122 | // 19 SSI_CE0# BIT_CLK(AIC) |
| 2123 | // 20 SSI_DT SDATA_OUT(AIC) |
| 2124 | // 21 SSI_DR SDATA_IN(AIC) |
| 2125 | // 22 SSI_CE1#&GPC SYNC(AIC) |
| 2126 | // 23 PWM0 I2C_SDA |
| 2127 | // 24 PWM1 I2C_SCK |
| 2128 | // 25 PWM2 UART0_TxD |
| 2129 | // 26 PWM3 UART0_RxD |
| 2130 | // 27 PWM4 A17 |
| 2131 | // 28 PWM5 A18 |
| 2132 | // 29 - - |
| 2133 | // 30 PWM6 UART0_CTS/UART1_RxD |
| 2134 | // 31 PWM7 UART0_RTS/UART1_TxD |
| 2135 | // |
| 2136 | ////////////////////////////////////////////////////////// |
| 2137 | |
| 2138 | // p is the port number (0,1,2,3) |
| 2139 | // o is the pin offset (0-31) inside the port |
| 2140 | |
| 2141 | //------------------------------------------- |
| 2142 | // Function Pins Mode |
| 2143 | |
| 2144 | static void gpio_as_func0 (unsigned p, unsigned o): |
| 2145 | GPIO_PXFUNS (p) = (1 << o) |
| 2146 | GPIO_PXSELC (p) = (1 << o) |
| 2147 | |
| 2148 | static void gpio_as_func1 (unsigned p, unsigned o): |
| 2149 | GPIO_PXFUNS (p) = (1 << o) |
| 2150 | GPIO_PXSELS (p) = (1 << o) |
| 2151 | |
| 2152 | // D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# |
| 2153 | static void gpio_as_sdram_32bit (): |
| 2154 | GPIO_PXFUNS (0) = 0xffffffff |
| 2155 | GPIO_PXSELC (0) = 0xffffffff |
| 2156 | GPIO_PXPES (0) = 0xffffffff |
| 2157 | GPIO_PXFUNS (1) = 0x81f9ffff |
| 2158 | GPIO_PXSELC (1) = 0x81f9ffff |
| 2159 | GPIO_PXPES (1) = 0x81f9ffff |
| 2160 | GPIO_PXFUNS (2) = 0x07000000 |
| 2161 | GPIO_PXSELC (2) = 0x07000000 |
| 2162 | GPIO_PXPES (2) = 0x07000000 |
| 2163 | |
| 2164 | // D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, RDWE#, CKO#, WE0#, WE1# |
| 2165 | static void gpio_as_sdram_16bit(): |
| 2166 | GPIO_PXFUNS (0) = 0x5442bfaa |
| 2167 | GPIO_PXSELC (0) = 0x5442bfaa |
| 2168 | GPIO_PXPES (0) = 0x5442bfaa |
| 2169 | GPIO_PXFUNS (1) = 0x81f9ffff |
| 2170 | GPIO_PXSELC (1) = 0x81f9ffff |
| 2171 | GPIO_PXPES (1) = 0x81f9ffff |
| 2172 | GPIO_PXFUNS (2) = 0x01000000 |
| 2173 | GPIO_PXSELC (2) = 0x01000000 |
| 2174 | GPIO_PXPES (2) = 0x01000000 |
| 2175 | |
| 2176 | // CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# |
| 2177 | static void gpio_as_nand (): |
| 2178 | GPIO_PXFUNS (1) = 0x02018000 |
| 2179 | GPIO_PXSELC (1) = 0x02018000 |
| 2180 | GPIO_PXPES (1) = 0x02018000 |
| 2181 | GPIO_PXFUNS (2) = 0x30000000 |
| 2182 | GPIO_PXSELC (2) = 0x30000000 |
| 2183 | GPIO_PXPES (2) = 0x30000000 |
| 2184 | GPIO_PXFUNC (2) = 0x40000000 |
| 2185 | GPIO_PXSELC (2) = 0x40000000 |
| 2186 | GPIO_PXDIRC (2) = 0x40000000 |
| 2187 | GPIO_PXPES (2) = 0x40000000 |
| 2188 | GPIO_PXFUNS (1) = 0x00400000 |
| 2189 | GPIO_PXSELC (1) = 0x00400000 |
| 2190 | |
| 2191 | // UART0_TxD, UART0_RxD |
| 2192 | static void gpio_as_uart0 (bool send_only = false): |
| 2193 | GPIO_PXFUNS (3) = send_only ? 0x02000000 : 0x06000000 |
| 2194 | GPIO_PXSELS (3) = send_only ? 0x02000000 : 0x06000000 |
| 2195 | GPIO_PXPES (3) = send_only ? 0x02000000 : 0x06000000 |
| 2196 | |
| 2197 | // UART0_CTS, UART0_RTS |
| 2198 | static void gpio_as_ctsrts (): |
| 2199 | GPIO_PXFUNS (3) = 0xc0000000 |
| 2200 | GPIO_PXSELS (3) = 0xc0000000 |
| 2201 | GPIO_PXTRGC (3) = 0xc0000000 |
| 2202 | GPIO_PXPES (3) = 0xc0000000 |
| 2203 | |
| 2204 | // JTAG on pad 147+148 (Jz4720) |
| 2205 | static void enable_jtag_debug (): |
| 2206 | GPIO_PXSELC (3) = 0x80000000 |
| 2207 | |
| 2208 | // UART0 on pad 147+148 (Jz4720) |
| 2209 | static void enable_uart0_debug (): |
| 2210 | GPIO_PXSELS (3) = 0x80000000 |
| 2211 | |
| 2212 | // UART1_TxD, UART1_RxD1 |
| 2213 | static void gpio_as_uart1(): |
| 2214 | GPIO_PXFUNS (3) = 0xc0000000 |
| 2215 | GPIO_PXSELC (3) = 0xc0000000 |
| 2216 | GPIO_PXTRGS (3) = 0xc0000000 |
| 2217 | GPIO_PXPES (3) = 0xc0000000 |
| 2218 | |
| 2219 | // LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE |
| 2220 | static void gpio_as_lcd_16bit (): |
| 2221 | GPIO_PXFUNS (2) = 0x003cffff |
| 2222 | GPIO_PXSELC (2) = 0x003cffff |
| 2223 | GPIO_PXPES (2) = 0x003cffff |
| 2224 | |
| 2225 | // LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE |
| 2226 | static void gpio_as_lcd_18bit (): |
| 2227 | GPIO_PXFUNS (2) = 0x003fffff |
| 2228 | GPIO_PXSELC (2) = 0x003fffff |
| 2229 | GPIO_PXPES (2) = 0x003fffff |
| 2230 | |
| 2231 | // LCD_PS, LCD_REV, LCD_CLS, LCD_SPL |
| 2232 | static void gpio_as_lcd_spl (): |
| 2233 | GPIO_PXFUNS (1) = 0x00060000 |
| 2234 | GPIO_PXSELC (1) = 0x00060000 |
| 2235 | GPIO_PXPES (1) = 0x00060000 |
| 2236 | GPIO_PXFUNS (2) = 0x00c00000 |
| 2237 | GPIO_PXSELC (2) = 0x00c00000 |
| 2238 | GPIO_PXPES (2) = 0x00c00000 |
| 2239 | |
| 2240 | // CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC |
| 2241 | static void gpio_as_cim (): |
| 2242 | GPIO_PXFUNS (3) = 0x0003c0ff |
| 2243 | GPIO_PXSELC (3) = 0x0003c0ff |
| 2244 | GPIO_PXPES (3) = 0x0003c0ff |
| 2245 | |
| 2246 | // SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET |
| 2247 | static void gpio_as_aic (): |
| 2248 | GPIO_PXFUNS(3) = 0x007c0000 |
| 2249 | GPIO_PXSELS(3) = 0x007c0000 |
| 2250 | GPIO_PXPES(3) = 0x007c0000 |
| 2251 | |
| 2252 | // MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 |
| 2253 | static void gpio_as_msc (): |
| 2254 | GPIO_PXFUNS (3) = 0x00003f00 |
| 2255 | GPIO_PXSELC (3) = 0x00003f00 |
| 2256 | GPIO_PXPES (3) = 0x00003f00 |
| 2257 | |
| 2258 | // SSI_CS0, SSI_CLK, SSI_DT, SSI_DR |
| 2259 | static void gpio_as_ssi (): |
| 2260 | GPIO_PXFUNS (3) = 0x003c0000 |
| 2261 | GPIO_PXSELC (3) = 0x003c0000 |
| 2262 | GPIO_PXPES (3) = 0x003c0000 |
| 2263 | |
| 2264 | // I2C_SCK, I2C_SDA |
| 2265 | static void gpio_as_i2c (): |
| 2266 | GPIO_PXFUNS (3) = 0x01800000 |
| 2267 | GPIO_PXSELS (3) = 0x01800000 |
| 2268 | GPIO_PXPES (3) = 0x01800000 |
| 2269 | |
| 2270 | // PWM* |
| 2271 | static void gpio_as_pwm0 (): |
| 2272 | GPIO_PXFUNS (3) = 0x00800000 |
| 2273 | GPIO_PXSELC (3) = 0x00800000 |
| 2274 | GPIO_PXPES (3) = 0x00800000 |
| 2275 | static void gpio_as_pwm1 (): |
| 2276 | GPIO_PXFUNS (3) = 0x01000000 |
| 2277 | GPIO_PXSELC (3) = 0x01000000 |
| 2278 | GPIO_PXPES (3) = 0x01000000 |
| 2279 | static void gpio_as_pwm2 (): |
| 2280 | GPIO_PXFUNS (3) = 0x02000000 |
| 2281 | GPIO_PXSELC (3) = 0x02000000 |
| 2282 | GPIO_PXPES (3) = 0x02000000 |
| 2283 | static void gpio_as_pwm3 (): |
| 2284 | GPIO_PXFUNS (3) = 0x04000000 |
| 2285 | GPIO_PXSELC (3) = 0x04000000 |
| 2286 | GPIO_PXPES (3) = 0x04000000 |
| 2287 | static void gpio_as_pwm4 (): |
| 2288 | GPIO_PXFUNS (3) = 0x08000000 |
| 2289 | GPIO_PXSELC (3) = 0x08000000 |
| 2290 | GPIO_PXPES (3) = 0x08000000 |
| 2291 | static void gpio_as_pwm5 (): |
| 2292 | GPIO_PXFUNS (3) = 0x10000000 |
| 2293 | GPIO_PXSELC (3) = 0x10000000 |
| 2294 | GPIO_PXPES (3) = 0x10000000 |
| 2295 | static void gpio_as_pwm6 (): |
| 2296 | GPIO_PXFUNS (3) = 0x40000000 |
| 2297 | GPIO_PXSELC (3) = 0x40000000 |
| 2298 | GPIO_PXPES (3) = 0x40000000 |
| 2299 | static void gpio_as_pwm7 (): |
| 2300 | GPIO_PXFUNS (3) = 0x80000000 |
| 2301 | GPIO_PXSELC (3) = 0x80000000 |
| 2302 | GPIO_PXPES (3) = 0x80000000 |
| 2303 | |
| 2304 | // n = 0 ~ 7 |
| 2305 | #define gpio_as_pwm(n) (gpio_as_pwm##n ()) |
| 2306 | |
| 2307 | //------------------------------------------- |
| 2308 | // GPIO or Interrupt Mode |
| 2309 | |
| 2310 | static unsigned gpio_get_port (unsigned p): |
| 2311 | return GPIO_PXPIN (p) |
| 2312 | static unsigned gpio_get_irqs (unsigned p): |
| 2313 | return GPIO_PXFLG (p) |
| 2314 | |
| 2315 | static void gpio_as_gpio (unsigned p, unsigned pins): |
| 2316 | GPIO_PXFUNC (p) = pins |
| 2317 | static void gpio_as_output (unsigned p, unsigned pins): |
| 2318 | GPIO_PXDIRS (p) = pins |
| 2319 | static void gpio_as_input (unsigned p, unsigned pins): |
| 2320 | GPIO_PXDIRC (p) = pins |
| 2321 | // Set gpio as interrupt. It must already be set as gpio. It must be unmasked before it will trigger. |
| 2322 | static void gpio_as_interrupt (unsigned p, unsigned pins, bool high, bool level): |
| 2323 | GPIO_PXIMS (p) = pins |
| 2324 | if level: |
| 2325 | GPIO_PXTRGC (p) = pins |
| 2326 | else: |
| 2327 | GPIO_PXTRGS (p) = pins |
| 2328 | GPIO_PXSELS (p) = pins |
| 2329 | if high: |
| 2330 | GPIO_PXDIRS (p) = pins |
| 2331 | else: |
| 2332 | GPIO_PXDIRC (p) = pins |
| 2333 | GPIO_PXFLGC (p) = pins |
| 2334 | |
| 2335 | static void gpio_set (unsigned p, unsigned pins): |
| 2336 | GPIO_PXDATS (p) = pins |
| 2337 | static void gpio_clear (unsigned p, unsigned pins): |
| 2338 | GPIO_PXDATC (p) = pins |
| 2339 | static void gpio_mask_irq (unsigned p, unsigned pins): |
| 2340 | GPIO_PXIMS (p) = pins |
| 2341 | static void gpio_unmask_irq (unsigned p, unsigned pins): |
| 2342 | GPIO_PXIMC (p) = pins |
| 2343 | static void gpio_ack_irq (unsigned p, unsigned pins): |
| 2344 | GPIO_PXFLGC (p) = pins |
| 2345 | |
| 2346 | static void gpio_enable_pull (unsigned p, unsigned pins): |
| 2347 | GPIO_PXPEC (p) = pins |
| 2348 | static void gpio_disable_pull (unsigned p, unsigned pins): |
| 2349 | GPIO_PXPES (p) = pins |
| 2350 | |
| 2351 | |
| 2352 | //************************************************************************** |
| 2353 | // CPM |
| 2354 | //************************************************************************** |
| 2355 | static void pll_init (): |
| 2356 | // The cpu clock frequency |
| 2357 | //unsigned const cpu_clock = 336000000 |
| 2358 | //unsigned const pixclock = 25846153 |
| 2359 | unsigned const cpu_clock = 200000000 |
| 2360 | unsigned const pixclock = 13500000 |
| 2361 | // Configure the pll frequency to cpu_clock. |
| 2362 | CPM_CPPCR = ((cpu_clock * 2 / JZ_EXTAL - 2) << CPM_CPPCR_PLLM_BIT) | (0 << CPM_CPPCR_PLLN_BIT) | (0 << CPM_CPPCR_PLLOD_BIT) | (0x20 << CPM_CPPCR_PLLST_BIT) | CPM_CPPCR_PLLEN |
| 2363 | // Set up dividers; see documentation for the meaning of all the values. |
| 2364 | // USB clock seems to work when bypassing the pll. (even though it must be 48 MHz according to the datasheet.) |
| 2365 | CPM_CPCCR = CPM_CPCCR_CLKOEN | (0 << CPM_CPCCR_CDIV_BIT) | (2 << CPM_CPCCR_HDIV_BIT) | (2 << CPM_CPCCR_PDIV_BIT) | (2 << CPM_CPCCR_MDIV_BIT) | (3 << CPM_CPCCR_LDIV_BIT) | CPM_CPCCR_CE | CPM_CPCCR_PCS |
| 2366 | CPM_LPCDR = (cpu_clock / pixclock) - 1 |
| 2367 | |
| 2368 | static unsigned cpm_get_pllm (): |
| 2369 | return (CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT |
| 2370 | static unsigned cpm_get_plln (): |
| 2371 | return (CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT |
| 2372 | static unsigned cpm_get_pllod (): |
| 2373 | return (CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT |
| 2374 | |
| 2375 | static unsigned cpm_get_cdiv (): |
| 2376 | return (CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT |
| 2377 | static unsigned cpm_get_hdiv (): |
| 2378 | return (CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT |
| 2379 | static unsigned cpm_get_pdiv (): |
| 2380 | return (CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT |
| 2381 | static unsigned cpm_get_mdiv (): |
| 2382 | return (CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT |
| 2383 | static unsigned cpm_get_ldiv (): |
| 2384 | return (CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT |
| 2385 | static unsigned cpm_get_udiv (): |
| 2386 | return (CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT |
| 2387 | static unsigned cpm_get_i2sdiv (): |
| 2388 | return (CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT |
| 2389 | static unsigned cpm_get_pixdiv (): |
| 2390 | return (CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT |
| 2391 | static unsigned cpm_get_mscdiv (): |
| 2392 | return (CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT |
| 2393 | static unsigned cpm_get_uhcdiv (): |
| 2394 | return (CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT |
| 2395 | static unsigned cpm_get_ssidiv (): |
| 2396 | return (CPM_SSICDR & CPM_SSICDR_SSIDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT |
| 2397 | |
| 2398 | static void cpm_set_cdiv (unsigned v): |
| 2399 | CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | (v << (CPM_CPCCR_CDIV_BIT)) |
| 2400 | static void cpm_set_hdiv (unsigned v): |
| 2401 | CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | (v << (CPM_CPCCR_HDIV_BIT)) |
| 2402 | static void cpm_set_pdiv (unsigned v): |
| 2403 | CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | (v << (CPM_CPCCR_PDIV_BIT)) |
| 2404 | static void cpm_set_mdiv (unsigned v): |
| 2405 | CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | (v << (CPM_CPCCR_MDIV_BIT)) |
| 2406 | static void cpm_set_ldiv (unsigned v): |
| 2407 | CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | (v << (CPM_CPCCR_LDIV_BIT)) |
| 2408 | static void cpm_set_udiv (unsigned v): |
| 2409 | CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | (v << (CPM_CPCCR_UDIV_BIT)) |
| 2410 | static void cpm_set_i2sdiv (unsigned v): |
| 2411 | CPM_I2SCDR = (CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | (v << (CPM_I2SCDR_I2SDIV_BIT)) |
| 2412 | static void cpm_set_pixdiv (unsigned v): |
| 2413 | CPM_LPCDR = (CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | (v << (CPM_LPCDR_PIXDIV_BIT)) |
| 2414 | static void cpm_set_mscdiv (unsigned v): |
| 2415 | CPM_MSCCDR = (CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | (v << (CPM_MSCCDR_MSCDIV_BIT)) |
| 2416 | static void cpm_set_uhcdiv (unsigned v): |
| 2417 | CPM_UHCCDR = (CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | (v << (CPM_UHCCDR_UHCDIV_BIT)) |
| 2418 | static void cpm_ssiclk_select_exclk (): |
| 2419 | CPM_SSICDR &= ~CPM_SSICDR_SCS |
| 2420 | static void cpm_ssiclk_select_pllout (): |
| 2421 | CPM_SSICDR |= CPM_SSICDR_SCS |
| 2422 | static void cpm_set_ssidiv (unsigned v): |
| 2423 | CPM_SSICDR = (CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)) |
| 2424 | |
| 2425 | #define cpm_select_i2sclk_exclk() (CPM_CPCCR &= ~CPM_CPCCR_I2CS) |
| 2426 | #define cpm_select_i2sclk_pll() (CPM_CPCCR |= CPM_CPCCR_I2CS) |
| 2427 | #define cpm_enable_cko() (CPM_CPCCR |= CPM_CPCCR_CLKOEN) |
| 2428 | #define cpm_select_usbclk_exclk() (CPM_CPCCR &= ~CPM_CPCCR_UCS) |
| 2429 | #define cpm_select_usbclk_pll() (CPM_CPCCR |= CPM_CPCCR_UCS) |
| 2430 | #define cpm_enable_pll_change() (CPM_CPCCR |= CPM_CPCCR_CE) |
| 2431 | #define cpm_pllout_direct() (CPM_CPCCR |= CPM_CPCCR_PCS) |
| 2432 | #define cpm_pllout_div2() (CPM_CPCCR &= ~CPM_CPCCR_PCS) |
| 2433 | |
| 2434 | #define cpm_pll_is_on() (CPM_CPPCR & CPM_CPPCR_PLLS) |
| 2435 | #define cpm_pll_bypass() (CPM_CPPCR |= CPM_CPPCR_PLLBP) |
| 2436 | #define cpm_pll_enable() (CPM_CPPCR |= CPM_CPPCR_PLLEN) |
| 2437 | |
| 2438 | #define cpm_get_cclk_doze_duty() ((CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) |
| 2439 | #define cpm_set_cclk_doze_duty(v) (CPM_LCR = (CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) |
| 2440 | |
| 2441 | #define cpm_doze_mode() (CPM_LCR |= CPM_LCR_DOZE_ON) |
| 2442 | #define cpm_idle_mode() (CPM_LCR = (CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) |
| 2443 | #define cpm_sleep_mode() (CPM_LCR = (CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) |
| 2444 | |
| 2445 | #define cpm_stop_all() (CPM_CLKGR = 0x7fff) |
| 2446 | #define cpm_stop_uart1() (CPM_CLKGR |= CPM_CLKGR_UART1) |
| 2447 | #define cpm_stop_uhc() (CPM_CLKGR |= CPM_CLKGR_UHC) |
| 2448 | #define cpm_stop_ipu() (CPM_CLKGR |= CPM_CLKGR_IPU) |
| 2449 | #define cpm_stop_dmac() (CPM_CLKGR |= CPM_CLKGR_DMAC) |
| 2450 | #define cpm_stop_udc() (CPM_CLKGR |= CPM_CLKGR_UDC) |
| 2451 | #define cpm_stop_lcd() (CPM_CLKGR |= CPM_CLKGR_LCD) |
| 2452 | #define cpm_stop_cim() (CPM_CLKGR |= CPM_CLKGR_CIM) |
| 2453 | #define cpm_stop_sadc() (CPM_CLKGR |= CPM_CLKGR_SADC) |
| 2454 | #define cpm_stop_msc() (CPM_CLKGR |= CPM_CLKGR_MSC) |
| 2455 | #define cpm_stop_aic1() (CPM_CLKGR |= CPM_CLKGR_AIC1) |
| 2456 | #define cpm_stop_aic2() (CPM_CLKGR |= CPM_CLKGR_AIC2) |
| 2457 | #define cpm_stop_ssi() (CPM_CLKGR |= CPM_CLKGR_SSI) |
| 2458 | #define cpm_stop_i2c() (CPM_CLKGR |= CPM_CLKGR_I2C) |
| 2459 | #define cpm_stop_rtc() (CPM_CLKGR |= CPM_CLKGR_RTC) |
| 2460 | #define cpm_stop_tcu() (CPM_CLKGR |= CPM_CLKGR_TCU) |
| 2461 | #define cpm_stop_uart0() (CPM_CLKGR |= CPM_CLKGR_UART0) |
| 2462 | |
| 2463 | #define cpm_start_all() (CPM_CLKGR = 0x0) |
| 2464 | #define cpm_start_uart1() (CPM_CLKGR &= ~CPM_CLKGR_UART1) |
| 2465 | #define cpm_start_uhc() (CPM_CLKGR &= ~CPM_CLKGR_UHC) |
| 2466 | #define cpm_start_ipu() (CPM_CLKGR &= ~CPM_CLKGR_IPU) |
| 2467 | #define cpm_start_dmac() (CPM_CLKGR &= ~CPM_CLKGR_DMAC) |
| 2468 | #define cpm_start_udc() (CPM_CLKGR &= ~CPM_CLKGR_UDC) |
| 2469 | #define cpm_start_lcd() (CPM_CLKGR &= ~CPM_CLKGR_LCD) |
| 2470 | #define cpm_start_cim() (CPM_CLKGR &= ~CPM_CLKGR_CIM) |
| 2471 | #define cpm_start_sadc() (CPM_CLKGR &= ~CPM_CLKGR_SADC) |
| 2472 | #define cpm_start_msc() (CPM_CLKGR &= ~CPM_CLKGR_MSC) |
| 2473 | #define cpm_start_aic1() (CPM_CLKGR &= ~CPM_CLKGR_AIC1) |
| 2474 | #define cpm_start_aic2() (CPM_CLKGR &= ~CPM_CLKGR_AIC2) |
| 2475 | #define cpm_start_ssi() (CPM_CLKGR &= ~CPM_CLKGR_SSI) |
| 2476 | #define cpm_start_i2c() (CPM_CLKGR &= ~CPM_CLKGR_I2C) |
| 2477 | #define cpm_start_rtc() (CPM_CLKGR &= ~CPM_CLKGR_RTC) |
| 2478 | #define cpm_start_tcu() (CPM_CLKGR &= ~CPM_CLKGR_TCU) |
| 2479 | #define cpm_start_uart0() (CPM_CLKGR &= ~CPM_CLKGR_UART0) |
| 2480 | |
| 2481 | #define cpm_get_o1st() ((CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) |
| 2482 | #define cpm_set_o1st(v) (CPM_SCR = (CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) |
| 2483 | #define cpm_suspend_usbphy() (CPM_SCR |= CPM_SCR_USBPHY_SUSPEND) |
| 2484 | #define cpm_enable_osc_in_sleep() (CPM_SCR |= CPM_SCR_OSC_ENABLE) |
| 2485 | |
| 2486 | // PLL output frequency |
| 2487 | static unsigned cpm_get_pllout (): |
| 2488 | unsigned m, n, no, pllout |
| 2489 | unsigned cppcr = CPM_CPPCR |
| 2490 | unsigned od[4] = {1, 2, 2, 4} |
| 2491 | if (cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP): |
| 2492 | m = cpm_get_pllm () + 2 |
| 2493 | n = cpm_get_plln () + 2 |
| 2494 | no = od[cpm_get_pllod ()] |
| 2495 | pllout = JZ_EXTAL * m / n / no |
| 2496 | else: |
| 2497 | pllout = JZ_EXTAL |
| 2498 | return pllout |
| 2499 | |
| 2500 | // PLL output frequency for MSC/I2S/LCD/USB |
| 2501 | static unsigned cpm_get_pllout2 (): |
| 2502 | if CPM_CPCCR & CPM_CPCCR_PCS: |
| 2503 | return cpm_get_pllout () |
| 2504 | else: |
| 2505 | return cpm_get_pllout () / 2 |
| 2506 | |
| 2507 | // CPU core clock |
| 2508 | static unsigned cpm_get_cclk (): |
| 2509 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32} |
| 2510 | return cpm_get_pllout () / div[cpm_get_cdiv ()] |
| 2511 | |
| 2512 | // AHB system bus clock |
| 2513 | static unsigned cpm_get_hclk (): |
| 2514 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32} |
| 2515 | return cpm_get_pllout () / div[cpm_get_hdiv ()] |
| 2516 | |
| 2517 | // Memory bus clock |
| 2518 | static unsigned cpm_get_mclk (): |
| 2519 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32} |
| 2520 | return cpm_get_pllout () / div[cpm_get_mdiv ()] |
| 2521 | |
| 2522 | // APB peripheral bus clock |
| 2523 | static unsigned cpm_get_pclk (): |
| 2524 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32} |
| 2525 | return cpm_get_pllout () / div[cpm_get_pdiv ()] |
| 2526 | |
| 2527 | // LCDC module clock |
| 2528 | static unsigned cpm_get_lcdclk (): |
| 2529 | return cpm_get_pllout2 () / (cpm_get_ldiv () + 1) |
| 2530 | |
| 2531 | // LCD pixel clock |
| 2532 | static unsigned cpm_get_pixclk (): |
| 2533 | return cpm_get_pllout2 () / (cpm_get_pixdiv () + 1) |
| 2534 | |
| 2535 | // I2S clock |
| 2536 | static unsigned cpm_get_i2sclk (): |
| 2537 | if CPM_CPCCR & CPM_CPCCR_I2CS: |
| 2538 | return cpm_get_pllout2 () / (cpm_get_i2sdiv () + 1) |
| 2539 | else: |
| 2540 | return JZ_EXTAL |
| 2541 | |
| 2542 | // USB clock |
| 2543 | static unsigned cpm_get_usbclk (): |
| 2544 | if CPM_CPCCR & CPM_CPCCR_UCS: |
| 2545 | return cpm_get_pllout2 () / (cpm_get_udiv () + 1) |
| 2546 | else: |
| 2547 | return JZ_EXTAL |
| 2548 | |
| 2549 | // MSC clock |
| 2550 | static unsigned cpm_get_mscclk (): |
| 2551 | return cpm_get_pllout2 () / (cpm_get_mscdiv () + 1) |
| 2552 | |
| 2553 | // EXTAL clock for UART,I2C,SSI,TCU,USB-PHY |
| 2554 | static unsigned cpm_get_extalclk (): |
| 2555 | return JZ_EXTAL |
| 2556 | |
| 2557 | // RTC clock for CPM,INTC,RTC,TCU,WDT |
| 2558 | static unsigned cpm_get_rtcclk (): |
| 2559 | return RTC_CLOCK |
| 2560 | |
| 2561 | // Output 24MHz for SD and 16MHz for MMC. |
| 2562 | static inline void cpm_select_msc_clk (int sd): |
| 2563 | unsigned int pllout2 = cpm_get_pllout2 () |
| 2564 | unsigned int div = 0 |
| 2565 | if sd: |
| 2566 | div = pllout2 / 24000000 |
| 2567 | else: |
| 2568 | div = pllout2 / 16000000 |
| 2569 | CPM_MSCCDR = div - 1 |
| 2570 | |
| 2571 | |
| 2572 | //************************************************************************** |
| 2573 | // TCU |
| 2574 | //************************************************************************** |
| 2575 | // where 'n' is the TCU channel |
| 2576 | #define tcu_select_extalclk(n) (TCU_TCSR((n)) = (TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) |
| 2577 | #define tcu_select_rtcclk(n) (TCU_TCSR((n)) = (TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) |
| 2578 | #define tcu_select_pclk(n) (TCU_TCSR((n)) = (TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) |
| 2579 | |
| 2580 | #define tcu_select_clk_div1(n) (TCU_TCSR((n)) = (TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) |
| 2581 | #define tcu_select_clk_div4(n) (TCU_TCSR((n)) = (TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) |
| 2582 | #define tcu_select_clk_div16(n) (TCU_TCSR((n)) = (TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) |
| 2583 | #define tcu_select_clk_div64(n) (TCU_TCSR((n)) = (TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) |
| 2584 | #define tcu_select_clk_div256(n) (TCU_TCSR((n)) = (TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) |
| 2585 | #define tcu_select_clk_div1024(n) (TCU_TCSR((n)) = (TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) |
| 2586 | |
| 2587 | #define tcu_enable_pwm_output(n) ( TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) |
| 2588 | #define tcu_disable_pwm_output(n) ( TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) |
| 2589 | |
| 2590 | #define tcu_init_pwm_output_high(n) ( TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) |
| 2591 | #define tcu_init_pwm_output_low(n) ( TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) |
| 2592 | |
| 2593 | #define tcu_set_pwm_output_shutdown_graceful(n) ( TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) |
| 2594 | #define tcu_set_pwm_output_shutdown_abrupt(n) ( TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) |
| 2595 | |
| 2596 | #define tcu_start_counter(n) ( TCU_TESR |= (1 << (n)) ) |
| 2597 | #define tcu_stop_counter(n) ( TCU_TECR |= (1 << (n)) ) |
| 2598 | |
| 2599 | #define tcu_half_match_flag(n) ( TCU_TFR & (1 << ((n) + 16)) ) |
| 2600 | #define tcu_full_match_flag(n) ( TCU_TFR & (1 << (n)) ) |
| 2601 | #define tcu_set_half_match_flag(n) ( TCU_TFSR = (1 << ((n) + 16)) ) |
| 2602 | #define tcu_set_full_match_flag(n) ( TCU_TFSR = (1 << (n)) ) |
| 2603 | #define tcu_clear_half_match_flag(n) ( TCU_TFCR = (1 << ((n) + 16)) ) |
| 2604 | #define tcu_clear_full_match_flag(n) ( TCU_TFCR = (1 << (n)) ) |
| 2605 | #define tcu_mask_half_match_irq(n) ( TCU_TMSR = (1 << ((n) + 16)) ) |
| 2606 | #define tcu_mask_full_match_irq(n) ( TCU_TMSR = (1 << (n)) ) |
| 2607 | #define tcu_unmask_half_match_irq(n) ( TCU_TMCR = (1 << ((n) + 16)) ) |
| 2608 | #define tcu_unmask_full_match_irq(n) ( TCU_TMCR = (1 << (n)) ) |
| 2609 | |
| 2610 | #define tcu_wdt_clock_stopped() ( TCU_TSR & TCU_TSSR_WDTSC ) |
| 2611 | #define tcu_timer_clock_stopped(n) ( TCU_TSR & (1 << (n)) ) |
| 2612 | |
| 2613 | #define tcu_start_wdt_clock() ( TCU_TSCR = TCU_TSSR_WDTSC ) |
| 2614 | #define tcu_start_timer_clock(n) ( TCU_TSCR = (1 << (n)) ) |
| 2615 | |
| 2616 | #define tcu_stop_wdt_clock() ( TCU_TSSR = TCU_TSSR_WDTSC ) |
| 2617 | #define tcu_stop_timer_clock(n) ( TCU_TSSR = (1 << (n)) ) |
| 2618 | |
| 2619 | #define tcu_get_count(n) ( TCU_TCNT((n)) ) |
| 2620 | #define tcu_set_count(n,v) ( TCU_TCNT((n)) = (v) ) |
| 2621 | #define tcu_set_full_data(n,v) ( TCU_TDFR((n)) = (v) ) |
| 2622 | #define tcu_set_half_data(n,v) ( TCU_TDHR((n)) = (v) ) |
| 2623 | |
| 2624 | |
| 2625 | //************************************************************************** |
| 2626 | // WDT |
| 2627 | //************************************************************************** |
| 2628 | #define wdt_start() ( WDT_TCER |= WDT_TCER_TCEN ) |
| 2629 | #define wdt_stop() ( WDT_TCER &= ~WDT_TCER_TCEN ) |
| 2630 | #define wdt_set_count(v) ( WDT_TCNT = (v) ) |
| 2631 | #define wdt_set_data(v) ( WDT_TDR = (v) ) |
| 2632 | |
| 2633 | #define wdt_select_extalclk() (WDT_TCSR = (WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) |
| 2634 | #define wdt_select_rtcclk() (WDT_TCSR = (WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) |
| 2635 | #define wdt_select_pclk() (WDT_TCSR = (WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) |
| 2636 | |
| 2637 | #define wdt_select_clk_div1() (WDT_TCSR = (WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) |
| 2638 | #define wdt_select_clk_div4() (WDT_TCSR = (WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) |
| 2639 | #define wdt_select_clk_div16() (WDT_TCSR = (WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) |
| 2640 | #define wdt_select_clk_div64() (WDT_TCSR = (WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) |
| 2641 | #define wdt_select_clk_div256() (WDT_TCSR = (WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) |
| 2642 | #define wdt_select_clk_div1024() (WDT_TCSR = (WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) |
| 2643 | |
| 2644 | |
| 2645 | //************************************************************************** |
| 2646 | // UART |
| 2647 | //************************************************************************** |
| 2648 | |
| 2649 | #define uart_enable(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) |= UARTFCR_UUE | UARTFCR_FE ) |
| 2650 | #define uart_disable(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE ) |
| 2651 | |
| 2652 | #define uart_enable_transmit_irq(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE ) |
| 2653 | #define uart_disable_transmit_irq(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE ) |
| 2654 | |
| 2655 | #define uart_enable_receive_irq(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) |
| 2656 | #define uart_disable_receive_irq(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) |
| 2657 | |
| 2658 | #define uart_enable_loopback(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP ) |
| 2659 | #define uart_disable_loopback(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP ) |
| 2660 | |
| 2661 | #define uart_set_8n1(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 ) |
| 2662 | |
| 2663 | static void uart_set_baud (unsigned n, unsigned devclk, unsigned baud): |
| 2664 | REG8 (UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB |
| 2665 | REG8 (UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff |
| 2666 | REG8 (UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff |
| 2667 | REG8 (UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB |
| 2668 | |
| 2669 | #define uart_parity_error(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 ) |
| 2670 | |
| 2671 | #define uart_clear_errors(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) |
| 2672 | |
| 2673 | #define uart_transmit_fifo_empty(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 ) |
| 2674 | |
| 2675 | #define uart_transmit_end(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 ) |
| 2676 | |
| 2677 | #define uart_transmit_char(n, ch) REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch) |
| 2678 | |
| 2679 | #define uart_receive_fifo_full(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) |
| 2680 | |
| 2681 | #define uart_receive_ready(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) |
| 2682 | |
| 2683 | #define uart_receive_char(n) REG8(UART_BASE + UART_OFF*(n) + OFF_RDR) |
| 2684 | |
| 2685 | #define uart_disable_irda() ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) |
| 2686 | #define uart_enable_irda() /* Tx high pulse as 0, Rx low pulse as 0 */ ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) |
| 2687 | |
| 2688 | |
| 2689 | //************************************************************************** |
| 2690 | // DMAC |
| 2691 | //************************************************************************** |
| 2692 | |
| 2693 | // n is the DMA channel (0 - 5) |
| 2694 | |
| 2695 | #define dmac_enable_module() ( DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) |
| 2696 | #define dmac_disable_module() ( DMAC_DMACR &= ~DMAC_DMACR_DMAE ) |
| 2697 | |
| 2698 | // p=0,1,2,3 |
| 2699 | static void dmac_set_priority (unsigned p): |
| 2700 | DMAC_DMACR &= ~DMAC_DMACR_PR_MASK |
| 2701 | DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT) |
| 2702 | |
| 2703 | #define dmac_test_halt_error() ( DMAC_DMACR & DMAC_DMACR_HLT ) |
| 2704 | #define dmac_test_addr_error() ( DMAC_DMACR & DMAC_DMACR_AR ) |
| 2705 | |
| 2706 | #define dmac_enable_descriptor(n) ( DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) |
| 2707 | #define dmac_disable_descriptor(n) ( DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) |
| 2708 | |
| 2709 | #define dmac_enable_channel(n) ( DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) |
| 2710 | #define dmac_disable_channel(n) ( DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) |
| 2711 | #define dmac_channel_enabled(n) ( DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) |
| 2712 | |
| 2713 | #define dmac_channel_enable_irq(n) ( DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) |
| 2714 | #define dmac_channel_disable_irq(n) ( DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) |
| 2715 | |
| 2716 | #define dmac_channel_transmit_halt_detected(n) ( DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) |
| 2717 | #define dmac_channel_transmit_end_detected(n) ( DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) |
| 2718 | #define dmac_channel_address_error_detected(n) ( DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) |
| 2719 | #define dmac_channel_count_terminated_detected(n) ( DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) |
| 2720 | #define dmac_channel_descriptor_invalid_detected(n) ( DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) |
| 2721 | |
| 2722 | #define dmac_channel_clear_transmit_halt(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) |
| 2723 | #define dmac_channel_clear_transmit_end(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) |
| 2724 | #define dmac_channel_clear_address_error(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) |
| 2725 | #define dmac_channel_clear_count_terminated(n) ( DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) |
| 2726 | #define dmac_channel_clear_descriptor_invalid(n) ( DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) |
| 2727 | |
| 2728 | #define dmac_channel_set_single_mode(n) ( DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) |
| 2729 | #define dmac_channel_set_block_mode(n) ( DMAC_DCMD((n)) |= DMAC_DCMD_TM ) |
| 2730 | |
| 2731 | static void dmac_channel_set_transfer_unit_32bit (unsigned n): |
| 2732 | DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK |
| 2733 | DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT |
| 2734 | |
| 2735 | static void dmac_channel_set_transfer_unit_16bit (unsigned n): |
| 2736 | DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK |
| 2737 | DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT |
| 2738 | |
| 2739 | static void dmac_channel_set_transfer_unit_8bit (unsigned n): |
| 2740 | DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK |
| 2741 | DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT |
| 2742 | |
| 2743 | static void dmac_channel_set_transfer_unit_16byte (unsigned n): |
| 2744 | DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK |
| 2745 | DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE |
| 2746 | |
| 2747 | static void dmac_channel_set_transfer_unit_32byte (unsigned n): |
| 2748 | DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK |
| 2749 | DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE |
| 2750 | |
| 2751 | // w=8,16,32 |
| 2752 | #define dmac_channel_set_dest_port_width(n,w) do { DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; } while (0) |
| 2753 | |
| 2754 | // w=8,16,32 |
| 2755 | #define dmac_channel_set_src_port_width(n,v) do { DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; } while (0) |
| 2756 | |
| 2757 | // v=0-15 |
| 2758 | static void dmac_channel_set_rdil(unsigned n, unsigned v): |
| 2759 | DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK |
| 2760 | DMAC_DCMD((n)) |= ((v) << DMAC_DCMD_RDIL_BIT) |
| 2761 | |
| 2762 | #define dmac_channel_dest_addr_fixed(n) ( DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) |
| 2763 | #define dmac_channel_dest_addr_increment(n) ( DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) |
| 2764 | |
| 2765 | #define dmac_channel_src_addr_fixed(n) ( DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) |
| 2766 | #define dmac_channel_src_addr_increment(n) ( DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) |
| 2767 | |
| 2768 | #define dmac_channel_set_doorbell(n) ( DMAC_DMADBSR = (1 << (n)) ) |
| 2769 | |
| 2770 | #define dmac_channel_irq_detected(n) ( DMAC_DMAIPR & (1 << (n)) ) |
| 2771 | #define dmac_channel_ack_irq(n) ( DMAC_DMAIPR &= ~(1 << (n)) ) |
| 2772 | |
| 2773 | |
| 2774 | //************************************************************************** |
| 2775 | // AIC (AC'97 & I2S Controller) |
| 2776 | //************************************************************************** |
| 2777 | |
| 2778 | #define aic_enable() ( AIC_FR |= AIC_FR_ENB ) |
| 2779 | #define aic_disable() ( AIC_FR &= ~AIC_FR_ENB ) |
| 2780 | |
| 2781 | #define aic_select_ac97() ( AIC_FR &= ~AIC_FR_AUSEL ) |
| 2782 | #define aic_select_i2s() ( AIC_FR |= AIC_FR_AUSEL ) |
| 2783 | |
| 2784 | #define aic_play_zero() ( AIC_FR &= ~AIC_FR_LSMP ) |
| 2785 | #define aic_play_lastsample() ( AIC_FR |= AIC_FR_LSMP ) |
| 2786 | |
| 2787 | #define i2s_as_master() ( AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) |
| 2788 | #define i2s_as_slave() ( AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) |
| 2789 | #define aic_reset_status() ( AIC_FR & AIC_FR_RST ) |
| 2790 | |
| 2791 | static void aic_reset(): |
| 2792 | AIC_FR |= AIC_FR_RST |
| 2793 | |
| 2794 | static void aic_set_transmit_trigger (unsigned n): |
| 2795 | AIC_FR &= ~AIC_FR_TFTH_MASK |
| 2796 | AIC_FR |= ((n) << AIC_FR_TFTH_BIT) |
| 2797 | |
| 2798 | static void aic_set_receive_trigger (unsigned n): |
| 2799 | AIC_FR &= ~AIC_FR_RFTH_MASK |
| 2800 | AIC_FR |= ((n) << AIC_FR_RFTH_BIT) |
| 2801 | |
| 2802 | #define aic_enable_record() ( AIC_CR |= AIC_CR_EREC ) |
| 2803 | #define aic_disable_record() ( AIC_CR &= ~AIC_CR_EREC ) |
| 2804 | #define aic_enable_replay() ( AIC_CR |= AIC_CR_ERPL ) |
| 2805 | #define aic_disable_replay() ( AIC_CR &= ~AIC_CR_ERPL ) |
| 2806 | #define aic_enable_loopback() ( AIC_CR |= AIC_CR_ENLBF ) |
| 2807 | #define aic_disable_loopback() ( AIC_CR &= ~AIC_CR_ENLBF ) |
| 2808 | |
| 2809 | #define aic_flush_fifo() ( AIC_CR |= AIC_CR_FLUSH ) |
| 2810 | #define aic_unflush_fifo() ( AIC_CR &= ~AIC_CR_FLUSH ) |
| 2811 | |
| 2812 | #define aic_enable_transmit_intr() ( AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) |
| 2813 | #define aic_disable_transmit_intr() ( AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) |
| 2814 | #define aic_enable_receive_intr() ( AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) |
| 2815 | #define aic_disable_receive_intr() ( AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) |
| 2816 | |
| 2817 | #define aic_enable_transmit_dma() ( AIC_CR |= AIC_CR_TDMS ) |
| 2818 | #define aic_disable_transmit_dma() ( AIC_CR &= ~AIC_CR_TDMS ) |
| 2819 | #define aic_enable_receive_dma() ( AIC_CR |= AIC_CR_RDMS ) |
| 2820 | #define aic_disable_receive_dma() ( AIC_CR &= ~AIC_CR_RDMS ) |
| 2821 | |
| 2822 | #define aic_enable_mono2stereo() ( AIC_CR |= AIC_CR_M2S ) |
| 2823 | #define aic_disable_mono2stereo() ( AIC_CR &= ~AIC_CR_M2S ) |
| 2824 | #define aic_enable_byteswap() ( AIC_CR |= AIC_CR_ENDSW ) |
| 2825 | #define aic_disable_byteswap() ( AIC_CR &= ~AIC_CR_ENDSW ) |
| 2826 | #define aic_enable_unsignadj() ( AIC_CR |= AIC_CR_AVSTSU ) |
| 2827 | #define aic_disable_unsignadj() ( AIC_CR &= ~AIC_CR_AVSTSU ) |
| 2828 | |
| 2829 | #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 |
| 2830 | #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 |
| 2831 | #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 |
| 2832 | #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 |
| 2833 | #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 |
| 2834 | #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 |
| 2835 | |
| 2836 | #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 |
| 2837 | #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 |
| 2838 | #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 |
| 2839 | #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 |
| 2840 | #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 |
| 2841 | #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 |
| 2842 | |
| 2843 | #define ac97_set_xs_none() ( AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) |
| 2844 | static void ac97_set_xs_mono(): |
| 2845 | AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK |
| 2846 | AIC_ACCR1 |= AC97_PCM_XS_R_FRONT |
| 2847 | static void ac97_set_xs_stereo(): |
| 2848 | AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK |
| 2849 | AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT |
| 2850 | |
| 2851 | // In fact, only stereo is support now. |
| 2852 | #define ac97_set_rs_none() ( AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) |
| 2853 | static void ac97_set_rs_mono(): |
| 2854 | AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK |
| 2855 | AIC_ACCR1 |= AC97_PCM_RS_R_FRONT |
| 2856 | static void ac97_set_rs_stereo(): |
| 2857 | AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK |
| 2858 | AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT |
| 2859 | |
| 2860 | static void ac97_warm_reset_codec(): |
| 2861 | AIC_ACCR2 |= AIC_ACCR2_SA |
| 2862 | AIC_ACCR2 |= AIC_ACCR2_SS |
| 2863 | //udelay(2) // TODO |
| 2864 | AIC_ACCR2 &= ~AIC_ACCR2_SS |
| 2865 | AIC_ACCR2 &= ~AIC_ACCR2_SA |
| 2866 | |
| 2867 | static void ac97_cold_reset_codec(): |
| 2868 | AIC_ACCR2 |= AIC_ACCR2_SR |
| 2869 | //udelay(2) // TODO |
| 2870 | AIC_ACCR2 &= ~AIC_ACCR2_SR |
| 2871 | |
| 2872 | // n=8,16,18,20 |
| 2873 | #define ac97_set_iass(n) ( AIC_ACCR2 = (AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) |
| 2874 | #define ac97_set_oass(n) ( AIC_ACCR2 = (AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) |
| 2875 | |
| 2876 | #define i2s_select_i2s() ( AIC_I2SCR &= ~AIC_I2SCR_AMSL ) |
| 2877 | #define i2s_select_msbjustified() ( AIC_I2SCR |= AIC_I2SCR_AMSL ) |
| 2878 | |
| 2879 | // n=8,16,18,20,24 |
| 2880 | //#define i2s_set_sample_size(n) ( AIC_I2SCR |= (AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT ) |
| 2881 | |
| 2882 | #define i2s_set_oss_sample_size(n) ( AIC_CR = (AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) |
| 2883 | #define i2s_set_iss_sample_size(n) ( AIC_CR = (AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) |
| 2884 | |
| 2885 | #define i2s_stop_bitclk() ( AIC_I2SCR |= AIC_I2SCR_STPBK ) |
| 2886 | #define i2s_start_bitclk() ( AIC_I2SCR &= ~AIC_I2SCR_STPBK ) |
| 2887 | |
| 2888 | #define aic_transmit_request() ( AIC_SR & AIC_SR_TFS ) |
| 2889 | #define aic_receive_request() ( AIC_SR & AIC_SR_RFS ) |
| 2890 | #define aic_transmit_underrun() ( AIC_SR & AIC_SR_TUR ) |
| 2891 | #define aic_receive_overrun() ( AIC_SR & AIC_SR_ROR ) |
| 2892 | |
| 2893 | #define aic_clear_errors() ( AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) |
| 2894 | |
| 2895 | #define aic_get_transmit_resident() ( (AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) |
| 2896 | #define aic_get_receive_count() ( (AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) |
| 2897 | |
| 2898 | #define ac97_command_transmitted() ( AIC_ACSR & AIC_ACSR_CADT ) |
| 2899 | #define ac97_status_received() ( AIC_ACSR & AIC_ACSR_SADR ) |
| 2900 | #define ac97_status_receive_timeout() ( AIC_ACSR & AIC_ACSR_RSTO ) |
| 2901 | #define ac97_codec_is_low_power_mode() ( AIC_ACSR & AIC_ACSR_CLPM ) |
| 2902 | #define ac97_codec_is_ready() ( AIC_ACSR & AIC_ACSR_CRDY ) |
| 2903 | #define ac97_slot_error_detected() ( AIC_ACSR & AIC_ACSR_SLTERR ) |
| 2904 | #define ac97_clear_slot_error() ( AIC_ACSR &= ~AIC_ACSR_SLTERR ) |
| 2905 | |
| 2906 | #define i2s_is_busy() ( AIC_I2SSR & AIC_I2SSR_BSY ) |
| 2907 | |
| 2908 | #define CODEC_READ_CMD (1 << 19) |
| 2909 | #define CODEC_WRITE_CMD (0 << 19) |
| 2910 | #define CODEC_REG_INDEX_BIT 12 |
| 2911 | #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) // 18:12 |
| 2912 | #define CODEC_REG_DATA_BIT 4 |
| 2913 | #define CODEC_REG_DATA_MASK (0x0ffff << 4) // 19:4 |
| 2914 | |
| 2915 | #define ac97_out_rcmd_addr(reg) (AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT)) |
| 2916 | |
| 2917 | #define ac97_out_wcmd_addr(reg) (AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT)) |
| 2918 | |
| 2919 | #define ac97_out_data(value) (AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT)) |
| 2920 | |
| 2921 | #define ac97_in_data() ( (AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) |
| 2922 | |
| 2923 | #define ac97_in_status_addr() ( (AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) |
| 2924 | |
| 2925 | #define i2s_set_sample_rate(i2sclk, sync) ( AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) |
| 2926 | |
| 2927 | #define aic_write_tfifo(v) ( AIC_DR = (v) ) |
| 2928 | #define aic_read_rfifo() ( AIC_DR ) |
| 2929 | |
| 2930 | #define aic_internal_codec() ( AIC_FR |= AIC_FR_ICDC ) |
| 2931 | #define aic_external_codec() ( AIC_FR &= ~AIC_FR_ICDC ) |
| 2932 | |
| 2933 | // |
| 2934 | // Define next ops for AC97 compatible |
| 2935 | // |
| 2936 | |
| 2937 | #define AC97_ACSR AIC_ACSR |
| 2938 | |
| 2939 | #define ac97_enable() aic_enable(); aic_select_ac97() |
| 2940 | #define ac97_disable() aic_disable() |
| 2941 | #define ac97_reset() aic_reset() |
| 2942 | |
| 2943 | #define ac97_set_transmit_trigger(n) aic_set_transmit_trigger(n) |
| 2944 | #define ac97_set_receive_trigger(n) aic_set_receive_trigger(n) |
| 2945 | |
| 2946 | #define ac97_enable_record() aic_enable_record() |
| 2947 | #define ac97_disable_record() aic_disable_record() |
| 2948 | #define ac97_enable_replay() aic_enable_replay() |
| 2949 | #define ac97_disable_replay() aic_disable_replay() |
| 2950 | #define ac97_enable_loopback() aic_enable_loopback() |
| 2951 | #define ac97_disable_loopback() aic_disable_loopback() |
| 2952 | |
| 2953 | #define ac97_enable_transmit_dma() aic_enable_transmit_dma() |
| 2954 | #define ac97_disable_transmit_dma() aic_disable_transmit_dma() |
| 2955 | #define ac97_enable_receive_dma() aic_enable_receive_dma() |
| 2956 | #define ac97_disable_receive_dma() aic_disable_receive_dma() |
| 2957 | |
| 2958 | #define ac97_transmit_request() aic_transmit_request() |
| 2959 | #define ac97_receive_request() aic_receive_request() |
| 2960 | #define ac97_transmit_underrun() aic_transmit_underrun() |
| 2961 | #define ac97_receive_overrun() aic_receive_overrun() |
| 2962 | |
| 2963 | #define ac97_clear_errors() aic_clear_errors() |
| 2964 | |
| 2965 | #define ac97_get_transmit_resident() aic_get_transmit_resident() |
| 2966 | #define ac97_get_receive_count() aic_get_receive_count() |
| 2967 | |
| 2968 | #define ac97_enable_transmit_intr() aic_enable_transmit_intr() |
| 2969 | #define ac97_disable_transmit_intr() aic_disable_transmit_intr() |
| 2970 | #define ac97_enable_receive_intr() aic_enable_receive_intr() |
| 2971 | #define ac97_disable_receive_intr() aic_disable_receive_intr() |
| 2972 | |
| 2973 | #define ac97_write_tfifo(v) aic_write_tfifo(v) |
| 2974 | #define ac97_read_rfifo() aic_read_rfifo() |
| 2975 | |
| 2976 | // |
| 2977 | // Define next ops for I2S compatible |
| 2978 | // |
| 2979 | |
| 2980 | #define I2S_ACSR AIC_I2SSR |
| 2981 | |
| 2982 | #define i2s_enable() aic_enable(); aic_select_i2s() |
| 2983 | #define i2s_disable() aic_disable() |
| 2984 | #define i2s_reset() aic_reset() |
| 2985 | |
| 2986 | #define i2s_set_transmit_trigger(n) aic_set_transmit_trigger(n) |
| 2987 | #define i2s_set_receive_trigger(n) aic_set_receive_trigger(n) |
| 2988 | |
| 2989 | #define i2s_enable_record() aic_enable_record() |
| 2990 | #define i2s_disable_record() aic_disable_record() |
| 2991 | #define i2s_enable_replay() aic_enable_replay() |
| 2992 | #define i2s_disable_replay() aic_disable_replay() |
| 2993 | #define i2s_enable_loopback() aic_enable_loopback() |
| 2994 | #define i2s_disable_loopback() aic_disable_loopback() |
| 2995 | |
| 2996 | #define i2s_enable_transmit_dma() aic_enable_transmit_dma() |
| 2997 | #define i2s_disable_transmit_dma() aic_disable_transmit_dma() |
| 2998 | #define i2s_enable_receive_dma() aic_enable_receive_dma() |
| 2999 | #define i2s_disable_receive_dma() aic_disable_receive_dma() |
| 3000 | |
| 3001 | #define i2s_transmit_request() aic_transmit_request() |
| 3002 | #define i2s_receive_request() aic_receive_request() |
| 3003 | #define i2s_transmit_underrun() aic_transmit_underrun() |
| 3004 | #define i2s_receive_overrun() aic_receive_overrun() |
| 3005 | |
| 3006 | #define i2s_clear_errors() aic_clear_errors() |
| 3007 | |
| 3008 | #define i2s_get_transmit_resident() aic_get_transmit_resident() |
| 3009 | #define i2s_get_receive_count() aic_get_receive_count() |
| 3010 | |
| 3011 | #define i2s_enable_transmit_intr() aic_enable_transmit_intr() |
| 3012 | #define i2s_disable_transmit_intr() aic_disable_transmit_intr() |
| 3013 | #define i2s_enable_receive_intr() aic_enable_receive_intr() |
| 3014 | #define i2s_disable_receive_intr() aic_disable_receive_intr() |
| 3015 | |
| 3016 | #define i2s_write_tfifo(v) aic_write_tfifo(v) |
| 3017 | #define i2s_read_rfifo() aic_read_rfifo() |
| 3018 | |
| 3019 | #define i2s_reset_codec() do { } while (0) |
| 3020 | |
| 3021 | static void aic_use_internal_codec (): |
| 3022 | aic_internal_codec () |
| 3023 | aic_select_i2s () |
| 3024 | i2s_as_slave () |
| 3025 | i2s_select_i2s () |
| 3026 | cpm_select_i2sclk_exclk () |
| 3027 | cpm_set_i2sdiv (1) |
| 3028 | |
| 3029 | //************************************************************************** |
| 3030 | // ICDC |
| 3031 | //************************************************************************** |
| 3032 | #define i2s_internal_codec() aic_internal_codec() |
| 3033 | #define i2s_external_codec() aic_external_codec() |
| 3034 | |
| 3035 | //************************************************************************** |
| 3036 | // INTC |
| 3037 | //************************************************************************** |
| 3038 | #define intc_unmask_irq(n) ( INTC_IMCR = (1 << (n)) ) |
| 3039 | #define intc_mask_irq(n) ( INTC_IMSR = (1 << (n)) ) |
| 3040 | #define intc_ack_irq(n) ( INTC_IPR = (1 << (n)) ) |
| 3041 | |
| 3042 | |
| 3043 | //************************************************************************** |
| 3044 | // I2C |
| 3045 | //************************************************************************** |
| 3046 | |
| 3047 | #define i2c_enable() ( I2C_CR |= I2C_CR_I2CE ) |
| 3048 | #define i2c_disable() ( I2C_CR &= ~I2C_CR_I2CE ) |
| 3049 | |
| 3050 | #define i2c_send_start() ( I2C_CR |= I2C_CR_STA ) |
| 3051 | #define i2c_send_stop() ( I2C_CR |= I2C_CR_STO ) |
| 3052 | #define i2c_send_ack() ( I2C_CR &= ~I2C_CR_AC ) |
| 3053 | #define i2c_send_nack() ( I2C_CR |= I2C_CR_AC ) |
| 3054 | |
| 3055 | #define i2c_set_drf() ( I2C_SR |= I2C_SR_DRF ) |
| 3056 | #define i2c_clear_drf() ( I2C_SR &= ~I2C_SR_DRF ) |
| 3057 | #define i2c_check_drf() ( I2C_SR & I2C_SR_DRF ) |
| 3058 | |
| 3059 | #define i2c_received_ack() ( !(I2C_SR & I2C_SR_ACKF) ) |
| 3060 | #define i2c_is_busy() ( I2C_SR & I2C_SR_BUSY ) |
| 3061 | #define i2c_transmit_ended() ( I2C_SR & I2C_SR_TEND ) |
| 3062 | |
| 3063 | #define i2c_set_clk(dev_clk, i2c_clk) ( I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) |
| 3064 | |
| 3065 | #define i2c_read() ( I2C_DR ) |
| 3066 | #define i2c_write(val) ( I2C_DR = (val) ) |
| 3067 | |
| 3068 | |
| 3069 | //************************************************************************** |
| 3070 | // MSC |
| 3071 | //************************************************************************** |
| 3072 | |
| 3073 | #define msc_start_op() ( MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) |
| 3074 | |
| 3075 | #define msc_set_resto(to) ( MSC_RESTO = to ) |
| 3076 | #define msc_set_rdto(to) ( MSC_RDTO = to ) |
| 3077 | #define msc_set_cmd(cmd) ( MSC_CMD = cmd ) |
| 3078 | #define msc_set_arg(arg) ( MSC_ARG = arg ) |
| 3079 | #define msc_set_nob(nob) ( MSC_NOB = nob ) |
| 3080 | #define msc_get_nob() ( MSC_NOB ) |
| 3081 | #define msc_set_blklen(len) ( MSC_BLKLEN = len ) |
| 3082 | #define msc_set_cmdat(cmdat) ( MSC_CMDAT = cmdat ) |
| 3083 | #define msc_set_cmdat_ioabort() ( MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) |
| 3084 | #define msc_clear_cmdat_ioabort() ( MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) |
| 3085 | |
| 3086 | static void msc_set_cmdat_bus_width1(): |
| 3087 | MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK |
| 3088 | MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT |
| 3089 | |
| 3090 | static void msc_set_cmdat_bus_width4(): |
| 3091 | MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK |
| 3092 | MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT |
| 3093 | |
| 3094 | #define msc_set_cmdat_dma_en() ( MSC_CMDAT |= MSC_CMDAT_DMA_EN ) |
| 3095 | #define msc_set_cmdat_init() ( MSC_CMDAT |= MSC_CMDAT_INIT ) |
| 3096 | #define msc_set_cmdat_busy() ( MSC_CMDAT |= MSC_CMDAT_BUSY ) |
| 3097 | #define msc_set_cmdat_stream() ( MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) |
| 3098 | #define msc_set_cmdat_block() ( MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) |
| 3099 | #define msc_set_cmdat_read() ( MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) |
| 3100 | #define msc_set_cmdat_write() ( MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) |
| 3101 | #define msc_set_cmdat_data_en() ( MSC_CMDAT |= MSC_CMDAT_DATA_EN ) |
| 3102 | |
| 3103 | // r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE |
| 3104 | static void msc_set_cmdat_res_format(unsigned r): |
| 3105 | MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_MASK |
| 3106 | MSC_CMDAT |= (r) |
| 3107 | |
| 3108 | #define msc_clear_cmdat() MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_MASK ) |
| 3109 | |
| 3110 | #define msc_get_imask() ( MSC_IMASK ) |
| 3111 | #define msc_mask_all_intrs() ( MSC_IMASK = 0xff ) |
| 3112 | #define msc_unmask_all_intrs() ( MSC_IMASK = 0x00 ) |
| 3113 | #define msc_mask_rd() ( MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) |
| 3114 | #define msc_unmask_rd() ( MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) |
| 3115 | #define msc_mask_wr() ( MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) |
| 3116 | #define msc_unmask_wr() ( MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) |
| 3117 | #define msc_mask_endcmdres() ( MSC_IMASK |= MSC_IMASK_END_CMD_RES ) |
| 3118 | #define msc_unmask_endcmdres() ( MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) |
| 3119 | #define msc_mask_datatrandone() ( MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) |
| 3120 | #define msc_unmask_datatrandone() ( MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) |
| 3121 | #define msc_mask_prgdone() ( MSC_IMASK |= MSC_IMASK_PRG_DONE ) |
| 3122 | #define msc_unmask_prgdone() ( MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) |
| 3123 | |
| 3124 | // n=0,1,2,3,4,5,6,7 |
| 3125 | #define msc_set_clkrt(n) (MSC_CLKRT = n) |
| 3126 | |
| 3127 | #define msc_get_ireg() ( MSC_IREG ) |
| 3128 | #define msc_ireg_rd() ( MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) |
| 3129 | #define msc_ireg_wr() ( MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) |
| 3130 | #define msc_ireg_end_cmd_res() ( MSC_IREG & MSC_IREG_END_CMD_RES ) |
| 3131 | #define msc_ireg_data_tran_done() ( MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) |
| 3132 | #define msc_ireg_prg_done() ( MSC_IREG & MSC_IREG_PRG_DONE ) |
| 3133 | #define msc_ireg_clear_end_cmd_res() ( MSC_IREG = MSC_IREG_END_CMD_RES ) |
| 3134 | #define msc_ireg_clear_data_tran_done() ( MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) |
| 3135 | #define msc_ireg_clear_prg_done() ( MSC_IREG = MSC_IREG_PRG_DONE ) |
| 3136 | |
| 3137 | #define msc_get_stat() ( MSC_STAT ) |
| 3138 | #define msc_stat_not_end_cmd_res() ( (MSC_STAT & MSC_STAT_END_CMD_RES) == 0) |
| 3139 | #define msc_stat_crc_err() ( MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) |
| 3140 | #define msc_stat_res_crc_err() ( MSC_STAT & MSC_STAT_CRC_RES_ERR ) |
| 3141 | #define msc_stat_rd_crc_err() ( MSC_STAT & MSC_STAT_CRC_READ_ERROR ) |
| 3142 | #define msc_stat_wr_crc_err() ( MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) |
| 3143 | #define msc_stat_resto_err() ( MSC_STAT & MSC_STAT_TIME_OUT_RES ) |
| 3144 | #define msc_stat_rdto_err() ( MSC_STAT & MSC_STAT_TIME_OUT_READ ) |
| 3145 | |
| 3146 | #define msc_rd_resfifo() ( MSC_RES ) |
| 3147 | #define msc_rd_rxfifo() ( MSC_RXFIFO ) |
| 3148 | #define msc_wr_txfifo(v) ( MSC_TXFIFO = v ) |
| 3149 | |
| 3150 | #define msc_start_clk() (MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START) |
| 3151 | |
| 3152 | #define MMC_CLK 19169200 |
| 3153 | #define SD_CLK 24576000 |
| 3154 | |
| 3155 | // msc_clk should little than pclk and little than clk retrieve from card |
| 3156 | static unsigned msc_calc_clk_divisor (bool sd, unsigned dev_clk, unsigned msc_clk): |
| 3157 | unsigned int rate, pclk, i |
| 3158 | pclk = dev_clk |
| 3159 | rate = sd ? SD_CLK : MMC_CLK |
| 3160 | if msc_clk && msc_clk < pclk: |
| 3161 | pclk = msc_clk |
| 3162 | i = 0 |
| 3163 | while pclk < rate: |
| 3164 | i ++ |
| 3165 | rate >>= 1 |
| 3166 | return i |
| 3167 | |
| 3168 | // divide rate to little than or equal to 400kHz |
| 3169 | static unsigned msc_calc_slow_clk_divisor (bool sd): |
| 3170 | unsigned rate, i |
| 3171 | rate = (sd ? SD_CLK : MMC_CLK) / 1000 / 400 |
| 3172 | i = 0 |
| 3173 | while rate > 0: |
| 3174 | rate >>= 1 |
| 3175 | ++i |
| 3176 | return i |
| 3177 | |
| 3178 | |
| 3179 | //************************************************************************** |
| 3180 | // SSI |
| 3181 | //************************************************************************** |
| 3182 | |
| 3183 | #define ssi_enable() ( SSI_CR0 |= SSI_CR0_SSIE ) |
| 3184 | #define ssi_disable() ( SSI_CR0 &= ~SSI_CR0_SSIE ) |
| 3185 | #define ssi_select_ce() ( SSI_CR0 &= ~SSI_CR0_FSEL ) |
| 3186 | |
| 3187 | #define ssi_normal_mode() ( SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) |
| 3188 | |
| 3189 | static void ssi_select_ce2 (): |
| 3190 | SSI_CR0 |= SSI_CR0_FSEL |
| 3191 | SSI_CR1 &= ~SSI_CR1_MULTS |
| 3192 | |
| 3193 | static void ssi_select_gpc (): |
| 3194 | SSI_CR0 &= ~SSI_CR0_FSEL |
| 3195 | SSI_CR1 |= SSI_CR1_MULTS |
| 3196 | |
| 3197 | #define ssi_enable_tx_intr() ( SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) |
| 3198 | |
| 3199 | #define ssi_disable_tx_intr() ( SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) |
| 3200 | |
| 3201 | #define ssi_enable_rx_intr() ( SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) |
| 3202 | |
| 3203 | #define ssi_disable_rx_intr() ( SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) |
| 3204 | |
| 3205 | #define ssi_enable_txfifo_half_empty_intr() ( SSI_CR0 |= SSI_CR0_TIE ) |
| 3206 | #define ssi_disable_txfifo_half_empty_intr() ( SSI_CR0 &= ~SSI_CR0_TIE ) |
| 3207 | #define ssi_enable_tx_error_intr() ( SSI_CR0 |= SSI_CR0_TEIE ) |
| 3208 | #define ssi_disable_tx_error_intr() ( SSI_CR0 &= ~SSI_CR0_TEIE ) |
| 3209 | |
| 3210 | #define ssi_enable_rxfifo_half_full_intr() ( SSI_CR0 |= SSI_CR0_RIE ) |
| 3211 | #define ssi_disable_rxfifo_half_full_intr() ( SSI_CR0 &= ~SSI_CR0_RIE ) |
| 3212 | #define ssi_enable_rx_error_intr() ( SSI_CR0 |= SSI_CR0_REIE ) |
| 3213 | #define ssi_disable_rx_error_intr() ( SSI_CR0 &= ~SSI_CR0_REIE ) |
| 3214 | |
| 3215 | #define ssi_enable_loopback() ( SSI_CR0 |= SSI_CR0_LOOP ) |
| 3216 | #define ssi_disable_loopback() ( SSI_CR0 &= ~SSI_CR0_LOOP ) |
| 3217 | |
| 3218 | #define ssi_enable_receive() ( SSI_CR0 &= ~SSI_CR0_DISREV ) |
| 3219 | #define ssi_disable_receive() ( SSI_CR0 |= SSI_CR0_DISREV ) |
| 3220 | |
| 3221 | #define ssi_finish_receive() ( SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
| 3222 | |
| 3223 | #define ssi_disable_recvfinish() ( SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
| 3224 | |
| 3225 | #define ssi_flush_txfifo() ( SSI_CR0 |= SSI_CR0_TFLUSH ) |
| 3226 | #define ssi_flush_rxfifo() ( SSI_CR0 |= SSI_CR0_RFLUSH ) |
| 3227 | |
| 3228 | #define ssi_flush_fifo() ( SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) |
| 3229 | |
| 3230 | #define ssi_finish_transmit() ( SSI_CR1 &= ~SSI_CR1_UNFIN ) |
| 3231 | |
| 3232 | static void ssi_spi_format(): |
| 3233 | SSI_CR1 &= ~SSI_CR1_FMAT_MASK |
| 3234 | SSI_CR1 |= SSI_CR1_FMAT_SPI |
| 3235 | SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK) |
| 3236 | SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1) |
| 3237 | |
| 3238 | // TI's SSP format, must clear SSI_CR1.UNFIN |
| 3239 | static void ssi_ssp_format (): |
| 3240 | SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN) |
| 3241 | SSI_CR1 |= SSI_CR1_FMAT_SSP |
| 3242 | |
| 3243 | // National's Microwire format, must clear SSI_CR0.RFINE, and set max delay |
| 3244 | static void ssi_microwire_format (): |
| 3245 | SSI_CR1 &= ~SSI_CR1_FMAT_MASK |
| 3246 | SSI_CR1 |= SSI_CR1_FMAT_MW1 |
| 3247 | SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK) |
| 3248 | SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3) |
| 3249 | SSI_CR0 &= ~SSI_CR0_RFINE |
| 3250 | |
| 3251 | // CE# level (FRMHL), CE# in interval time (ITFRM), clock phase and polarity (PHA POL), interval time (SSIITR), interval characters/frame (SSIICR) |
| 3252 | // frmhl,endian,mcom,flen,pha,pol MASK |
| 3253 | #define SSICR1_MISC_MASK ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) |
| 3254 | static void ssi_spi_set_misc (unsigned frmhl, unsigned endian, unsigned flen, unsigned mcom, unsigned pha, unsigned pol): |
| 3255 | SSI_CR1 &= ~SSICR1_MISC_MASK |
| 3256 | SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | (((mcom) - 1) << 12) | (((flen) - 2) << 4) | ((pha) << 1) | (pol) |
| 3257 | |
| 3258 | // Transfer with MSB or LSB first |
| 3259 | #define ssi_set_msb() ( SSI_CR1 &= ~SSI_CR1_LFST ) |
| 3260 | #define ssi_set_lsb() ( SSI_CR1 |= SSI_CR1_LFST ) |
| 3261 | |
| 3262 | #define ssi_set_frame_length(n) SSI_CR1 = (SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) |
| 3263 | |
| 3264 | // n = 1 - 16 |
| 3265 | #define ssi_set_microwire_command_length(n) ( SSI_CR1 = ((SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) |
| 3266 | |
| 3267 | // Set the clock phase for SPI |
| 3268 | #define ssi_set_spi_clock_phase(n) ( SSI_CR1 = ((SSI_CR1 & ~SSI_CR1_PHA) | ((n&0x1)<< 1))) |
| 3269 | |
| 3270 | // Set the clock polarity for SPI |
| 3271 | #define ssi_set_spi_clock_polarity(n) ( SSI_CR1 = ((SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) |
| 3272 | |
| 3273 | // n = ix8 |
| 3274 | #define ssi_set_tx_trigger(n) do { SSI_CR1 &= ~SSI_CR1_TTRG_MASK; SSI_CR1 |= SSI_CR1_TTRG_##n; } while (0) |
| 3275 | |
| 3276 | // n = ix8 |
| 3277 | #define ssi_set_rx_trigger(n) do { SSI_CR1 &= ~SSI_CR1_RTRG_MASK; SSI_CR1 |= SSI_CR1_RTRG_##n; } while (0) |
| 3278 | |
| 3279 | #define ssi_get_txfifo_count() ( (SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) |
| 3280 | |
| 3281 | #define ssi_get_rxfifo_count() ( (SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) |
| 3282 | |
| 3283 | #define ssi_clear_errors() ( SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) |
| 3284 | |
| 3285 | #define ssi_transfer_end() ( SSI_SR & SSI_SR_END ) |
| 3286 | #define ssi_is_busy() ( SSI_SR & SSI_SR_BUSY ) |
| 3287 | |
| 3288 | #define ssi_txfifo_full() ( SSI_SR & SSI_SR_TFF ) |
| 3289 | #define ssi_rxfifo_empty() ( SSI_SR & SSI_SR_RFE ) |
| 3290 | #define ssi_rxfifo_noempty() ( SSI_SR & SSI_SR_RFHF ) |
| 3291 | |
| 3292 | #define ssi_set_clk(dev_clk, ssi_clk) ( SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) |
| 3293 | |
| 3294 | #define ssi_receive_data() SSI_DR |
| 3295 | #define ssi_transmit_data(v) ( SSI_DR = (v) ) |
| 3296 | |
| 3297 | |
| 3298 | //************************************************************************** |
| 3299 | // CIM |
| 3300 | //************************************************************************** |
| 3301 | |
| 3302 | #define cim_enable() ( CIM_CTRL |= CIM_CTRL_ENA ) |
| 3303 | #define cim_disable() ( CIM_CTRL &= ~CIM_CTRL_ENA ) |
| 3304 | |
| 3305 | #define cim_input_data_inverse() ( CIM_CFG |= CIM_CFG_INV_DAT ) |
| 3306 | #define cim_input_data_normal() ( CIM_CFG &= ~CIM_CFG_INV_DAT ) |
| 3307 | |
| 3308 | #define cim_vsync_active_low() ( CIM_CFG |= CIM_CFG_VSP ) |
| 3309 | #define cim_vsync_active_high() ( CIM_CFG &= ~CIM_CFG_VSP ) |
| 3310 | |
| 3311 | #define cim_hsync_active_low() ( CIM_CFG |= CIM_CFG_HSP ) |
| 3312 | #define cim_hsync_active_high() ( CIM_CFG &= ~CIM_CFG_HSP ) |
| 3313 | |
| 3314 | #define cim_sample_data_at_pclk_falling_edge() ( CIM_CFG |= CIM_CFG_PCP ) |
| 3315 | #define cim_sample_data_at_pclk_rising_edge() ( CIM_CFG &= ~CIM_CFG_PCP ) |
| 3316 | |
| 3317 | #define cim_enable_dummy_zero() ( CIM_CFG |= CIM_CFG_DUMMY_ZERO ) |
| 3318 | #define cim_disable_dummy_zero() ( CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) |
| 3319 | |
| 3320 | #define cim_select_external_vsync() ( CIM_CFG |= CIM_CFG_EXT_VSYNC ) |
| 3321 | #define cim_select_internal_vsync() ( CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) |
| 3322 | |
| 3323 | // n=0-7 |
| 3324 | #define cim_set_data_packing_mode(n) do { CIM_CFG &= ~CIM_CFG_PACK_MASK; CIM_CFG |= (CIM_CFG_PACK_##n); } while (0) |
| 3325 | |
| 3326 | static void cim_enable_ccir656_progressive_mode (): |
| 3327 | CIM_CFG &= ~CIM_CFG_DSM_MASK |
| 3328 | CIM_CFG |= CIM_CFG_DSM_CPM |
| 3329 | |
| 3330 | static void cim_enable_ccir656_interlace_mode (): |
| 3331 | CIM_CFG &= ~CIM_CFG_DSM_MASK |
| 3332 | CIM_CFG |= CIM_CFG_DSM_CIM |
| 3333 | |
| 3334 | static void cim_enable_gated_clock_mode (): |
| 3335 | CIM_CFG &= ~CIM_CFG_DSM_MASK |
| 3336 | CIM_CFG |= CIM_CFG_DSM_GCM |
| 3337 | |
| 3338 | static void cim_enable_nongated_clock_mode (): |
| 3339 | CIM_CFG &= ~CIM_CFG_DSM_MASK |
| 3340 | CIM_CFG |= CIM_CFG_DSM_NGCM |
| 3341 | |
| 3342 | // sclk:system bus clock |
| 3343 | // mclk: CIM master clock |
| 3344 | #define cim_set_master_clk(sclk, mclk) do { CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); } while (0) |
| 3345 | |
| 3346 | #define cim_enable_sof_intr() ( CIM_CTRL |= CIM_CTRL_DMA_SOFM ) |
| 3347 | #define cim_disable_sof_intr() ( CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) |
| 3348 | |
| 3349 | #define cim_enable_eof_intr() ( CIM_CTRL |= CIM_CTRL_DMA_EOFM ) |
| 3350 | #define cim_disable_eof_intr() ( CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) |
| 3351 | |
| 3352 | #define cim_enable_stop_intr() ( CIM_CTRL |= CIM_CTRL_DMA_STOPM ) |
| 3353 | #define cim_disable_stop_intr() ( CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) |
| 3354 | |
| 3355 | #define cim_enable_trig_intr() ( CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) |
| 3356 | #define cim_disable_trig_intr() ( CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) |
| 3357 | |
| 3358 | #define cim_enable_rxfifo_overflow_intr() ( CIM_CTRL |= CIM_CTRL_RXF_OFM ) |
| 3359 | #define cim_disable_rxfifo_overflow_intr() ( CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) |
| 3360 | |
| 3361 | // n=1-16 |
| 3362 | #define cim_set_frame_rate(n) do { CIM_CTRL &= ~CIM_CTRL_FRC_MASK; CIM_CTRL |= CIM_CTRL_FRC_##n; } while (0) |
| 3363 | |
| 3364 | #define cim_enable_dma() ( CIM_CTRL |= CIM_CTRL_DMA_EN ) |
| 3365 | #define cim_disable_dma() ( CIM_CTRL &= ~CIM_CTRL_DMA_EN ) |
| 3366 | |
| 3367 | #define cim_reset_rxfifo() ( CIM_CTRL |= CIM_CTRL_RXF_RST ) |
| 3368 | #define cim_unreset_rxfifo() ( CIM_CTRL &= ~CIM_CTRL_RXF_RST ) |
| 3369 | |
| 3370 | // n=4,8,12,16,20,24,28,32 |
| 3371 | #define cim_set_rxfifo_trigger(n) do { CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; } while (0) |
| 3372 | |
| 3373 | #define cim_clear_state() ( CIM_STATE = 0 ) |
| 3374 | |
| 3375 | #define cim_disable_done() ( CIM_STATE & CIM_STATE_VDD ) |
| 3376 | #define cim_rxfifo_empty() ( CIM_STATE & CIM_STATE_RXF_EMPTY ) |
| 3377 | #define cim_rxfifo_reach_trigger() ( CIM_STATE & CIM_STATE_RXF_TRIG ) |
| 3378 | #define cim_rxfifo_overflow() ( CIM_STATE & CIM_STATE_RXF_OF ) |
| 3379 | #define cim_clear_rxfifo_overflow() ( CIM_STATE &= ~CIM_STATE_RXF_OF ) |
| 3380 | #define cim_dma_stop() ( CIM_STATE & CIM_STATE_DMA_STOP ) |
| 3381 | #define cim_dma_eof() ( CIM_STATE & CIM_STATE_DMA_EOF ) |
| 3382 | #define cim_dma_sof() ( CIM_STATE & CIM_STATE_DMA_SOF ) |
| 3383 | |
| 3384 | #define cim_get_iid() ( CIM_IID ) |
| 3385 | #define cim_get_image_data() ( CIM_RXFIFO ) |
| 3386 | #define cim_get_dam_cmd() ( CIM_CMD ) |
| 3387 | |
| 3388 | #define cim_set_da(a) ( CIM_DA = (a) ) |
| 3389 | |
| 3390 | //************************************************************************** |
| 3391 | // LCD |
| 3392 | //************************************************************************** |
| 3393 | #define lcd_as_smart_lcd() ( LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) ) |
| 3394 | #define lcd_as_general_lcd() ( LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) ) |
| 3395 | |
| 3396 | #define lcd_set_dis() ( LCD_CTRL |= LCD_CTRL_DIS ) |
| 3397 | #define lcd_clr_dis() ( LCD_CTRL &= ~LCD_CTRL_DIS ) |
| 3398 | |
| 3399 | #define lcd_set_ena() ( LCD_CTRL |= LCD_CTRL_ENA ) |
| 3400 | #define lcd_clr_ena() ( LCD_CTRL &= ~LCD_CTRL_ENA ) |
| 3401 | |
| 3402 | // n=1,2,4,8,16 |
| 3403 | #define lcd_set_bpp(n) ( LCD_CTRL = (LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) |
| 3404 | |
| 3405 | // n=4,8,16 |
| 3406 | #define lcd_set_burst_length(n) do { LCD_CTRL &= ~LCD_CTRL_BST_MASK; LCD_CTRL |= LCD_CTRL_BST_n##; } while (0) |
| 3407 | |
| 3408 | #define lcd_select_rgb565() ( LCD_CTRL &= ~LCD_CTRL_RGB555 ) |
| 3409 | #define lcd_select_rgb555() ( LCD_CTRL |= LCD_CTRL_RGB555 ) |
| 3410 | |
| 3411 | #define lcd_set_ofup() ( LCD_CTRL |= LCD_CTRL_OFUP ) |
| 3412 | #define lcd_clr_ofup() ( LCD_CTRL &= ~LCD_CTRL_OFUP ) |
| 3413 | |
| 3414 | // n=2,4,16 |
| 3415 | #define lcd_set_stn_frc(n) do { LCD_CTRL &= ~LCD_CTRL_FRC_MASK; LCD_CTRL |= LCD_CTRL_FRC_n##; } while (0) |
| 3416 | |
| 3417 | |
| 3418 | #define lcd_pixel_endian_little() ( LCD_CTRL |= LCD_CTRL_PEDN ) |
| 3419 | #define lcd_pixel_endian_big() ( LCD_CTRL &= ~LCD_CTRL_PEDN ) |
| 3420 | |
| 3421 | #define lcd_reverse_byte_endian() ( LCD_CTRL |= LCD_CTRL_BEDN ) |
| 3422 | #define lcd_normal_byte_endian() ( LCD_CTRL &= ~LCD_CTRL_BEDN ) |
| 3423 | |
| 3424 | #define lcd_enable_eof_intr() ( LCD_CTRL |= LCD_CTRL_EOFM ) |
| 3425 | #define lcd_disable_eof_intr() ( LCD_CTRL &= ~LCD_CTRL_EOFM ) |
| 3426 | |
| 3427 | #define lcd_enable_sof_intr() ( LCD_CTRL |= LCD_CTRL_SOFM ) |
| 3428 | #define lcd_disable_sof_intr() ( LCD_CTRL &= ~LCD_CTRL_SOFM ) |
| 3429 | |
| 3430 | #define lcd_enable_ofu_intr() ( LCD_CTRL |= LCD_CTRL_OFUM ) |
| 3431 | #define lcd_disable_ofu_intr() ( LCD_CTRL &= ~LCD_CTRL_OFUM ) |
| 3432 | |
| 3433 | #define lcd_enable_ifu0_intr() ( LCD_CTRL |= LCD_CTRL_IFUM0 ) |
| 3434 | #define lcd_disable_ifu0_intr() ( LCD_CTRL &= ~LCD_CTRL_IFUM0 ) |
| 3435 | |
| 3436 | #define lcd_enable_ifu1_intr() ( LCD_CTRL |= LCD_CTRL_IFUM1 ) |
| 3437 | #define lcd_disable_ifu1_intr() ( LCD_CTRL &= ~LCD_CTRL_IFUM1 ) |
| 3438 | |
| 3439 | #define lcd_enable_ldd_intr() ( LCD_CTRL |= LCD_CTRL_LDDM ) |
| 3440 | #define lcd_disable_ldd_intr() ( LCD_CTRL &= ~LCD_CTRL_LDDM ) |
| 3441 | |
| 3442 | #define lcd_enable_qd_intr() ( LCD_CTRL |= LCD_CTRL_QDM ) |
| 3443 | #define lcd_disable_qd_intr() ( LCD_CTRL &= ~LCD_CTRL_QDM ) |
| 3444 | |
| 3445 | |
| 3446 | // LCD status register indication |
| 3447 | |
| 3448 | #define lcd_quick_disable_done() ( LCD_STATE & LCD_STATE_QD ) |
| 3449 | #define lcd_disable_done() ( LCD_STATE & LCD_STATE_LDD ) |
| 3450 | #define lcd_infifo0_underrun() ( LCD_STATE & LCD_STATE_IFU0 ) |
| 3451 | #define lcd_infifo1_underrun() ( LCD_STATE & LCD_STATE_IFU1 ) |
| 3452 | #define lcd_outfifo_underrun() ( LCD_STATE & LCD_STATE_OFU ) |
| 3453 | #define lcd_start_of_frame() ( LCD_STATE & LCD_STATE_SOF ) |
| 3454 | #define lcd_end_of_frame() ( LCD_STATE & LCD_STATE_EOF ) |
| 3455 | |
| 3456 | #define lcd_clr_outfifounderrun() ( LCD_STATE &= ~LCD_STATE_OFU ) |
| 3457 | #define lcd_clr_sof() ( LCD_STATE &= ~LCD_STATE_SOF ) |
| 3458 | #define lcd_clr_eof() ( LCD_STATE &= ~LCD_STATE_EOF ) |
| 3459 | |
| 3460 | #define lcd_panel_white() ( LCD_CFG |= LCD_CFG_WHITE ) |
| 3461 | #define lcd_panel_black() ( LCD_CFG &= ~LCD_CFG_WHITE ) |
| 3462 | |
| 3463 | // n=1,2,4,8 for single mono-STN |
| 3464 | // n=4,8 for dual mono-STN |
| 3465 | #define lcd_set_panel_datawidth(n) do { LCD_CFG &= ~LCD_CFG_PDW_MASK; LCD_CFG |= LCD_CFG_PDW_n##; } while (0) |
| 3466 | |
| 3467 | // m=LCD_CFG_MODE_GENERUIC_TFT_xxx |
| 3468 | #define lcd_set_panel_mode(m) do { LCD_CFG &= ~LCD_CFG_MODE_MASK; LCD_CFG |= (m); } while(0) |
| 3469 | |
| 3470 | // n = 0-255 |
| 3471 | #define lcd_disable_ac_bias() ( LCD_IO = 0xff ) |
| 3472 | #define lcd_set_ac_bias(n) do { LCD_IO &= ~LCD_IO_ACB_MASK; LCD_IO |= ((n) << LCD_IO_ACB_BIT); } while(0) |
| 3473 | |
| 3474 | #define lcd_io_set_dir() ( LCD_IO |= LCD_IO_DIR ) |
| 3475 | #define lcd_io_clr_dir() ( LCD_IO &= ~LCD_IO_DIR ) |
| 3476 | |
| 3477 | #define lcd_io_set_dep() ( LCD_IO |= LCD_IO_DEP ) |
| 3478 | #define lcd_io_clr_dep() ( LCD_IO &= ~LCD_IO_DEP ) |
| 3479 | |
| 3480 | #define lcd_io_set_vsp() ( LCD_IO |= LCD_IO_VSP ) |
| 3481 | #define lcd_io_clr_vsp() ( LCD_IO &= ~LCD_IO_VSP ) |
| 3482 | |
| 3483 | #define lcd_io_set_hsp() ( LCD_IO |= LCD_IO_HSP ) |
| 3484 | #define lcd_io_clr_hsp() ( LCD_IO &= ~LCD_IO_HSP ) |
| 3485 | |
| 3486 | #define lcd_io_set_pcp() ( LCD_IO |= LCD_IO_PCP ) |
| 3487 | #define lcd_io_clr_pcp() ( LCD_IO &= ~LCD_IO_PCP ) |
| 3488 | |
| 3489 | #define lcd_vsync_get_vps() ( (LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) |
| 3490 | |
| 3491 | #define lcd_vsync_get_vpe() ( (LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) |
| 3492 | #define lcd_vsync_set_vpe(n) do { LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; } while (0) |
| 3493 | |
| 3494 | #define lcd_hsync_get_hps() ( (LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) |
| 3495 | #define lcd_hsync_set_hps(n) do { LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; } while (0) |
| 3496 | |
| 3497 | #define lcd_hsync_get_hpe() ( (LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) |
| 3498 | #define lcd_hsync_set_hpe(n) do { LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; } while (0) |
| 3499 | |
| 3500 | #define lcd_vat_get_ht() ( (LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) |
| 3501 | #define lcd_vat_set_ht(n) do { LCD_VAT &= ~LCD_VAT_HT_MASK; LCD_VAT |= (n) << LCD_VAT_HT_BIT; } while (0) |
| 3502 | |
| 3503 | #define lcd_vat_get_vt() ( (LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) |
| 3504 | #define lcd_vat_set_vt(n) do { LCD_VAT &= ~LCD_VAT_VT_MASK; LCD_VAT |= (n) << LCD_VAT_VT_BIT; } while (0) |
| 3505 | |
| 3506 | #define lcd_dah_get_hds() ( (LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) |
| 3507 | #define lcd_dah_set_hds(n) do { LCD_DAH &= ~LCD_DAH_HDS_MASK; LCD_DAH |= (n) << LCD_DAH_HDS_BIT; } while (0) |
| 3508 | |
| 3509 | #define lcd_dah_get_hde() ( (LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) |
| 3510 | #define lcd_dah_set_hde(n) do { LCD_DAH &= ~LCD_DAH_HDE_MASK; LCD_DAH |= (n) << LCD_DAH_HDE_BIT; } while (0) |
| 3511 | |
| 3512 | #define lcd_dav_get_vds() ( (LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) |
| 3513 | #define lcd_dav_set_vds(n) do { LCD_DAV &= ~LCD_DAV_VDS_MASK; LCD_DAV |= (n) << LCD_DAV_VDS_BIT; } while (0) |
| 3514 | |
| 3515 | #define lcd_dav_get_vde() ( (LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) |
| 3516 | #define lcd_dav_set_vde(n) do { LCD_DAV &= ~LCD_DAV_VDE_MASK; LCD_DAV |= (n) << LCD_DAV_VDE_BIT; } while (0) |
| 3517 | |
| 3518 | #define lcd_cmd0_set_sofint() ( LCD_CMD0 |= LCD_CMD_SOFINT ) |
| 3519 | #define lcd_cmd0_clr_sofint() ( LCD_CMD0 &= ~LCD_CMD_SOFINT ) |
| 3520 | #define lcd_cmd1_set_sofint() ( LCD_CMD1 |= LCD_CMD_SOFINT ) |
| 3521 | #define lcd_cmd1_clr_sofint() ( LCD_CMD1 &= ~LCD_CMD_SOFINT ) |
| 3522 | |
| 3523 | #define lcd_cmd0_set_eofint() ( LCD_CMD0 |= LCD_CMD_EOFINT ) |
| 3524 | #define lcd_cmd0_clr_eofint() ( LCD_CMD0 &= ~LCD_CMD_EOFINT ) |
| 3525 | #define lcd_cmd1_set_eofint() ( LCD_CMD1 |= LCD_CMD_EOFINT ) |
| 3526 | #define lcd_cmd1_clr_eofint() ( LCD_CMD1 &= ~LCD_CMD_EOFINT ) |
| 3527 | |
| 3528 | #define lcd_cmd0_set_pal() ( LCD_CMD0 |= LCD_CMD_PAL ) |
| 3529 | #define lcd_cmd0_clr_pal() ( LCD_CMD0 &= ~LCD_CMD_PAL ) |
| 3530 | |
| 3531 | #define lcd_cmd0_get_len() ( (LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
| 3532 | #define lcd_cmd1_get_len() ( (LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
| 3533 | |
| 3534 | //************************************************************************** |
| 3535 | // RTC ops |
| 3536 | //************************************************************************** |
| 3537 | |
| 3538 | #define rtc_write_ready() ( (RTC_RCR & RTC_RCR_WRDY) >> RTC_RCR_WRDY_BIT ) |
| 3539 | #define rtc_enabled() ( RTC_RCR |= RTC_RCR_RTCE ) |
| 3540 | #define rtc_disabled() ( RTC_RCR &= ~RTC_RCR_RTCE ) |
| 3541 | #define rtc_enable_alarm() ( RTC_RCR |= RTC_RCR_AE ) |
| 3542 | #define rtc_disable_alarm() ( RTC_RCR &= ~RTC_RCR_AE ) |
| 3543 | #define rtc_alarm_is_enabled() ( RTC_RCR & RTC_RCR_AE ) |
| 3544 | #define rtc_enable_alarm_irq() ( RTC_RCR |= RTC_RCR_AIE ) |
| 3545 | #define rtc_disable_alarm_irq() ( RTC_RCR &= ~RTC_RCR_AIE ) |
| 3546 | #define rtc_enable_1Hz_irq() ( RTC_RCR |= RTC_RCR_1HZIE ) |
| 3547 | #define rtc_disable_1Hz_irq() ( RTC_RCR &= ~RTC_RCR_1HZIE ) |
| 3548 | |
| 3549 | #define rtc_get_1Hz_flag() ( (RTC_RCR >> RTC_RCR_1HZ_BIT) & 0x1 ) |
| 3550 | #define rtc_clear_1Hz_flag() ( RTC_RCR &= ~RTC_RCR_1HZ ) |
| 3551 | #define rtc_get_alarm_flag() ( (RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 ) |
| 3552 | #define rtc_clear_alarm_flag() ( RTC_RCR &= ~RTC_RCR_AF ) |
| 3553 | |
| 3554 | #define rtc_get_second() ( RTC_RSR ) |
| 3555 | #define rtc_set_second(v) ( RTC_RSR = v ) |
| 3556 | |
| 3557 | #define rtc_get_alarm_second() ( RTC_RSAR ) |
| 3558 | #define rtc_set_alarm_second(v) ( RTC_RSAR = v ) |
| 3559 | |
| 3560 | #define rtc_RGR_is_locked() ( (RTC_RGR >> RTC_RGR_LOCK) ) |
| 3561 | #define rtc_lock_RGR() ( RTC_RGR |= RTC_RGR_LOCK ) |
| 3562 | #define rtc_unlock_RGR() ( RTC_RGR &= ~RTC_RGR_LOCK ) |
| 3563 | #define rtc_get_adjc_val() ( (RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ) |
| 3564 | #define rtc_set_adjc_val(v) ( RTC_RGR = ( (RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) |
| 3565 | #define rtc_get_nc1Hz_val() ( (RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) |
| 3566 | #define rtc_set_nc1Hz_val(v) ( RTC_RGR = ( (RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) |
| 3567 | |
| 3568 | #define rtc_power_down() ( RTC_HCR |= RTC_HCR_PD ) |
| 3569 | |
| 3570 | #define rtc_get_hwfcr_val() ( RTC_HWFCR & RTC_HWFCR_MASK ) |
| 3571 | #define rtc_set_hwfcr_val(v) ( RTC_HWFCR = (v) & RTC_HWFCR_MASK ) |
| 3572 | #define rtc_get_hrcr_val() ( RTC_HRCR & RTC_HRCR_MASK ) |
| 3573 | #define rtc_set_hrcr_val(v) ( RTC_HRCR = (v) & RTC_HRCR_MASK ) |
| 3574 | |
| 3575 | #define rtc_enable_alarm_wakeup() ( RTC_HWCR |= RTC_HWCR_EALM ) |
| 3576 | #define rtc_disable_alarm_wakeup() ( RTC_HWCR &= ~RTC_HWCR_EALM ) |
| 3577 | |
| 3578 | #define rtc_status_hib_reset_occur() ( (RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ) |
| 3579 | #define rtc_status_ppr_reset_occur() ( (RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ) |
| 3580 | #define rtc_status_wakeup_pin_waken_up() ( (RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ) |
| 3581 | #define rtc_status_alarm_waken_up() ( (RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ) |
| 3582 | #define rtc_clear_hib_stat_all() ( RTC_HWRSR = 0 ) |
| 3583 | |
| 3584 | #define rtc_get_scratch_pattern() (RTC_HSPR) |
| 3585 | #define rtc_set_scratch_pattern(n) (RTC_HSPR = n ) |
| 3586 | |
| 3587 | |
| 3588 | #ifdef __KERNEL__ |
| 3589 | static void setup_sdram (): |
| 3590 | // SDRAM BANK Number: 1, 2 |
| 3591 | unsigned CONFIG_NR_DRAM_BANKS = 1 |
| 3592 | // CAS latency: 2 or 3 |
| 3593 | unsigned SDRAM_CASL = 2 |
| 3594 | // SDRAM Timings, unit: ns |
| 3595 | // RAS# Active Time |
| 3596 | unsigned SDRAM_TRAS = 45 |
| 3597 | // RAS# to CAS# Delay |
| 3598 | unsigned SDRAM_RCD = 20 |
| 3599 | // RAS# Precharge Time |
| 3600 | unsigned SDRAM_TPC = 20 |
| 3601 | // Write Latency Time |
| 3602 | unsigned SDRAM_TRWL = 7 |
| 3603 | // Refresh period: 4096 refresh cycles/64ms |
| 3604 | unsigned SDRAM_TREF = 7812 |
| 3605 | unsigned dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns |
| 3606 | unsigned cas_latency_sdmr[2] = { EMC_SDMR_CAS_2, EMC_SDMR_CAS_3 } |
| 3607 | unsigned cas_latency_dmcr[2] = { 1 << EMC_DMCR_TCL_BIT, 2 << EMC_DMCR_TCL_BIT } |
| 3608 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32} |
| 3609 | |
| 3610 | cpu_clk = 252000000 |
| 3611 | gpio_as_sdram_16bit () |
| 3612 | unsigned SDRAM_BW16 = 1 |
| 3613 | unsigned SDRAM_BANK4 = 1 |
| 3614 | unsigned SDRAM_ROW = 12 |
| 3615 | unsigned SDRAM_COL = 8 |
| 3616 | |
| 3617 | mem_clk = cpu_clk * div[cpm_get_cdiv()] / div[cpm_get_mdiv()] |
| 3618 | EMC_BCR = 0 |
| 3619 | EMC_RTCSR = 0 |
| 3620 | unsigned SDRAM_BW160 = 0 |
| 3621 | unsigned SDRAM_ROW0 = 11 |
| 3622 | unsigned SDRAM_COL0 = 8 |
| 3623 | unsigned SDRAM_BANK40 = 0 |
| 3624 | dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | (SDRAM_BW160<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)] |
| 3625 | // Basic DMCR value |
| 3626 | dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)] |
| 3627 | // SDRAM timimg |
| 3628 | ns = 1000000000 / mem_clk |
| 3629 | tmp = SDRAM_TRAS / ns |
| 3630 | if tmp < 4: |
| 3631 | tmp = 4 |
| 3632 | if tmp > 11: |
| 3633 | tmp = 11 |
| 3634 | dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT) |
| 3635 | tmp = SDRAM_RCD/ns |
| 3636 | if tmp > 3: |
| 3637 | tmp = 3 |
| 3638 | dmcr |= (tmp << EMC_DMCR_RCD_BIT) |
| 3639 | tmp = SDRAM_TPC/ns |
| 3640 | if tmp > 7: |
| 3641 | tmp = 7 |
| 3642 | dmcr |= (tmp << EMC_DMCR_TPC_BIT) |
| 3643 | tmp = SDRAM_TRWL/ns |
| 3644 | if tmp > 3: |
| 3645 | tmp = 3 |
| 3646 | dmcr |= (tmp << EMC_DMCR_TRWL_BIT) |
| 3647 | tmp = (SDRAM_TRAS + SDRAM_TPC)/ns |
| 3648 | if tmp > 14: |
| 3649 | tmp = 14 |
| 3650 | dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT) |
| 3651 | |
| 3652 | // SDRAM mode value |
| 3653 | sdmode = EMC_SDMR_BT_SEQ | EMC_SDMR_OM_NORMAL | EMC_SDMR_BL_4 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; |
| 3654 | |
| 3655 | // Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 |
| 3656 | EMC_DMCR = dmcr |
| 3657 | REG8(EMC_SDMR0|sdmode) = 0 |
| 3658 | |
| 3659 | // Wait for precharge, > 200us |
| 3660 | tmp = (cpu_clk / 1000000) * 1000 |
| 3661 | volatile unsigned t = tmp |
| 3662 | while t--: |
| 3663 | |
| 3664 | // Stage 2. Enable auto-refresh |
| 3665 | EMC_DMCR = dmcr | EMC_DMCR_RFSH |
| 3666 | |
| 3667 | tmp = SDRAM_TREF/ns |
| 3668 | tmp = tmp/64 + 1 |
| 3669 | if tmp > 0xff: |
| 3670 | tmp = 0xff |
| 3671 | EMC_RTCOR = tmp |
| 3672 | EMC_RTCNT = 0 |
| 3673 | // Divisor is 64, CKO/64 |
| 3674 | EMC_RTCSR = EMC_RTCSR_CKS_64 |
| 3675 | |
| 3676 | // Wait for number of auto-refresh cycles |
| 3677 | tmp = (cpu_clk / 1000000) * 1000 |
| 3678 | t = tmp |
| 3679 | while t--: |
| 3680 | |
| 3681 | // Stage 3. Mode Register Set |
| 3682 | EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET |
| 3683 | REG8(EMC_SDMR0|sdmode) = 0 |
| 3684 | |
| 3685 | // Set back to basic DMCR value |
| 3686 | EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET |
| 3687 | #if 0 |
| 3688 | EMC_SMCR (0) = 0x00000080 |
| 3689 | EMC_SMCR (1) = 0x094c4400 |
| 3690 | EMC_SMCR (2) = 0x0fff7700 |
| 3691 | EMC_SMCR (3) = 0x0fff7700 |
| 3692 | EMC_SMCR (4) = 0x0fff7700 |
| 3693 | EMC_SACR (0) = 0x1cfc |
| 3694 | EMC_SACR (1) = 0x18fc |
| 3695 | EMC_SACR (2) = 0x14fc |
| 3696 | EMC_SACR (3) = 0x0cfc |
| 3697 | EMC_SACR (4) = 0x08fc |
| 3698 | EMC_DMCR = 0x85aa3211 |
| 3699 | EMC_RTCSR = 0x83 |
| 3700 | EMC_RTCOR = 0x1f |
| 3701 | #endif |
| 3702 | #if 0 |
| 3703 | for unsigned i = 0; i < 5; ++i: |
| 3704 | dbg_log ("memory: ") |
| 3705 | dbg_log_num (EMC_SMCR (i), 8) |
| 3706 | dbg_log (",") |
| 3707 | dbg_log_num (EMC_SACR (i), 8) |
| 3708 | dbg_log (";") |
| 3709 | dbg_log_num (EMC_RTCSR, 8) |
| 3710 | dbg_log (",") |
| 3711 | dbg_log_num (EMC_RTCOR, 8) |
| 3712 | dbg_log ("\n") |
| 3713 | #endif |
| 3714 | |
| 3715 | static void setup_uart (bool send_only = false): |
| 3716 | // Set up uart. |
| 3717 | #ifndef NDEBUG |
| 3718 | cpm_start_uart0 () |
| 3719 | enable_uart0_debug () |
| 3720 | gpio_as_uart0 (send_only) |
| 3721 | UART0_IER = 0 |
| 3722 | UART0_FCR = 0 |
| 3723 | UART0_MCR = 0 |
| 3724 | UART0_SIRCR = 0 |
| 3725 | UART0_UACR = 0 |
| 3726 | UART0_UMR = 16 |
| 3727 | UART0_LCR = UARTLCR_WLEN_8 | UARTLCR_STOP1 | UARTLCR_DLAB |
| 3728 | unsigned const baud = 57600 |
| 3729 | unsigned uart_div = 12000000 / 16 / baud |
| 3730 | UART0_DLHR = (uart_div >> 8) & 0xff |
| 3731 | UART0_DLLR = uart_div & 0xff |
| 3732 | UART0_LCR = UARTLCR_WLEN_8 | UARTLCR_STOP1 |
| 3733 | UART0_FCR = UARTFCR_UUE | UARTFCR_FE | UARTFCR_RFLS | UARTFCR_TFLS |
| 3734 | #endif |
| 3735 | #endif |
| 3736 | |
| 3737 | #endif |
| 3738 |
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