Date:2010-05-28 04:26:56 (10 years 3 months ago)
Author:Carlos Camargo
Commit:01e672d02826a9532fe64a875f07c5bf14fb3d2b
Message:Fixing plasma files.. Now works :)

Files: Examples/sram/logic/Makefile (1 diff)
plasma/bootldr/bootldr.c (1 diff)
plasma/logic/Makefile (1 diff)
plasma/logic/code.txt (1 diff)
plasma/logic/control.vhd (3 diffs)
plasma/logic/mlite_cpu.vhd (1 diff)
plasma/logic/mlite_pack.vhd (4 diffs)
plasma/logic/plasma.vhd (5 diffs)
plasma/logic/plasma_TB.vhd (2 diffs)
plasma/logic/ram_image.vhd (5 diffs)
plasma/logic/ram_xilinx.vhd (5 diffs)
plasma/logic/reg_bank.vhd (1 diff)
plasma/logic/simulation/output.txt (0 diffs)
plasma/logic/simulation/wave.do (2 diffs)
plasma/logic/uart.vhd (6 diffs)

Change Details

Examples/sram/logic/Makefile
8989    cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
9090
9191iversim:
92    $(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
93# $(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) build/project.v $(SIM_SRC) -s $(DESIGN)_TB
92    $(IVERILOG) -Wall -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
9493    vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
9594    gtkwave simulation/$(DESIGN)_TB.vcd&
9695
plasma/bootldr/bootldr.c
122122
123123   DdrInit(); //Harmless if SDRAM instead of DDR
124124
125   puts("\n1233456Greetings from the bootloader ");
126   puts(__DATE__);
127   puts(" ");
128   puts(__TIME__);
125   puts("\nSAKC bootloader ");
129126   puts(":\n");
130127   MemoryWrite(FLASH_BASE, 0xff); //read mode
131128   if((MemoryRead(GPIOA_IN) & 1) && (MemoryRead(FLASH_BASE) & 0xffff) == 0x3c1c)
plasma/logic/Makefile
11DESIGN = plasma
22PINS = $(DESIGN).ucf
33DEVICE = xc3s500e-VQ100-4
4#DEVICE = xc3s250e-fg320-4
4#DEVICE = xc3s500e-fg320-4
55BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
66                  -g CRC:enable -g StartUpClk:CCLK
77SIM_CMD = /opt/cad/modeltech/bin/vsim
88SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
99SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
1010
11SRC_HDL = plasma.vhd ram_image.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd mlite_cpu.vhd pc_next.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd
11SRC_HDL = mlite_pack.vhd plasma.vhd ram_image.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd mlite_cpu.vhd pc_next.vhd pipeline.vhd reg_bank.vhd uart.vhd
1212
1313all: bits
1414
plasma/logic/code.txt
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plasma/logic/control.vhd
136136         c_source := C_FROM_MULT;
137137         mult_function := MULT_READ_HI;
138138
139      when "010001" => --FTHI s->hi=r[rs];
139      when "010001" => --MTHI s->hi=r[rs];
140140         mult_function := MULT_WRITE_HI;
141141
142142      when "010010" => --MFLO r[rd]=s->lo;
...... 
240240      --when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
241241      --when "00011" => --BGEZL lbranch=r[rs]>=0;
242242
243      when others =>
244      end case;
243      when others =>
244      end case;
245245
246246   when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
247247      c_source := C_FROM_PC_PLUS4;
...... 
479479end process;
480480
481481end; --logic
482
plasma/logic/mlite_cpu.vhd
7272use ieee.std_logic_unsigned.all;
7373
7474entity mlite_cpu is
75   generic(memory_type : string := "XILINX_16X";
75   generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
7676           mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
7777           shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
7878           alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
plasma/logic/mlite_pack.vhd
107107                         ) return std_logic_vector;
108108   function bv_inc(a : in std_logic_vector
109109                  ) return std_logic_vector;
110
111   -- For Altera
112   COMPONENT lpm_ram_dp
113      generic (
114         LPM_WIDTH : natural; -- MUST be greater than 0
115         LPM_WIDTHAD : natural; -- MUST be greater than 0
116         LPM_NUMWORDS : natural := 0;
117         LPM_INDATA : string := "REGISTERED";
118         LPM_OUTDATA : string := "REGISTERED";
119         LPM_RDADDRESS_CONTROL : string := "REGISTERED";
120         LPM_WRADDRESS_CONTROL : string := "REGISTERED";
121         LPM_FILE : string := "UNUSED";
122         LPM_TYPE : string := "LPM_RAM_DP";
123         USE_EAB : string := "OFF";
124         INTENDED_DEVICE_FAMILY : string := "UNUSED";
125         RDEN_USED : string := "TRUE";
126         LPM_HINT : string := "UNUSED");
127      port (
128         RDCLOCK : in std_logic := '0';
129         RDCLKEN : in std_logic := '1';
130         RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
131         RDEN : in std_logic := '1';
132         DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
133         WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
134         WREN : in std_logic;
135         WRCLOCK : in std_logic := '0';
136         WRCLKEN : in std_logic := '1';
137         Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
138   END COMPONENT;
139
140   -- For Altera
141   component LPM_RAM_DQ
142      generic (
143         LPM_WIDTH : natural; -- MUST be greater than 0
144         LPM_WIDTHAD : natural; -- MUST be greater than 0
145         LPM_NUMWORDS : natural := 0;
146         LPM_INDATA : string := "REGISTERED";
147         LPM_ADDRESS_CONTROL: string := "REGISTERED";
148         LPM_OUTDATA : string := "REGISTERED";
149         LPM_FILE : string := "UNUSED";
150         LPM_TYPE : string := "LPM_RAM_DQ";
151         USE_EAB : string := "OFF";
152         INTENDED_DEVICE_FAMILY : string := "UNUSED";
153         LPM_HINT : string := "UNUSED");
154        port (
155         DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
156         ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
157         INCLOCK : in std_logic := '0';
158         OUTCLOCK : in std_logic := '0';
159         WE : in std_logic;
160         Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
161   end component;
162
110163   -- For Xilinx
111164   component RAM16X1D
112165      -- synthesis translate_off
...... 
309362   end component; --cache
310363
311364   component ram
365      generic(memory_type : string := "DEFAULT");
312366      port(clk : in std_logic;
313367           enable : in std_logic;
314368           write_byte_enable : in std_logic_vector(3 downto 0);
315           address : in std_logic_vector(10 downto 0);
369           address : in std_logic_vector(31 downto 2);
316370           data_write : in std_logic_vector(31 downto 0);
317371           data_read : out std_logic_vector(31 downto 0));
318372   end component; --ram
319373
320374   component uart
375      generic(log_file : string := "UNUSED");
321376      port(clk : in std_logic;
322377           reset : in std_logic;
323378           cs : in std_logic;
...... 
326381           data_out : out std_logic_vector(7 downto 0);
327382           uart_read : in std_logic;
328383           uart_write : out std_logic;
329           addr : in std_logic_vector(3 downto 0));
384           busy_write : out std_logic;
385           data_avail : out std_logic);
330386   end component; --uart
331387
332388   component eth_dma
...... 
357413   end component; --eth_dma
358414
359415   component plasma
360      generic(memory_type : string := "XILINX_X16");
361      port(clk : in std_logic;
362           reset : in std_logic;
363           U_TxD : out std_logic;
364           U_RxD : in std_logic;
416      generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
417              log_file : string := "UNUSED");
418      port(clk_in : in std_logic;
419           rst_in : in std_logic;
420           uart_write : out std_logic;
421           uart_read : in std_logic;
422
365423           addr : in std_logic_vector(12 downto 0);
366424           sram_data : in std_logic_vector(7 downto 0);
367425           nwe : in std_logic;
368426           noe : in std_logic;
369427           ncs : in std_logic;
370           led : out std_logic
371      );
428           led : out std_logic);
372429   end component; --plasma
373430
374431   component ddr_ctrl
plasma/logic/plasma.vhd
1717-- 0x20000000 Uart Read
1818-- 0x20000010 IRQ Mask
1919-- 0x20000020 IRQ Status
20-- 0x20000030 Peripheric 1
21-- 0x20000040 Peripheric 2
22-- 0x20000050 Peripheric 3
23-- 0x20000060 Peripheric 4
24-- IRQ bits:
25-- 1 ^UartWriteBusy
26-- 0 UartDataAvailable
2027---------------------------------------------------------------------
2128library ieee;
2229use ieee.std_logic_1164.all;
2330use work.mlite_pack.all;
24library UNISIM;
25use UNISIM.vcomponents.all;
2631
2732entity plasma is
28   generic(memory_type : string := "XILINX_16X");
29   port(clk : in std_logic;
30        reset : in std_logic;
31        U_TxD : out std_logic;
32        U_RxD : in std_logic;
33   generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
34           log_file : string := "UNUSED");
35   port(clk_in : in std_logic;
36        rst_in : in std_logic;
37        uart_write : out std_logic;
38        uart_read : in std_logic;
3339        addr : in std_logic_vector(12 downto 0);
3440        sram_data : in std_logic_vector(7 downto 0);
3541        nwe : in std_logic;
...... 
4346end; --entity plasma
4447
4548architecture logic of plasma is
46   signal address_next : std_logic_vector(31 downto 0);
49   signal reset : std_logic;
50   signal clk : std_logic;
51   signal address_next : std_logic_vector(31 downto 2);
4752   signal byte_we_next : std_logic_vector(3 downto 0);
4853   signal cpu_address : std_logic_vector(31 downto 0);
4954   signal cpu_byte_we : std_logic_vector(3 downto 0);
...... 
5257   signal cpu_pause : std_logic;
5358
5459   signal data_read_uart : std_logic_vector(7 downto 0);
60   signal data_read_pic : std_logic_vector(7 downto 0);
61   signal write_enable : std_logic;
62   signal mem_busy : std_logic;
5563
64   signal cs_pher : std_logic;
5665   signal cs_uart : std_logic;
66   signal cs_pic : std_logic;
67   signal cs_p1 : std_logic;
68   signal cs_p2 : std_logic;
69   signal cs_p3 : std_logic;
70   signal cs_p4 : std_logic;
71
5772   signal uart_write_busy : std_logic;
5873   signal uart_data_avail : std_logic;
5974   signal irq_mask_reg : std_logic_vector(7 downto 0);
...... 
6176   signal irq : std_logic;
6277
6378   signal cs_ram : std_logic;
79   signal ram_byte_we : std_logic_vector(3 downto 0);
6480   signal ram_address : std_logic_vector(31 downto 2);
81   signal ram_data_w : std_logic_vector(31 downto 0);
6582   signal ram_data_r : std_logic_vector(31 downto 0);
6683
67   signal nreset : std_logic;
6884
69begin --architecture
85begin
86--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
87-- PROCESSOR
88--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
89   led <= not(rst_in);
90   reset <= not(rst_in);
91
92   clk_div: process(reset, clk, clk_in)
93   begin
94      if reset = '1' then
95         clk <= '0';
96      elsif rising_edge(clk_in) then
97         clk <= not clk;
98      end if;
99   end process;
100
101   write_enable <= '1' when cpu_byte_we /= "0000" else '0';
102   cpu_pause <= (uart_write_busy and cs_uart and write_enable);
103
70104--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
71105-- PROCESSOR
72106--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
...... 
74108      generic map (memory_type => memory_type)
75109      PORT MAP (
76110         clk => clk,
77         reset_in => nreset,
111         reset_in => reset,
78112         intr_in => irq,
79
80         address_next => address_next(31 downto 2), --before rising_edge(clk)
113         address_next => address_next, --before rising_edge(clk)
81114         byte_we_next => byte_we_next,
82
83115         address => cpu_address(31 downto 2), --after rising_edge(clk)
84116         byte_we => cpu_byte_we,
85117         data_w => cpu_data_w,
86118         data_r => cpu_data_r,
87119         mem_pause => cpu_pause);
88120
121--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
122-- ADDRESS DECODER
123--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
124   cpu_address(1 downto 0) <= "00";
125
126   addr_decoder: process (cpu_address)
127     variable addr_dec : std_logic_vector(6 downto 0);
128   begin
129     addr_dec := cpu_address(30 downto 28) & cpu_address(7 downto 4);
130     case addr_dec is
131       when "0100000" => cs_uart <= '1'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
132       when "0100001" => cs_uart <= '0'; cs_pic <= '1'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
133       when "0100010" => cs_uart <= '0'; cs_pic <= '1'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
134       when "0100011" => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '1'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
135       when "0100100" => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '1'; cs_p3 <= '0'; cs_p4 <= '0';
136       when "0100101" => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '1'; cs_p4 <= '0';
137       when "0100110" => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '1';
138       when others => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
139     end case;
140   end process;
141
142--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
143-- BUS MULTIPLEXOR
144--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
145
146  bus_mux: process (cpu_address, ram_data_r, data_read_uart, data_read_pic)
147     variable bus_dec : std_logic_vector(6 downto 0);
148  begin
149     bus_dec := cpu_address(30 downto 28) & cpu_address(7 downto 4);
150     case bus_dec is
151       when "000----" => cpu_data_r <= ram_data_r;
152       when "0100000" => cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
153       when "0100001" => cpu_data_r <= ZERO(31 downto 8) & data_read_pic;
154       when "0100010" => cpu_data_r <= ZERO(31 downto 8) & data_read_pic;
155       when "0100011" => cpu_data_r <= ZERO;
156       when "0100100" => cpu_data_r <= ZERO;
157       when "0100101" => cpu_data_r <= ZERO;
158       when "0100110" => cpu_data_r <= ZERO;
159       when others => cpu_data_r <= ZERO;
160    end case;
161  end process;
162
163--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
164-- PIC
165--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
166   pic_proc: process(clk, reset, cpu_address, cs_pic, cpu_pause, cpu_byte_we, irq_mask_reg, irq_status, cpu_data_w)
167   begin
168
169     irq_status <= ZERO(5 downto 0) & not uart_write_busy & uart_data_avail;
170
171     if cs_pic = '1' and cpu_byte_we = "0000" then
172       case cpu_address(5 downto 4) is
173         when "01" => data_read_pic <= irq_mask_reg;
174         when "10" => data_read_pic <= irq_status;
175         when others => data_read_pic <= ZERO(7 downto 0);
176       end case;
177     end if;
178
179     if reset = '1' then
180       irq_mask_reg <= ZERO(7 downto 0);
181     elsif rising_edge(clk) then
182       if cpu_pause = '0' then
183         if cs_pic = '1' and cpu_byte_we = "1111" then
184           if cpu_address(6 downto 4) = "001" then
185             irq_mask_reg <= cpu_data_w(7 downto 0);
186           end if;
187         end if;
188       end if;
189     end if;
190
191    if (irq_status and irq_mask_reg) /= ZERO(7 downto 0) then
192      irq <= '1';
193    else
194      irq <= '0';
195    end if;
196
197   end process;
198
199
200--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
201-- RAM
202--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
203   cs_ram <= '1' when address_next(30 downto 28) = "000" else '0';
204   ram_address(31 downto 2) <= ZERO(31 downto 13) & address_next(12 downto 2);
205
89206   u2_ram: ram
207      generic map (memory_type => memory_type)
90208      port map (
91209         clk => clk,
92210         enable => cs_ram,
93211         write_byte_enable => byte_we_next,
94         address => ram_address(12 downto 2),
212         address => ram_address,
95213         data_write => cpu_data_w,
96214         data_read => ram_data_r);
97215
216--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
217-- UART
218--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
219
98220   u3_uart: uart
221      generic map (log_file => log_file)
99222      port map(
100223         clk => clk,
101         reset => nreset,
224         reset => reset,
102225         cs => cs_uart,
103226         nRdWr => cpu_byte_we(0),
104227         data_in => cpu_data_w(7 downto 0),
105228         data_out => data_read_uart,
106         uart_read => U_RxD,
107         uart_write => U_TxD,
108         addr => cpu_address(7 downto 4));
109
110   cpu_pause <= '0'; --(uart_write_busy and enable_uart and write_enable) or --UART busy
111   ram_address <= ZERO(31 downto 13) & (address_next(12)) & address_next(11 downto 2);
112   cpu_address(1 downto 0) <= "00";
113   address_next(1 downto 0) <= "00";
114
115   nreset <= not(reset);
116
117
118   led <= not(reset);
119
120   addr_dec: process (cpu_address(30 downto 4))
121   begin
122     if (cpu_address(30 downto 28) = "000") then
123       cs_ram <= '1';
124       cs_uart <= '0';
125     elsif ( (cpu_address(30 downto 28) = "010") and ( (cpu_address(11 downto 8) = "0000") )) then
126       cs_ram <= '0';
127       cs_uart <= '1';
128     else
129       cs_ram <= '0';
130       cs_uart <= '0';
131     end if;
132   end process;
133
134   misc_proc: process(clk, nreset, cpu_address,
135      ram_data_r, data_read_uart, cpu_pause,
136      irq_mask_reg, irq_status, cpu_data_w)
137   begin
138      case cpu_address(30 downto 28) is
139      when "000" => --internal RAM
140         cpu_data_r <= ram_data_r;
141      when "010" => --misc
142         case cpu_address(6 downto 4) is
143         when "000" => --uart
144            cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
145         when "010" => --uart
146            cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
147         when others =>
148            cpu_data_r <= ZERO;
149         end case;
150      when others =>
151         cpu_data_r <= ZERO;
152      end case;
153    end process;
154
155
156
229         uart_read => uart_read,
230         uart_write => uart_write,
231         busy_write => uart_write_busy,
232         data_avail => uart_data_avail);
157233
158234end; --architecture logic
159235
plasma/logic/plasma_TB.vhd
2121   constant memory_type : string :=
2222   "TRI_PORT_X";
2323
24   signal clk : std_logic := '1';
25   signal reset : std_logic := '0';
24   signal clk_in : std_logic := '1';
25   signal rst_in : std_logic := '0';
2626   signal addr : std_logic_vector(12 downto 0);
2727   signal sram_data : std_logic_vector(7 downto 0);
2828   signal nwe : std_logic;
...... 
3131   signal led : std_logic;
3232
3333   signal TxD : std_logic;
34   signal RxD : std_logic;
35
3436begin --architecture
35   clk <= not clk after 50 ns;
36   reset <= '1' after 500 ns;
37   clk_in <= not clk_in after 50 ns;
38   rst_in <= '1' after 500 ns;
39   RxD <= '1';
3740
3841
3942   u1_plasma: plasma
4043      generic map (memory_type => memory_type)
4144      PORT MAP (
42         clk => clk,
43         reset => reset,
44         U_RxD => TxD,
45         U_TxD => TxD,
45         clk_in => clk_in,
46         rst_in => rst_in,
47         uart_read => RxD,
48         uart_write => TxD,
4649         addr => addr,
4750         sram_data => sram_data,
4851         nwe => nwe,
plasma/logic/ram_image.vhd
2727use UNISIM.vcomponents.all;
2828
2929entity ram is
30   generic(memory_type : string := "DEFAULT");
3031   port(clk : in std_logic;
3132        enable : in std_logic;
3233        write_byte_enable : in std_logic_vector(3 downto 0);
33        address : in std_logic_vector(10 downto 0);
34        address : in std_logic_vector(31 downto 2);
3435        data_write : in std_logic_vector(31 downto 0);
3536        data_read : out std_logic_vector(31 downto 0));
3637end; --entity ram
...... 
107108   port map (
108109      DO => data_read(31 downto 24),
109110      DOP => open,
110      ADDR => address(10 downto 0),
111      ADDR => address(12 downto 2),
111112      CLK => clk,
112113      DI => data_write(31 downto 24),
113114      DIP => ZERO(0 downto 0),
...... 
184185   port map (
185186      DO => data_read(23 downto 16),
186187      DOP => open,
187      ADDR => address(10 downto 0),
188      ADDR => address(12 downto 2),
188189      CLK => clk,
189190      DI => data_write(23 downto 16),
190191      DIP => ZERO(0 downto 0),
...... 
261262   port map (
262263      DO => data_read(15 downto 8),
263264      DOP => open,
264      ADDR => address(10 downto 0),
265      ADDR => address(12 downto 2),
265266      CLK => clk,
266267      DI => data_write(15 downto 8),
267268      DIP => ZERO(0 downto 0),
...... 
338339   port map (
339340      DO => data_read(7 downto 0),
340341      DOP => open,
341      ADDR => address(10 downto 0),
342      ADDR => address(12 downto 2),
342343      CLK => clk,
343344      DI => data_write(7 downto 0),
344345      DIP => ZERO(0 downto 0),
plasma/logic/ram_xilinx.vhd
2727use UNISIM.vcomponents.all;
2828
2929entity ram is
30   generic(memory_type : string := "DEFAULT");
3031   port(clk : in std_logic;
3132        enable : in std_logic;
3233        write_byte_enable : in std_logic_vector(3 downto 0);
33        address : in std_logic_vector(10 downto 0);
34        address : in std_logic_vector(31 downto 2);
3435        data_write : in std_logic_vector(31 downto 0);
3536        data_read : out std_logic_vector(31 downto 0));
3637end; --entity ram
...... 
107108   port map (
108109      DO => data_read(31 downto 24),
109110      DOP => open,
110      ADDR => address(10 downto 0),
111      ADDR => address(12 downto 2),
111112      CLK => clk,
112113      DI => data_write(31 downto 24),
113114      DIP => ZERO(0 downto 0),
...... 
184185   port map (
185186      DO => data_read(23 downto 16),
186187      DOP => open,
187      ADDR => address(10 downto 0),
188      ADDR => address(12 downto 2),
188189      CLK => clk,
189190      DI => data_write(23 downto 16),
190191      DIP => ZERO(0 downto 0),
...... 
261262   port map (
262263      DO => data_read(15 downto 8),
263264      DOP => open,
264      ADDR => address(10 downto 0),
265      ADDR => address(12 downto 2),
265266      CLK => clk,
266267      DI => data_write(15 downto 8),
267268      DIP => ZERO(0 downto 0),
...... 
338339   port map (
339340      DO => data_read(7 downto 0),
340341      DOP => open,
341      ADDR => address(10 downto 0),
342      ADDR => address(12 downto 2),
342343      CLK => clk,
343344      DI => data_write(7 downto 0),
344345      DIP => ZERO(0 downto 0),
plasma/logic/reg_bank.vhd
235235      data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
236236   end generate; --xilinx_16x1d
237237
238
239   -- Option #4
240   -- Altera LPM_RAM_DP
241   altera_mem:
242   if memory_type = "ALTERA_LPM" generate
243      signal clk_delayed : std_logic;
244      signal addr_reg : std_logic_vector(4 downto 0);
245      signal data_reg : std_logic_vector(31 downto 0);
246      signal q1 : std_logic_vector(31 downto 0);
247      signal q2 : std_logic_vector(31 downto 0);
248   begin
249      -- Altera dual port RAMs must have the addresses registered (sampled
250      -- at the rising edge). This is very unfortunate.
251      -- Therefore, the dual port RAM read clock must delayed so that
252      -- the read address signal can be sent from the mem_ctrl block.
253      -- This solution also delays the how fast the registers are read so the
254      -- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).
255
256      clk_delayed <= not clk; --Could be delayed by 1/4 clock cycle instead
257      dpram_bypass: process(clk, addr_write, reg_dest_new)
258      begin
259         if rising_edge(clk) and write_enable = '1' then
260            addr_reg <= addr_write;
261            data_reg <= reg_dest_new;
262         end if;
263      end process; --dpram_bypass
264
265      -- Bypass dpram if reading what was just written (Altera limitation)
266      data_out1 <= q1 when addr_read1 /= addr_reg else data_reg;
267      data_out2 <= q2 when addr_read2 /= addr_reg else data_reg;
268
269      lpm_ram_dp_component1 : lpm_ram_dp
270      generic map (
271         LPM_WIDTH => 32,
272         LPM_WIDTHAD => 5,
273         --LPM_NUMWORDS => 0,
274         LPM_INDATA => "REGISTERED",
275         LPM_OUTDATA => "UNREGISTERED",
276         LPM_RDADDRESS_CONTROL => "REGISTERED",
277         LPM_WRADDRESS_CONTROL => "REGISTERED",
278         LPM_FILE => "UNUSED",
279         LPM_TYPE => "LPM_RAM_DP",
280         USE_EAB => "ON",
281         INTENDED_DEVICE_FAMILY => "UNUSED",
282         RDEN_USED => "FALSE",
283         LPM_HINT => "UNUSED")
284      port map (
285         RDCLOCK => clk_delayed,
286         RDCLKEN => '1',
287         RDADDRESS => addr_read1,
288         RDEN => '1',
289         DATA => reg_dest_new,
290         WRADDRESS => addr_write,
291         WREN => write_enable,
292         WRCLOCK => clk,
293         WRCLKEN => '1',
294         Q => q1);
295      lpm_ram_dp_component2 : lpm_ram_dp
296      generic map (
297         LPM_WIDTH => 32,
298         LPM_WIDTHAD => 5,
299         --LPM_NUMWORDS => 0,
300         LPM_INDATA => "REGISTERED",
301         LPM_OUTDATA => "UNREGISTERED",
302         LPM_RDADDRESS_CONTROL => "REGISTERED",
303         LPM_WRADDRESS_CONTROL => "REGISTERED",
304         LPM_FILE => "UNUSED",
305         LPM_TYPE => "LPM_RAM_DP",
306         USE_EAB => "ON",
307         INTENDED_DEVICE_FAMILY => "UNUSED",
308         RDEN_USED => "FALSE",
309         LPM_HINT => "UNUSED")
310      port map (
311         RDCLOCK => clk_delayed,
312         RDCLKEN => '1',
313         RDADDRESS => addr_read2,
314         RDEN => '1',
315         DATA => reg_dest_new,
316         WRADDRESS => addr_write,
317         WREN => write_enable,
318         WRCLOCK => clk,
319         WRCLKEN => '1',
320         Q => q2);
321   end generate; --altera_mem
322
238323end; --architecture ram_block
plasma/logic/simulation/output.txt
plasma/logic/simulation/wave.do
11onerror {resume}
22quietly WaveActivateNextPane {} 0
3add wave -noupdate -format Logic /tbench/clk
4add wave -noupdate -format Logic /tbench/reset
5add wave -noupdate -format Logic /tbench/pause1
6add wave -noupdate -format Logic /tbench/pause2
7add wave -noupdate -format Logic /tbench/pause
3add wave -noupdate -format Logic /tbench/clk_in
4add wave -noupdate -format Logic /tbench/rst_in
5add wave -noupdate -format Literal /tbench/addr
6add wave -noupdate -format Literal /tbench/sram_data
7add wave -noupdate -format Logic /tbench/nwe
8add wave -noupdate -format Logic /tbench/noe
9add wave -noupdate -format Logic /tbench/ncs
10add wave -noupdate -format Logic /tbench/led
11add wave -noupdate -format Logic /tbench/txd
12add wave -noupdate -format Logic /tbench/rxd
13add wave -noupdate -format Literal /tbench/u1_plasma/address_next
14add wave -noupdate -format Literal /tbench/u1_plasma/byte_we_next
15add wave -noupdate -format Literal /tbench/u1_plasma/cpu_address
816add wave -noupdate -format Literal /tbench/u1_plasma/cpu_byte_we
9add wave -noupdate -format Literal -expand /tbench/u1_plasma/byte_we_next
10add wave -noupdate -format Literal -radix hexadecimal /tbench/u1_plasma/cpu_address
11add wave -noupdate -format Literal -radix hexadecimal /tbench/u1_plasma/address_next
12add wave -noupdate -format Literal -radix hexadecimal /tbench/u1_plasma/cpu_data_w
13add wave -noupdate -format Literal -radix hexadecimal /tbench/u1_plasma/cpu_data_r
14add wave -noupdate -format Logic /tbench/u1_plasma/cs_ram
15add wave -noupdate -format Logic /tbench/u1_plasma/cs_uart
16add wave -noupdate -format Literal /tbench/u1_plasma/u3_uart/addr
17add wave -noupdate -format Logic /tbench/u1_plasma/u3_uart/enable_read
18add wave -noupdate -format Literal /tbench/u1_plasma/u3_uart/addr
19add wave -noupdate -format Logic /tbench/u1_plasma/u3_uart/enable_write
20add wave -noupdate -format Logic /tbench/u1_plasma/u_txd
21add wave -noupdate -format Logic /tbench/u1_plasma/u3_uart/busy_write
22add wave -noupdate -format Logic /tbench/u1_plasma/u_rxd
23add wave -noupdate -format Logic /tbench/u1_plasma/u3_uart/data_avail
24add wave -noupdate -format Literal -radix hexadecimal /tbench/u1_plasma/u3_uart/data_in
25add wave -noupdate -format Literal -radix hexadecimal /tbench/u1_plasma/u3_uart/data_out
17add wave -noupdate -format Literal /tbench/u1_plasma/cpu_data_w
18add wave -noupdate -format Literal /tbench/u1_plasma/cpu_data_r
19add wave -noupdate -format Literal /tbench/u1_plasma/data_read_uart
20add wave -noupdate -format Literal /tbench/u1_plasma/data_read_pic
2621TreeUpdate [SetDefaultTree]
27WaveRestoreCursors {{Cursor 1} {999785196 ps} 0}
28configure wave -namecolwidth 285
29configure wave -valuecolwidth 40
22WaveRestoreCursors {{Cursor 1} {999999246 ps} 0}
23configure wave -namecolwidth 150
24configure wave -valuecolwidth 100
3025configure wave -justifyvalue left
3126configure wave -signalnamewidth 0
3227configure wave -snapdistance 10
...... 
3833configure wave -griddelta 40
3934configure wave -timeline 0
4035update
41WaveRestoreZoom {0 ps} {1050 us}
36WaveRestoreZoom {999999050 ps} {1000000050 ps}
plasma/logic/uart.vhd
1919use work.mlite_pack.all;
2020
2121entity uart is
22   generic(log_file : string := "UNUSED");
2223   port(clk : in std_logic;
2324        reset : in std_logic;
2425        cs : in std_logic;
...... 
2728        data_out : out std_logic_vector(7 downto 0);
2829        uart_read : in std_logic;
2930        uart_write : out std_logic;
30        addr : in std_logic_vector(3 downto 0)
31       );
31        busy_write : out std_logic;
32        data_avail : out std_logic);
3233end; --entity uart
3334
3435architecture logic of uart is
...... 
4445   signal uart_read2 : std_logic;
4546   signal enable_read : std_logic;
4647   signal enable_write : std_logic;
47   signal busy_write : std_logic;
48   signal data_avail : std_logic;
49   signal data_out_sig : std_logic_vector(7 downto 0);
50
5148
5249begin
5350
54interface_proc: process(cs, nRdWr, addr, data_out_sig, busy_write, data_avail, data_save_reg)
51interface_proc: process(cs, nRdWr)
5552begin
5653  if cs = '1' then
5754    if nRdWr = '1' then
5855      enable_read <= '0';
5956      enable_write <= '1';
60      data_out_sig <= "00000000";
6157    else
6258      enable_read <= '1';
6359      enable_write <= '0';
64      case addr(3 downto 0) is
65      when "0000" =>
66        data_out_sig <= data_save_reg(7 downto 0);
67      when "0010" =>
68        data_out_sig(7 downto 0) <= "000000" & busy_write & data_avail;
69      when others =>
70        data_out_sig <= "00000000";
71      end case;
7260    end if;
7361  else
7462    enable_read <= '0';
7563    enable_write <= '0';
76    data_out_sig <= "00000000";
7764  end if;
78  data_out <= data_out_sig;
7965end process;
8066
81
8267uart_proc: process(clk, reset, enable_read, enable_write, data_in,
8368                   data_write_reg, bits_write_reg, delay_write_reg,
8469                   data_read_reg, bits_read_reg, delay_read_reg,
...... 
8671                   busy_write_sig, uart_read)
8772   constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
8873-- "0100011110"; --33MHz/2/57600Hz = 0x11e
89      "1101100100"; --50MHz/57600Hz = 0x364
74-- "1101100100"; --50MHz/57600Hz = 0x364
75      "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
9076-- "0011011001"; --12.5MHz/57600Hz = 0xd9
9177-- "0000000100"; --for debug (shorten read_value_reg)
9278begin
...... 
10590   elsif rising_edge(clk) then
10691
10792      --Write UART
108    if bits_write_reg = "0000" then --nothing left to write?
109       if enable_write = '1' then
110          delay_write_reg <= ZERO(9 downto 0); --delay before next bit
111          bits_write_reg <= "1010"; --number of bits to write
112          data_write_reg <= data_in & '0'; --remember data & start bit
113       end if;
114    else
115       if delay_write_reg /= COUNT_VALUE then
116          delay_write_reg <= delay_write_reg + 1; --delay before next bit
117       else
118          delay_write_reg <= ZERO(9 downto 0); --reset delay
119          bits_write_reg <= bits_write_reg - 1; --bits left to write
120          data_write_reg <= '1' & data_write_reg(8 downto 1);
121       end if;
122    end if;
123     --Average uart_read signal
124    if uart_read = '1' then
125       if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
126          read_value_reg <= read_value_reg + 1;
127       end if;
128    else
129       if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
130          read_value_reg <= read_value_reg - 1;
131       end if;
132    end if;
133     --Read UART
134    if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
135       if bits_read_reg = "0000" then --nothing left to read?
136          if uart_read2 = '0' then --wait for start bit
137             delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
138             bits_read_reg <= "1001"; --bits left to read
139          end if;
140       else
141          delay_read_reg <= COUNT_VALUE; --initialize delay
142          bits_read_reg <= bits_read_reg - 1; --bits left to read
143          data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
144       end if;
145    else
146       delay_read_reg <= delay_read_reg - 1; --delay
147    end if;
148     --Control character buffer
149    if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
150       if data_save_reg(8) = '0' or
151             (enable_read = '1' and data_save_reg(17) = '0') then
152          --Empty buffer
153          data_save_reg(8 downto 0) <= '1' & data_read_reg;
154       else
155          --Second character in buffer
156          data_save_reg(17 downto 9) <= '1' & data_read_reg;
157          if enable_read = '1' then
158             data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
159          end if;
160       end if;
161    elsif enable_read = '1' then
162       data_save_reg(17) <= '0'; --data_available
163       data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
164    end if;
165 end if; --rising_edge(clk)
93      if bits_write_reg = "0000" then --nothing left to write?
94         if enable_write = '1' then
95            delay_write_reg <= ZERO(9 downto 0); --delay before next bit
96            bits_write_reg <= "1010"; --number of bits to write
97            data_write_reg <= data_in & '0'; --remember data & start bit
98         end if;
99      else
100         if delay_write_reg /= COUNT_VALUE then
101            delay_write_reg <= delay_write_reg + 1; --delay before next bit
102         else
103            delay_write_reg <= ZERO(9 downto 0); --reset delay
104            bits_write_reg <= bits_write_reg - 1; --bits left to write
105            data_write_reg <= '1' & data_write_reg(8 downto 1);
106         end if;
107      end if;
108
109      --Average uart_read signal
110      if uart_read = '1' then
111         if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
112            read_value_reg <= read_value_reg + 1;
113         end if;
114      else
115         if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
116            read_value_reg <= read_value_reg - 1;
117         end if;
118      end if;
119
120      --Read UART
121      if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
122         if bits_read_reg = "0000" then --nothing left to read?
123            if uart_read2 = '0' then --wait for start bit
124               delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
125               bits_read_reg <= "1001"; --bits left to read
126            end if;
127         else
128            delay_read_reg <= COUNT_VALUE; --initialize delay
129            bits_read_reg <= bits_read_reg - 1; --bits left to read
130            data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
131         end if;
132      else
133         delay_read_reg <= delay_read_reg - 1; --delay
134      end if;
135
136      --Control character buffer
137      if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
138         if data_save_reg(8) = '0' or
139               (enable_read = '1' and data_save_reg(17) = '0') then
140            --Empty buffer
141            data_save_reg(8 downto 0) <= '1' & data_read_reg;
142         else
143            --Second character in buffer
144            data_save_reg(17 downto 9) <= '1' & data_read_reg;
145            if enable_read = '1' then
146               data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
147            end if;
148         end if;
149      elsif enable_read = '1' then
150         data_save_reg(17) <= '0'; --data_available
151         data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
152      end if;
153   end if; --rising_edge(clk)
166154
167155   uart_write <= data_write_reg(0);
168156   if bits_write_reg /= "0000"
157-- Comment out the following line for full UART simulation (much slower)
158   and log_file = "UNUSED"
169159   then
170160      busy_write_sig <= '1';
171161   else
...... 
173163   end if;
174164   busy_write <= busy_write_sig;
175165   data_avail <= data_save_reg(8);
166   data_out <= data_save_reg(7 downto 0);
176167
177168end process; --uart_proc
169
178170end; --architecture logic

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