Date:2010-04-29 19:45:56 (9 years 8 months ago)
Author:Carlos Camargo
Commit:0348078440d34ea1b8805e18314e9f3d12a9e2f8
Message:Adding simulation files to blink example

Files: Examples/blink/logic/Makefile (2 diffs)
Examples/blink/logic/blink.v (1 diff)
Examples/blink/logic/blink_TB.v (1 diff)
Examples/blink/logic/simulation/blink_TB.do (1 diff)
Examples/blink/logic/simulation/wave.do (1 diff)

Change Details

Examples/blink/logic/Makefile
44BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
55                  -g CRC:enable -g StartUpClk:CCLK
66
7SIM_CMD = /opt/cad/modeltech/bin/vsim
7SIM_CMD = vsim
88SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
9#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
109SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
1110SAKC_IP = 192.168.254.101
1211
...... 
1817
1918clean:
2019    rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
21    rm *.bit
20    rm -f *.bit
2221
23clean-build: clean
24    rm -rf build
25
26cleanall: clean
27    rm -rf build $(DESIGN).bit
22cleanall: clean
23    rm -rf build simulation/work simulation/transcript simulation/vsim.wlf
2824
2925bits: $(DESIGN).bit
3026
Examples/blink/logic/blink.v
11`timescale 1ns / 1ps
22module blink(clk, reset, led);
3  parameter B = (7);
4
53  input clk, reset;
64  output led;
75
Examples/blink/logic/blink_TB.v
1`timescale 1ns / 1ps
2
3module blink_TB_v;
4
5   reg clk;
6   reg reset;
7   wire led;
8
9   blink uut ( .clk(clk), .reset(reset), .led(led));
10
11   parameter PERIOD = 20;
12   parameter real DUTY_CYCLE = 0.5;
13   parameter OFFSET = 0;
14   parameter TSET = 3;
15   parameter THLD = 3;
16   parameter NWS = 3;
17
18   event reset_trigger;
19
20
21   initial begin // Initialize Inputs
22      clk = 0; reset = 0;
23   end
24
25   initial begin // Process for clk
26     #OFFSET;
27     forever
28       begin
29         clk = 1'b0;
30         #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
31         #(PERIOD*DUTY_CYCLE);
32       end
33   end
34
35   initial begin // Reset the system, Start the image capture process
36      forever begin
37        @ (reset_trigger);
38        @ (negedge clk);
39        reset = 1;
40        @ (negedge clk);
41        reset = 0;
42      end
43   end
44
45
46   initial begin: TEST_CASE
47     #10 -> reset_trigger;
48   end
49
50endmodule
51
Examples/blink/logic/simulation/blink_TB.do
1vlib work
2vlog +acc "../blink.v"
3vlog +acc "../blink_TB.v"
4vlog +acc "/opt/cad/Xilinx/verilog/src/glbl.v"
5vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver blink_TB_v glbl
6view wave
7do wave.do
8#add wave *
9add wave /glbl/GSR
10view structure
11view signals
12run 15ms
Examples/blink/logic/simulation/wave.do
1onerror {resume}
2quietly WaveActivateNextPane {} 0
3add wave -noupdate -format Logic /blink_TB_v/clk
4add wave -noupdate -format Logic /blink_TB_v/reset
5add wave -noupdate -format Logic /blink_TB_v/led
6add wave -noupdate -format Event /blink_TB_v/reset_trigger
7add wave -noupdate -format Logic /glbl/GSR
8add wave -noupdate -format Literal -radix hexadecimal /blink_TB_v/uut/counter
9add wave -noupdate -format Logic /glbl/GSR
10TreeUpdate [SetDefaultTree]
11WaveRestoreCursors {{Cursor 1} {17827 ps} 0}
12configure wave -namecolwidth 218
13configure wave -valuecolwidth 40
14configure wave -justifyvalue left
15configure wave -signalnamewidth 0
16configure wave -snapdistance 10
17configure wave -datasetprefix 0
18configure wave -rowmargin 4
19configure wave -childrowmargin 2
20configure wave -gridoffset 0
21configure wave -gridperiod 1
22configure wave -griddelta 40
23configure wave -timeline 0
24update
25WaveRestoreZoom {0 ps} {240328 ps}

Archive Download the corresponding diff file

Branches:
master



interactive