Hardware Design: SIE

Hardware Design: SIE Commit Details

Date:	2010-05-12 16:36:30 (13 years 7 months ago)
Author:	Carlos Camargo
Commit:	079d8042f6e48a7c0f86a7ef21c397248666706a
Message:	Adding iverilog simulation support
Files:	Examples/blink/logic/Makefile (3 diffs) Examples/blink/logic/blink_TB.v (1 diff) Examples/sram/logic/Makefile (2 diffs) Examples/sram/logic/simulation/sram_bus_TB.do (1 diff) Examples/sram/logic/simulation/sram_bus_TIMING_TB.do (1 diff) Examples/sram/logic/simulation/transcript (4 diffs) Examples/sram/logic/simulation/vsim.wlf (0 diffs) Examples/sram/logic/simulation/work/_info (1 diff) Examples/sram/logic/simulation/work/glbl/_primary.dat (0 diffs) Examples/sram/logic/simulation/work/sram_bus/_primary.dat (0 diffs) Examples/sram/logic/simulation/work/sram_bus/verilog.asm (0 diffs) Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.dat (0 diffs) Examples/sram/logic/simulation/work/sram_bus_@t@b_v/verilog.asm (0 diffs) Examples/sram/logic/sram_bus.v (2 diffs) Examples/sram/logic/sram_bus_TB.v (1 diff)

Change Details

Examples/blink/logic/Makefile
7	7	SIM_CMD = vsim
8	8	SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
9	9	SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
	10	IVERILOG = iverilog
	11
10	12	SAKC_IP = 192.168.254.101
11	13
12	14	SRC = $(DESIGN).v
	15
	16	SIM_SRC = $(DESIGN)_TB.v \
	17	sim/unisims/BUFG.v \
	18	sim/unisims/DCM.v \
	19	sim/unisims/FDDRRSE.v
	20
	21
13	22
14	23	all: bits
15	24
...	...
20	29	rm -f *.bit
21	30
22	31	cleanall: clean
23		rm -rf build simulation/work simulation/transcript simulation/vsim.wlf
	32	rm -rf build simulation/work simulation/transcript simulation/vsim.wlf simulation/blink_TB.vvp simulation/blink_TB.vcd
24	33
25	34	bits: $(DESIGN).bit
26	35
...	...
65	74	@mv -f build/project_r.bit $@
66	75
67	76	build/project_r.v: build/project_r.ncd
68		cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
	77	cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver projecsimulationt.ngd -w project.v
69	78
70		sim:
	79	modelsim:
71	80	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
72	81
73	82	timesim: build/project_r.v
74	83	cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
75	84
	85	iversim:
	86	$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB_v
	87	vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
	88	gtkwave simulation/$(DESIGN)_TB.vcd&
	89
76	90	upload: $(DESIGN).bit
77	91	scp $(DESIGN).bit root@$(SAKC_IP):

Examples/blink/logic/blink_TB.v
43	43	end
44	44
45	45
46		initial begin: TEST_CASE
	46	initial begin: TEST_CASE
	47	$dumpfile("blink_TB.vcd");
	48	$dumpvars(-1, uut);
	49
47	50	#10 -> reset_trigger;
	51	#((PERIODDUTY_CYCLE)100) $finish;
48	52	end
49	53
50	54	endmodule

Examples/sram/logic/Makefile
8	8	SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
9	9	SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
10	10	SAKC_IP = 192.168.254.101
	11	IVERILOG = iverilog
	12	XILINXCADROOT = /opt/cad/Xilinx/verilog/src
	13	#XILINXCADROOT = /opt/cad/modeltech/xilinx/verilog/
	14
11	15
12	16	SRC = sram_bus.v
13
	17
	18	SIM_SRC = $(DESIGN)_TB.v \
	19	# sim/unisims/BUFG.v \
	20	# sim/unisims/DCM.v \
	21	# sim/unisims/FDDRRSE.v \
	22	# glbl.v
	23	# sim/unisims/RAMB16_S2_S9.v
	24
	25
14	26	all: bits
15	27
16	28	remake: clean-build all
...	...
70	82	build/project_r.v: build/project_r.ncd
71	83	cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
72	84
73		sim:
	85	modelsim:
74	86	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
75	87
76	88	timesim: build/project_r.v
77	89	cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
78	90
	91	iversim:
	92	$(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
	93	# $(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) build/project.v $(SIM_SRC) -s $(DESIGN)_TB
	94	vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
	95	gtkwave simulation/$(DESIGN)_TB.vcd&
	96
79	97	upload: $(DESIGN).bit
80	98	scp $(DESIGN).bit root@$(SAKC_IP):

Examples/sram/logic/simulation/sram_bus_TB.do
3	3	"../sram_bus.v" \
4	4	"../sram_bus_TB.v" \
5	5	"glbl.v"
6		vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
	6	vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl
7	7	view wave
8	8	#do wave.do
9	9	add wave *

Examples/sram/logic/simulation/sram_bus_TIMING_TB.do
1	1	vlib work
2	2	vlog -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
3		vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
	3	vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl
4	4	view wave
5	5	#do wave.do
6	6	add wave *

Examples/sram/logic/simulation/transcript
13	13	# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
14	14	# -- Compiling module sram_bus
15	15	# -- Compiling module glbl
16		# -- Compiling module sram_bus_TB_v
	16	# -- Compiling module sram_bus_TB
17	17	# ** Warning: glbl.v(5): 'glbl' already exists.
18	18	# -- Compiling module glbl
19	19	#
20	20	# Top level modules:
21	21	# glbl
22		# sram_bus_TB_v
23		# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl
24		# Loading work.sram_bus_TB_v
	22	# sram_bus_TB
	23	# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl
	24	# Loading work.sram_bus_TB
25	25	# Loading work.sram_bus
26	26	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
27	27	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
...	...
33	33	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
34	34	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
35	35	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
36		# Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
37	36	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
38	37	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
39	38	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
...	...
43	42	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
44	43	# Loading work.glbl
45	44	# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
46		# Region: /sram_bus_TB_v/uut
	45	# Region: /sram_bus_TB/uut
47	46	# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
48		# Region: /sram_bus_TB_v/uut
	47	# Region: /sram_bus_TB/uut
49	48	# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
50	49	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
51	50	# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
...	...
55	54	# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
56	55	# .main_pane.workspace
57	56	# .main_pane.signals.interior.cs
58
59
60
61
62
63		exit
	57	quit

Examples/sram/logic/simulation/work/_info
12	12	r1
13	13	31
14	14	vsram_bus
15		IYS7oKaz71LdIhQ>[[g2fo3
	15	IhWan4YkPClmK5z;GkOZUS2
16	16	V7bnNHP1kz?3UaZfjPj4WE1
17		w1273511584
	17	w1273543976
18	18	F../build/project.v
19	19	L0 37
20	20	OE;L;6.0d;29
21	21	r1
22	22	31
	23	vsram_bus_TB
	24	IeNSImUgW[X4l`QoUVUKI`3
	25	V<VFiY^801Z<UUJ?^z?JM20
	26	w1273543928
	27	F../sram_bus_TB.v
	28	L0 3
	29	OE;L;6.0d;29
	30	r1
	31	31
	32	nsram_bus_@t@b
23	33	vsram_bus_TB_v
24	34	IA=m;kT@<eh:`ekMlOPXX@0
25	35	VQ[@Nfjd=de;Dc[[gj0bf41
26		w1273511227
	36	w1273541944
27	37	F../sram_bus_TB.v
28	38	L0 3
29	39	OE;L;6.0d;29
30	40	r1
31	41	31
	42	o+libext+.v
32	43	nsram_bus_@t@b_v

Examples/sram/logic/sram_bus.v
2	2	module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
3	3	parameter B = (7);
4	4
5		input clk, addr, nwe, ncs, noe, reset;
	5	input clk, nwe, ncs, noe, reset;
	6	input [12:0] addr;
6	7	inout [B:0] sram_data;
7	8	output led;
8	9
...	...
12	13	reg [B:0] buffer_data;
13	14
14	15	// interfaz fpga signals
15		wire [12:0] addr;
	16	// wire [12:0] addr;
16	17
17	18	// bram interfaz signals
18	19	reg we;

Examples/sram/logic/sram_bus_TB.v
1	1	`timescale 1ns / 1ps
2	2
3		module sram_bus_TB_v;
	3	module sram_bus_TB;
4	4
5	5	// inputs
6	6	reg clk;

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Hardware Design: SIE

Hardware Design: SIE Commit Details

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