Date:2010-05-12 16:36:30 (9 years 8 months ago)
Author:Carlos Camargo
Commit:079d8042f6e48a7c0f86a7ef21c397248666706a
Message:Adding iverilog simulation support

Files: Examples/blink/logic/Makefile (3 diffs)
Examples/blink/logic/blink_TB.v (1 diff)
Examples/sram/logic/Makefile (2 diffs)
Examples/sram/logic/simulation/sram_bus_TB.do (1 diff)
Examples/sram/logic/simulation/sram_bus_TIMING_TB.do (1 diff)
Examples/sram/logic/simulation/transcript (4 diffs)
Examples/sram/logic/simulation/vsim.wlf (0 diffs)
Examples/sram/logic/simulation/work/_info (1 diff)
Examples/sram/logic/simulation/work/glbl/_primary.dat (0 diffs)
Examples/sram/logic/simulation/work/sram_bus/_primary.dat (0 diffs)
Examples/sram/logic/simulation/work/sram_bus/verilog.asm (0 diffs)
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.dat (0 diffs)
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/verilog.asm (0 diffs)
Examples/sram/logic/sram_bus.v (2 diffs)
Examples/sram/logic/sram_bus_TB.v (1 diff)

Change Details

Examples/blink/logic/Makefile
77SIM_CMD = vsim
88SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
99SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
10IVERILOG = iverilog
11
1012SAKC_IP = 192.168.254.101
1113
1214SRC = $(DESIGN).v
15
16SIM_SRC = $(DESIGN)_TB.v \
17    sim/unisims/BUFG.v \
18    sim/unisims/DCM.v \
19    sim/unisims/FDDRRSE.v
20
21
1322
1423all: bits
1524
...... 
2029    rm -f *.bit
2130
2231cleanall: clean
23    rm -rf build simulation/work simulation/transcript simulation/vsim.wlf
32    rm -rf build simulation/work simulation/transcript simulation/vsim.wlf simulation/blink_TB.vvp simulation/blink_TB.vcd
2433
2534bits: $(DESIGN).bit
2635
...... 
6574    @mv -f build/project_r.bit $@
6675
6776build/project_r.v: build/project_r.ncd
68    cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
77    cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver projecsimulationt.ngd -w project.v
6978
70sim:
79modelsim:
7180    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
7281
7382timesim: build/project_r.v
7483    cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
7584
85iversim:
86    $(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB_v
87    vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
88    gtkwave simulation/$(DESIGN)_TB.vcd&
89
7690upload: $(DESIGN).bit
7791    scp $(DESIGN).bit root@$(SAKC_IP):
Examples/blink/logic/blink_TB.v
4343   end
4444
4545
46   initial begin: TEST_CASE
46   initial begin: TEST_CASE
47     $dumpfile("blink_TB.vcd");
48     $dumpvars(-1, uut);
49
4750     #10 -> reset_trigger;
51     #((PERIOD*DUTY_CYCLE)*100) $finish;
4852   end
4953
5054endmodule
Examples/sram/logic/Makefile
88SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
99SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
1010SAKC_IP = 192.168.254.101
11IVERILOG = iverilog
12XILINXCADROOT = /opt/cad/Xilinx/verilog/src
13#XILINXCADROOT = /opt/cad/modeltech/xilinx/verilog/
14
1115
1216SRC = sram_bus.v
13
17
18SIM_SRC = $(DESIGN)_TB.v \
19# sim/unisims/BUFG.v \
20# sim/unisims/DCM.v \
21# sim/unisims/FDDRRSE.v \
22# glbl.v
23# sim/unisims/RAMB16_S2_S9.v
24
25
1426all: bits
1527
1628remake: clean-build all
...... 
7082build/project_r.v: build/project_r.ncd
7183    cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
7284
73sim:
85modelsim:
7486    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
7587
7688timesim: build/project_r.v
7789    cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
7890
91iversim:
92    $(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
93# $(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) build/project.v $(SIM_SRC) -s $(DESIGN)_TB
94    vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
95    gtkwave simulation/$(DESIGN)_TB.vcd&
96
7997upload: $(DESIGN).bit
8098    scp $(DESIGN).bit root@$(SAKC_IP):
Examples/sram/logic/simulation/sram_bus_TB.do
33            "../sram_bus.v" \
44            "../sram_bus_TB.v" \
55            "glbl.v"
6vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
6vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl
77view wave
88#do wave.do
99add wave *
Examples/sram/logic/simulation/sram_bus_TIMING_TB.do
11vlib work
22vlog -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
3vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
3vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl
44view wave
55#do wave.do
66add wave *
Examples/sram/logic/simulation/transcript
1313# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
1414# -- Compiling module sram_bus
1515# -- Compiling module glbl
16# -- Compiling module sram_bus_TB_v
16# -- Compiling module sram_bus_TB
1717# ** Warning: glbl.v(5): 'glbl' already exists.
1818# -- Compiling module glbl
1919#
2020# Top level modules:
2121# glbl
22# sram_bus_TB_v
23# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl
24# Loading work.sram_bus_TB_v
22# sram_bus_TB
23# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl
24# Loading work.sram_bus_TB
2525# Loading work.sram_bus
2626# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
2727# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
...... 
3333# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
3434# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
3535# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
36# Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
3736# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
3837# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
3938# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
...... 
4342# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
4443# Loading work.glbl
4544# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
46# Region: /sram_bus_TB_v/uut
45# Region: /sram_bus_TB/uut
4746# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
48# Region: /sram_bus_TB_v/uut
47# Region: /sram_bus_TB/uut
4948# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
5049# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
5150# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
...... 
5554# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
5655# .main_pane.workspace
5756# .main_pane.signals.interior.cs
58
59
60
61
62
63exit
57quit
Examples/sram/logic/simulation/vsim.wlf
Examples/sram/logic/simulation/work/_info
1212r1
131331
1414vsram_bus
15IYS7oKaz71LdIhQ>[[g2fo3
15IhWan4YkPClmK5z;GkOZUS2
1616V7bnNHP1kz?3UaZfjPj4WE1
17w1273511584
17w1273543976
1818F../build/project.v
1919L0 37
2020OE;L;6.0d;29
2121r1
222231
23vsram_bus_TB
24IeNSImUgW[X4l`QoUVUKI`3
25V<VFiY^801Z<UUJ?^z?JM20
26w1273543928
27F../sram_bus_TB.v
28L0 3
29OE;L;6.0d;29
30r1
3131
32nsram_bus_@t@b
2333vsram_bus_TB_v
2434IA=m;kT@<eh:`ekMlOPXX@0
2535VQ[@Nfjd=de;Dc[[gj0bf41
26w1273511227
36w1273541944
2737F../sram_bus_TB.v
2838L0 3
2939OE;L;6.0d;29
3040r1
314131
42o+libext+.v
3243nsram_bus_@t@b_v
Examples/sram/logic/simulation/work/glbl/_primary.dat
Examples/sram/logic/simulation/work/sram_bus/_primary.dat
Examples/sram/logic/simulation/work/sram_bus/verilog.asm
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.dat
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/verilog.asm
Examples/sram/logic/sram_bus.v
22module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
33  parameter B = (7);
44
5  input clk, addr, nwe, ncs, noe, reset;
5  input clk, nwe, ncs, noe, reset;
6  input [12:0] addr;
67  inout [B:0] sram_data;
78  output led;
89
...... 
1213  reg [B:0] buffer_data;
1314
1415  // interfaz fpga signals
15  wire [12:0] addr;
16// wire [12:0] addr;
1617
1718  // bram interfaz signals
1819  reg we;
Examples/sram/logic/sram_bus_TB.v
11`timescale 1ns / 1ps
22
3module sram_bus_TB_v;
3module sram_bus_TB;
44
55   // inputs
66   reg clk;

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