Date:2010-05-10 22:09:13 (13 years 7 months ago)
Author:Carlos Camargo
Commit:23184f39dd7fee01f79564182b2dbcc96517e361
Message:Adding modelsim simulation files
Files: plasma/logic/simulation/glbl.v (1 diff)
plasma/logic/simulation/plasma_TB.do (1 diff)
plasma/logic/simulation/wave.do (1 diff)
plasma/logic/simulation/wave1.do (1 diff)

Change Details

plasma/logic/simulation/glbl.v
1// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.11.156.1 2007/03/09 18:12:55 patrickp Exp $
2
3`timescale 1 ps / 1 ps
4
5module glbl ();
6
7    parameter ROC_WIDTH = 100000;
8    parameter TOC_WIDTH = 0;
9
10    wire GSR;
11    wire GTS;
12    wire PRLD;
13
14    reg GSR_int;
15    reg GTS_int;
16    reg PRLD_int;
17
18//-------- JTAG Globals --------------
19    wire JTAG_TDO_GLBL;
20    wire JTAG_TCK_GLBL;
21    wire JTAG_TDI_GLBL;
22    wire JTAG_TMS_GLBL;
23    wire JTAG_TRST_GLBL;
24
25    reg JTAG_CAPTURE_GLBL;
26    reg JTAG_RESET_GLBL;
27    reg JTAG_SHIFT_GLBL;
28    reg JTAG_UPDATE_GLBL;
29
30    reg JTAG_SEL1_GLBL = 0;
31    reg JTAG_SEL2_GLBL = 0 ;
32    reg JTAG_SEL3_GLBL = 0;
33    reg JTAG_SEL4_GLBL = 0;
34
35    reg JTAG_USER_TDO1_GLBL = 1'bz;
36    reg JTAG_USER_TDO2_GLBL = 1'bz;
37    reg JTAG_USER_TDO3_GLBL = 1'bz;
38    reg JTAG_USER_TDO4_GLBL = 1'bz;
39
40    assign (weak1, weak0) GSR = GSR_int;
41    assign (weak1, weak0) GTS = GTS_int;
42    assign (weak1, weak0) PRLD = PRLD_int;
43
44    initial begin
45    GSR_int = 1'b1;
46    PRLD_int = 1'b1;
47    #(ROC_WIDTH)
48    GSR_int = 1'b0;
49    PRLD_int = 1'b0;
50    end
51
52    initial begin
53    GTS_int = 1'b1;
54    #(TOC_WIDTH)
55    GTS_int = 1'b0;
56    end
57
58endmodule
plasma/logic/simulation/plasma_TB.do
1vlib work
2vmap work
3vcom -93 -work work ../mlite_pack.vhd
4vcom -93 -work work ../plasma.vhd
5vcom -93 -work work ../alu.vhd
6vcom -93 -work work ../control.vhd
7vcom -93 -work work ../mem_ctrl.vhd
8vcom -93 -work work ../mult.vhd
9vcom -93 -work work ../shifter.vhd
10vcom -93 -work work ../bus_mux.vhd
11vcom -93 -work work ../ddr_ctrl.vhd
12vcom -93 -work work ../mlite_cpu.vhd
13vcom -93 -work work ../pc_next.vhd
14vcom -93 -work work ../cache.vhd
15vcom -93 -work work ../pipeline.vhd
16vcom -93 -work work ../reg_bank.vhd
17vcom -93 -work work ../uart.vhd
18vcom -93 -work work ../ram_image.vhd
19vcom -93 -work work ../plasma_TB.vhd
20
21vsim -t 1ps tbench
22view wave
23#add wave *
24do wave.do
25
26view structure
27view signals
28run 1ms
plasma/logic/simulation/wave.do
1onerror {resume}
2quietly WaveActivateNextPane {} 0
3add wave -noupdate -format Logic /tbench/clk
4add wave -noupdate -format Logic /tbench/reset
5add wave -noupdate -format Logic /tbench/interrupt
6add wave -noupdate -format Logic /tbench/mem_write
7add wave -noupdate -format Literal -radix hexadecimal /tbench/data_read
8add wave -noupdate -format Logic /tbench/pause1
9add wave -noupdate -format Logic /tbench/pause2
10add wave -noupdate -format Logic /tbench/pause
11add wave -noupdate -format Logic /tbench/u1_plasma/enable_misc
12add wave -noupdate -format Logic /tbench/u1_plasma/enable_uart
13add wave -noupdate -format Logic /tbench/uart_write
14add wave -noupdate -format Literal -radix hexadecimal /tbench/u1_plasma/cpu_data_w
15add wave -noupdate -format Literal -radix hexadecimal /tbench/u1_plasma/cpu_data_r
16add wave -noupdate -format Literal -radix hexadecimal /tbench/u1_plasma/address_next
17add wave -noupdate -format Literal /tbench/gpioa_in
18add wave -noupdate -format Logic /tbench/u1_plasma/write_enable
19add wave -noupdate -format Literal /tbench/u1_plasma/cpu_byte_we
20add wave -noupdate -format Literal -expand /tbench/u1_plasma/byte_we_next
21TreeUpdate [SetDefaultTree]
22WaveRestoreCursors {{Cursor 1} {75144797 ps} 0}
23configure wave -namecolwidth 269
24configure wave -valuecolwidth 40
25configure wave -justifyvalue left
26configure wave -signalnamewidth 0
27configure wave -snapdistance 10
28configure wave -datasetprefix 0
29configure wave -rowmargin 4
30configure wave -childrowmargin 2
31configure wave -gridoffset 0
32configure wave -gridperiod 1
33configure wave -griddelta 40
34configure wave -timeline 0
35update
36WaveRestoreZoom {71704646 ps} {72130128 ps}
plasma/logic/simulation/wave1.do
1onerror {resume}
2quietly WaveActivateNextPane {} 0
3add wave -noupdate -format Logic /plasma_TB_v/clk
4add wave -noupdate -format Logic /plasma_TB_v/reset
5add wave -noupdate -format Literal /plasma_TB_v/data_tx
6add wave -noupdate -format Event /plasma_TB_v/reset_trigger
7add wave -noupdate -format Event /plasma_TB_v/reset_done_trigger
8add wave -noupdate -format Literal /plasma_TB_v/uut/data_read
9add wave -noupdate -format Logic /plasma_TB_v/uut/ram_enable
10add wave -noupdate -format Literal -radix hexadecimal /plasma_TB_v/uut/cpu_data_w
11add wave -noupdate -format Literal -radix hexadecimal /plasma_TB_v/uut/cpu_data_r
12add wave -noupdate -format Literal /plasma_TB_v/uut/byte_we_next
13TreeUpdate [SetDefaultTree]
14WaveRestoreCursors {{Cursor 1} {3952754 ps} 0}
15configure wave -namecolwidth 240
16configure wave -valuecolwidth 100
17configure wave -justifyvalue left
18configure wave -signalnamewidth 0
19configure wave -snapdistance 10
20configure wave -datasetprefix 0
21configure wave -rowmargin 4
22configure wave -childrowmargin 2
23configure wave -gridoffset 0
24configure wave -gridperiod 1
25configure wave -griddelta 40
26configure wave -timeline 0
27update
28WaveRestoreZoom {3946113 ps} {4013617 ps}

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