Hardware Design: SIE

Hardware Design: SIE Commit Details

Date:	2010-05-12 17:06:23 (13 years 7 months ago)
Author:	Carlos Camargo
Commit:	47b7172e9896650584b804af3e984688abcd4c78
Message:	Fixing Makefile errors
Files:	Examples/blink/logic/Makefile (2 diffs) Examples/blink/logic/blink_TB.v (1 diff) Examples/sram/logic/Makefile (2 diffs) Examples/sram/logic/simulation/transcript (1 diff) Examples/sram/logic/simulation/vsim.wlf (0 diffs) Examples/sram/logic/simulation/work/_info (1 diff) Examples/sram/logic/simulation/work/glbl/_primary.dat (0 diffs) Examples/sram/logic/simulation/work/sram_bus/_primary.dat (0 diffs) Examples/sram/logic/simulation/work/sram_bus/_primary.vhd (1 diff) Examples/sram/logic/simulation/work/sram_bus/verilog.asm (0 diffs)

Change Details

Examples/blink/logic/Makefile
74	74	@mv -f build/project_r.bit $@
75	75
76	76	build/project_r.v: build/project_r.ncd
77		cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver projecsimulationt.ngd -w project.v
	77	cd build && ngd2ver project.ngd -w project.v
78	78
79	79	modelsim:
80	80	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
...	...
83	83	cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
84	84
85	85	iversim:
86		$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB_v
	86	$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
87	87	vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
88	88	gtkwave simulation/$(DESIGN)_TB.vcd&
89	89

Examples/blink/logic/blink_TB.v
1	1	`timescale 1ns / 1ps
2	2
3		module blink_TB_v;
	3	module blink_TB;
4	4
5	5	reg clk;
6	6	reg reset;

Examples/sram/logic/Makefile
29	29
30	30	clean:
31	31	rm -f ~ /~ a.out .log .key .edf *.ps trace.dat
32		rm *.bit
	32	rm -rf *.bit
33	33
34	34	clean-build: clean
35	35	rm -rf build
...	...
80	80	@mv -f build/project_r.bit $@
81	81
82	82	build/project_r.v: build/project_r.ncd
83		cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
	83	cd build && ngd2ver project.ngd -w project.v
84	84
85	85	modelsim:
86	86	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do

Examples/sram/logic/simulation/transcript
8	8	# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
9	9	# // AND IS SUBJECT TO LICENSE TERMS.
10	10	# //
11		# do sram_bus_TIMING_TB.do
	11	# do sram_bus_TB.do
12	12	# ** Warning: (vlib-34) Library already exists at "work".
13	13	# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
14	14	# -- Compiling module sram_bus
15		# -- Compiling module glbl
16	15	# -- Compiling module sram_bus_TB
17		# ** Warning: glbl.v(5): 'glbl' already exists.
18	16	# -- Compiling module glbl
19	17	#
20	18	# Top level modules:
21		# glbl
22	19	# sram_bus_TB
	20	# glbl
23	21	# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl
24	22	# Loading work.sram_bus_TB
25	23	# Loading work.sram_bus
26		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
27		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
28		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF
29		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF
30		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2
31		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2
32		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2
33		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
34		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
35		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
36		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
37		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
38		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
39		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD
40		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF
41		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT
42		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
	24	# Loading /opt/cad/modeltech/xilinx/verilog/unisims_ver.RAMB16_S2
43	25	# Loading work.glbl
44	26	# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
45	27	# Region: /sram_bus_TB/uut
46	28	# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
47	29	# Region: /sram_bus_TB/uut
48	30	# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
49		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
50		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
51		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux
52		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4
53		# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4
54	31	# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
55	32	# .main_pane.workspace
56	33	# .main_pane.signals.interior.cs

Examples/sram/logic/simulation/work/_info
11	11	OE;L;6.0d;29
12	12	r1
13	13	31
	14	o+libext+.v
14	15	vsram_bus
15		IhWan4YkPClmK5z;GkOZUS2
16		V7bnNHP1kz?3UaZfjPj4WE1
17		w1273543976
18		F../build/project.v
19		L0 37
	16	I4L5C3LJ<U_bBN0U__mYo>0
	17	V7R>S0^PdJz?6eY;E[l1^E2
	18	w1273543761
	19	F../sram_bus.v
	20	L0 2
20	21	OE;L;6.0d;29
21	22	r1
22	23	31
	24	o+libext+.v
23	25	vsram_bus_TB
24	26	IeNSImUgW[X4l`QoUVUKI`3
25	27	V<VFiY^801Z<UUJ?^z?JM20
26		w1273543928
	28	w1273676679
27	29	F../sram_bus_TB.v
28	30	L0 3
29	31	OE;L;6.0d;29
30	32	r1
31	33	31
	34	o+libext+.v
32	35	nsram_bus_@t@b
33	36	vsram_bus_TB_v
34	37	IA=m;kT@<eh:`ekMlOPXX@0

Examples/sram/logic/simulation/work/sram_bus/_primary.vhd
1	1	library verilog;
2	2	use verilog.vl_types.all;
3	3	entity sram_bus is
	4	generic(
	5	B : integer := 7
	6	);
4	7	port(
5	8	clk : in vl_logic;
6		reset : in vl_logic;
	9	sram_data : inout vl_logic_vector;
	10	addr : in vl_logic_vector(12 downto 0);
	11	nwe : in vl_logic;
7	12	ncs : in vl_logic;
8	13	noe : in vl_logic;
9		nwe : in vl_logic;
10		led : out vl_logic;
11		sram_data : inout vl_logic_vector(7 downto 0);
12		addr : in vl_logic_vector(12 downto 0)
	14	reset : in vl_logic;
	15	led : out vl_logic
13	16	);
14	17	end sram_bus;

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Hardware Design: SIE

Hardware Design: SIE Commit Details

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