Date:2010-05-12 17:06:23 (9 years 8 months ago)
Author:Carlos Camargo
Commit:47b7172e9896650584b804af3e984688abcd4c78
Message:Fixing Makefile errors

Files: Examples/blink/logic/Makefile (2 diffs)
Examples/blink/logic/blink_TB.v (1 diff)
Examples/sram/logic/Makefile (2 diffs)
Examples/sram/logic/simulation/transcript (1 diff)
Examples/sram/logic/simulation/vsim.wlf (0 diffs)
Examples/sram/logic/simulation/work/_info (1 diff)
Examples/sram/logic/simulation/work/glbl/_primary.dat (0 diffs)
Examples/sram/logic/simulation/work/sram_bus/_primary.dat (0 diffs)
Examples/sram/logic/simulation/work/sram_bus/_primary.vhd (1 diff)
Examples/sram/logic/simulation/work/sram_bus/verilog.asm (0 diffs)

Change Details

Examples/blink/logic/Makefile
7474    @mv -f build/project_r.bit $@
7575
7676build/project_r.v: build/project_r.ncd
77    cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver projecsimulationt.ngd -w project.v
77    cd build && ngd2ver project.ngd -w project.v
7878
7979modelsim:
8080    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
...... 
8383    cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
8484
8585iversim:
86    $(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB_v
86    $(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
8787    vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
8888    gtkwave simulation/$(DESIGN)_TB.vcd&
8989
Examples/blink/logic/blink_TB.v
11`timescale 1ns / 1ps
22
3module blink_TB_v;
3module blink_TB;
44
55   reg clk;
66   reg reset;
Examples/sram/logic/Makefile
2929
3030clean:
3131    rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
32    rm *.bit
32    rm -rf *.bit
3333
3434clean-build: clean
3535    rm -rf build
...... 
8080    @mv -f build/project_r.bit $@
8181
8282build/project_r.v: build/project_r.ncd
83    cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
83    cd build && ngd2ver project.ngd -w project.v
8484
8585modelsim:
8686    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
Examples/sram/logic/simulation/transcript
88# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
99# // AND IS SUBJECT TO LICENSE TERMS.
1010# //
11# do sram_bus_TIMING_TB.do
11# do sram_bus_TB.do
1212# ** Warning: (vlib-34) Library already exists at "work".
1313# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
1414# -- Compiling module sram_bus
15# -- Compiling module glbl
1615# -- Compiling module sram_bus_TB
17# ** Warning: glbl.v(5): 'glbl' already exists.
1816# -- Compiling module glbl
1917#
2018# Top level modules:
21# glbl
2219# sram_bus_TB
20# glbl
2321# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl
2422# Loading work.sram_bus_TB
2523# Loading work.sram_bus
26# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
27# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
28# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF
29# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF
30# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2
31# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2
32# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2
33# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
34# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
35# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
36# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
37# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
38# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
39# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD
40# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF
41# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT
42# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
24# Loading /opt/cad/modeltech/xilinx/verilog/unisims_ver.RAMB16_S2
4325# Loading work.glbl
4426# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
4527# Region: /sram_bus_TB/uut
4628# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
4729# Region: /sram_bus_TB/uut
4830# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
49# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
50# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
51# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux
52# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4
53# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4
5431# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
5532# .main_pane.workspace
5633# .main_pane.signals.interior.cs
Examples/sram/logic/simulation/vsim.wlf
Examples/sram/logic/simulation/work/_info
1111OE;L;6.0d;29
1212r1
131331
14o+libext+.v
1415vsram_bus
15IhWan4YkPClmK5z;GkOZUS2
16V7bnNHP1kz?3UaZfjPj4WE1
17w1273543976
18F../build/project.v
19L0 37
16I4L5C3LJ<U_bBN0U__mYo>0
17V7R>S0^PdJz?6eY;E[l1^E2
18w1273543761
19F../sram_bus.v
20L0 2
2021OE;L;6.0d;29
2122r1
222331
24o+libext+.v
2325vsram_bus_TB
2426IeNSImUgW[X4l`QoUVUKI`3
2527V<VFiY^801Z<UUJ?^z?JM20
26w1273543928
28w1273676679
2729F../sram_bus_TB.v
2830L0 3
2931OE;L;6.0d;29
3032r1
313331
34o+libext+.v
3235nsram_bus_@t@b
3336vsram_bus_TB_v
3437IA=m;kT@<eh:`ekMlOPXX@0
Examples/sram/logic/simulation/work/glbl/_primary.dat
Examples/sram/logic/simulation/work/sram_bus/_primary.dat
Examples/sram/logic/simulation/work/sram_bus/_primary.vhd
11library verilog;
22use verilog.vl_types.all;
33entity sram_bus is
4    generic(
5        B : integer := 7
6    );
47    port(
58        clk : in vl_logic;
6        reset : in vl_logic;
9        sram_data : inout vl_logic_vector;
10        addr : in vl_logic_vector(12 downto 0);
11        nwe : in vl_logic;
712        ncs : in vl_logic;
813        noe : in vl_logic;
9        nwe : in vl_logic;
10        led : out vl_logic;
11        sram_data : inout vl_logic_vector(7 downto 0);
12        addr : in vl_logic_vector(12 downto 0)
14        reset : in vl_logic;
15        led : out vl_logic
1316    );
1417end sram_bus;
Examples/sram/logic/simulation/work/sram_bus/verilog.asm

Archive Download the corresponding diff file

Branches:
master



interactive