Hardware Design: SIE

Hardware Design: SIE Commit Details

Date:	2010-06-11 15:06:13 (13 years 6 months ago)
Author:	Carlos Camargo
Commit:	5041c0eb60ab780746243015df81dfd5193de83b
Message:	Updating examples to Board changes, adding irq driver demo
Files:	Examples/ADC/logic/ADC.ucf (1 diff) Examples/ADC/logic/ADC.v (4 diffs) Examples/blink/logic/blink.ucf (1 diff) Examples/blink/logic/blink.v (1 diff) Examples/drivers/IRQ/Makefile (1 diff) Examples/drivers/IRQ/irq.c (1 diff) Examples/drivers/IRQ/irq_main.c (1 diff) Examples/hello_nand/build/Makefile (1 diff) Examples/hello_nand/build/load_u-boot (1 diff) Examples/hello_sram/build/1 (1 diff) Examples/hello_sram/build/Makefile (1 diff) Examples/sram/logic/sram_bus.ucf (1 diff) Examples/sram/logic/sram_bus.v (3 diffs) Examples/sram/src/Makefile (3 diffs) Examples/sram/src/jz47xx_gpio.c (1 diff) lm32/logic/milkymist-avnet (1 diff) lm32/logic/sakc/cores/ps2/rtl/ps2.v (1 diff) lm32/logic/sakc/cores/uart/doc/Makefile (1 diff) lm32/logic/sakc/cores/uart/doc/uart.tex (1 diff) lm32/logic/sakc/cores/uart/rtl/uart.v (1 diff) lm32/logic/sakc/cores/uart/rtl/uart_transceiver.v (1 diff) lm32/logic/sakc/cores/vgafb/doc/Makefile (1 diff) lm32/logic/sakc/cores/vgafb/doc/vgafb.tex (1 diff) lm32/logic/sakc/cores/vgafb/rtl/vgafb.v (1 diff) lm32/logic/sakc/cores/vgafb/rtl/vgafb_asfifo.v (1 diff) lm32/logic/sakc/cores/vgafb/rtl/vgafb_asfifo_xilinx.v (1 diff) lm32/logic/sakc/cores/vgafb/rtl/vgafb_ctlif.v (1 diff) lm32/logic/sakc/cores/vgafb/rtl/vgafb_fifo64to16.v (1 diff) lm32/logic/sakc/cores/vgafb/rtl/vgafb_graycounter.v (1 diff) lm32/logic/sakc/cores/vgafb/rtl/vgafb_pixelfeed.v (1 diff) lm32/logic/sakc/cores/vgafb/test/Makefile (1 diff) lm32/logic/sakc/cores/vgafb/test/tb_pixelfeed.v (1 diff) lm32/logic/sakc/system_tb.v (1 diff) plasma/datasheet/28f128j3_256j3_320j3_640j3.pdf (0 diffs) plasma/logic/mlite_pack.vhd (1 diff) plasma/logic/plasma.ucf (1 diff) plasma/logic/plasma.vhd (3 diffs) plasma/logic/plasma_TB.vhd (2 diffs) plasma/logic/ram.vhd (1 diff) plasma/logic/ram_image.vhd (4 diffs) plasma/logic/tbench.vhd (1 diff)

Change Details

Examples/ADC/logic/ADC.ucf
1		NET clk LOC = "P38";
2		NET reset LOC = "P71"; #WARNING change to another pin
3		NET led LOC = "P44";
	1	NET clk LOC = "P38";
	2	NET reset LOC = "P30"; #WARNING change to another pin
	3	NET led LOC = "P44";
	4	NET irq_pin LOC = "P71";
4	5
5	6	#ADDRESS BUS
6	7	NET "addr<12>" LOC = "P90";

Examples/ADC/logic/ADC.v
1	1	`timescale 1ns / 1ps
2	2	module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
3		ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART);
	3	ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART, irq_pin);
4	4
5		parameter B = (7);
	5	parameter B = (7);
6	6
7	7	input clk, addr, nwe, ncs, noe, reset, ADC_EOC;
8	8	inout [B:0] sram_data;
9	9	output led, ADC_CS, ADC_CSTART, ADC_SCLK;
10		inout ADC_SDIN, ADC_SDOUT;
	10	inout ADC_SDIN, ADC_SDOUT;
	11	input irq_pin;
11	12
12	13
13	14	// Internal conection
...	...
32	33
33	34	// Test : LED blinking
34	35	always @(posedge clk) begin
35		if (reset)
	36	if (~reset)
36	37	counter <= {25{1'b0}};
37	38	else
38	39	counter <= counter + 1;
...	...
54	55
55	56	// write access cpu to bram
56	57	always @(posedge clk)
57		if(reset) {w_st, we, wrBus} <= 0;
	58	if(~reset) {w_st, we, wrBus} <= 0;
58	59	else begin
59	60	wrBus <= buffer_data;
60	61	case (w_st)
...	...
89	90	// Peripheral instantiation
90	91	ADC_peripheral P1(
91	92	.clk(clk),
92		.reset(reset),
	93	.reset(~reset),
93	94	.cs(csN[0]),
94	95	.ADC_EOC(ADC_EOC),
95	96	.ADC_CS(ADC_CS),

Examples/blink/logic/blink.ucf
1	1	NET clk LOC = "P38";
2		NET reset LOC = "P71";
	2	NET reset LOC = "P30";
3	3	NET led LOC = "P44";
4	4
5	5	#ADDRESS BUS

Examples/blink/logic/blink.v
5	5
6	6	reg [24:0] counter;
7	7	always @(posedge clk) begin
8		if (reset)
	8	if (~reset)
9	9	counter <= {25{1'b0}};
10	10	else
11	11	counter <= counter + 1;

Examples/drivers/IRQ/Makefile
	1	EXTRA_CFLAGS += -Wall
	2	CC = mipsel-openwrt-linux-gcc
	3	OPENWRT_BASE = /home/cain/Embedded/ingenic/sakc/build/openwrt-xburst
	4	KERNEL_SRC = $(OPENWRT_BASE)/build_dir/linux-xburst_qi_lb60/linux-2.6.32.10/
	5	CROSS_COMPILE = mipsel-openwrt-linux-
	6
	7	obj-m += irq.o
	8	all: driver irq_main
	9
	10	driver:
	11	make -C $(KERNEL_SRC) M=$(PWD) ARCH=mips CROSS_COMPILE=$(CROSS_COMPILE) modules
	12	clean:
	13	make -C $(KERNEL_SRC) M=$(PWD) ARCH=mips CROSS_COMPILE=$(CROSS_COMPILE) clean
	14	rm -rf *.o main.o main irq.ko Modules.symvers irq_main
	15
	16	main: main.o
	17
	18	PREPROCESS.c = $(CC) $(CFLAGS) $(TARGET_ARCH) -E -Wp,-C,-dD,-dI
	19	%.pp : %.c FORCE
	20	$(PREPROCESS.c) $< > $@
	21
	22
	23

Examples/drivers/IRQ/irq.c
	1	/*
	2	* Interrupt device driver demo
	3	*
	4	* Author: Andres Calderon
	5	* Created: September 16, 2005
	6	* Copyright: (C) 2005 emQbit Ltda
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/module.h> /* Needed by all modules */
	16	#include <linux/kernel.h> /* Needed for KERN_INFO */
	17	#include <linux/ioport.h>
	18	#include <linux/device.h>
	19	#include <linux/interrupt.h> /* We want an interrupt */
	20	#include <linux/irq.h> /* We want an interrupt */
	21	#include <linux/platform_device.h>
	22	#include <linux/fs.h>
	23	#include <asm/delay.h>
	24	#include <asm/uaccess.h>
	25	#include <asm/io.h>
	26	#include <linux/gpio.h>
	27	#include <asm/mach-jz4740/gpio.h>
	28
	29
	30
	31	#define FPGA_IRQ_PIN JZ_GPIO_PORTC(15)
	32	#define FPGA_BASE 0x15000000 //FPGA_BASE (FPGA) 0x14000000 - 0x17FFFFFF //
	33	#define SUCCESS 0
	34	#define DEVICE_NAME "irq" /* Dev name as it appears in /proc/devices */
	35	#define BUF_LEN 80 /* Max length of the message from the device */
	36
	37
	38
	39	static int device_open(struct inode , struct file );
	40	static int device_release(struct inode , struct file );
	41	static ssize_t device_read(struct file , char , size_t, loff_t *);
	42	static ssize_t device_write(struct file , const char , size_t, loff_t *);
	43
	44	static int irq_enabled = 0;
	45	static int is_device_open = 0; /* Is device open? Used to prevent multiple access to device */
	46	static int Major;
	47
	48	void __iomem *ioaddress;
	49	static unsigned int interrupt_counter = 0;
	50
	51	static DECLARE_WAIT_QUEUE_HEAD(wq);
	52
	53
	54	struct file_operations fops = {
	55	.owner = THIS_MODULE,
	56	.read = device_read,
	57	.write = device_write,
	58	.open = device_open,
	59	.release = device_release
	60	};
	61
	62
	63
	64	static irqreturn_t irq_handler(int irq, void *dev_id)
	65	{
	66	if(irq_enabled)
	67	{
	68	interrupt_counter++;
	69	printk(KERN_INFO "interrupt_counter=%d\n",interrupt_counter);
	70	wake_up_interruptible(&wq);
	71	}
	72
	73	return IRQ_HANDLED;
	74	}
	75
	76
	77	static int __init qem_init(void)
	78	{
	79	int res, irq;
	80	printk(KERN_INFO "FPGA module is Up.\n");
	81	interrupt_counter = 0;
	82
	83	Major = register_chrdev(0, DEVICE_NAME, &fops);
	84
	85	if (Major < 0) {
	86	printk(KERN_ALERT "Registering char device failed with %d\n", Major);
	87	return Major;
	88	}
	89
	90	printk(KERN_ALERT "I was assigned major number %d. To talk to\n", Major);
	91	printk(KERN_ALERT "the driver, create a dev file with\n");
	92	printk(KERN_ALERT "'mknod /dev/%s c %d 0'.\n", DEVICE_NAME, Major);
	93
	94
	95	/* Set up the FGPA irq line */
	96	irq = gpio_to_irq(FPGA_IRQ_PIN);
	97
	98	res = request_irq(irq, irq_handler, IRQF_DISABLED \| IRQF_TRIGGER_RISING, "FPGA - IRQ", NULL); // IRQF_TRIGGER_FALLING
	99
	100	ioaddress = ioremap(FPGA_BASE, 0x4000);
	101
	102	return 0;
	103	}
	104
	105
	106	static void __exit qem_exit(void)
	107	{
	108	// int ret;
	109	/Tho order for free_irq, iounmap & unregister is very important /
	110	free_irq(FPGA_IRQ_PIN, NULL);
	111	iounmap(ioaddress);
	112	unregister_chrdev(Major, DEVICE_NAME);
	113	printk(KERN_INFO "FPGA driver is down...\n");
	114	}
	115
	116
	117	static int device_open(struct inode inode, struct file file)
	118	{
	119	if (is_device_open)
	120	return -EBUSY;
	121
	122	is_device_open = 1;
	123
	124	try_module_get(THIS_MODULE);
	125
	126	return SUCCESS;
	127	}
	128
	129	static int device_release(struct inode inode, struct file file)
	130	{
	131	is_device_open = 0;
	132
	133	module_put(THIS_MODULE);
	134
	135	return 0;
	136	}
	137
	138	static ssize_t device_read(struct file filp, / see include/linux/fs.h */
	139	char buffer, / buffer to fill with data */
	140	size_t count, /* length of the buffer */
	141	loff_t *offset)
	142	{
	143
	144	wait_event_interruptible(wq, interrupt_counter!=0);
	145	return copy_to_user(buffer, &interrupt_counter, sizeof(interrupt_counter)) ? -EFAULT : 0;
	146	}
	147
	148	static ssize_t
	149	device_write(struct file filp, const char buff, size_t count, loff_t * off)
	150	{
	151	const char cmd = buff[0];
	152
	153	if(cmd=='Q')
	154	{
	155	irq_enabled = 1;
	156	printk(KERN_INFO "FPGA irq_enabled...\n");
	157
	158	}
	159	else
	160	if(cmd=='S'){
	161	irq_enabled = 0;
	162	printk(KERN_INFO "FPGA irq disabled.\n");
	163	}
	164
	165	return 1;
	166	}
	167
	168	module_init(qem_init);
	169	module_exit(qem_exit);
	170
	171
	172	MODULE_LICENSE("GPL");
	173	MODULE_AUTHOR("Andres Calderon <andresn@emqbit.com>");
	174	MODULE_DESCRIPTION("FPGA' IRQ driver");
	175	MODULE_VERSION("1:0.1");

Examples/drivers/IRQ/irq_main.c
	1	/*******************************************************************************
	2	*
	3	* Filename: irq_main.c
	4	* Author: Carlos Camargo
	5	* Created: June 10, 2010
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	******************************************************************************/
	13
	14	#include "stdio.h"
	15	#include "sys/types.h"
	16	#include "sys/stat.h"
	17	#include "fcntl.h"
	18	#include <unistd.h>
	19	#include <stdlib.h>
	20
	21	int main(int argc, char **argv) {
	22	int fileNum, bytes;
	23	unsigned char buf[40];
	24	size_t nbytes;
	25	ssize_t bytes_read;
	26
	27	if(argc != 2){
	28	fprintf(stderr,"\nUsage: %s enable\|disable\|read \n",argv[0]);
	29	}
	30
	31	nbytes = sizeof(int);
	32	fileNum = open("/dev/irq", O_RDWR);
	33	if (fileNum < 0) {
	34	printf(" Unable to open device\n");
	35	exit(1);
	36	}
	37	printf("Device opened successfully \n");
	38
	39	if(!strcmp(argv[1], "enable"))
	40	write(fileNum, "Q", 1);
	41	if(!strcmp(argv[1], "disable"))
	42	write(fileNum, "S", 1);
	43	if(!strcmp(argv[1], "read")){
	44	read(fileNum, buf, nbytes);
	45	printf("Interrupts = %d \n", ((int)(buf)));
	46	}
	47	if( (strcmp(argv[1], "read") != 0 ) & (strcmp(argv[1], "disable") != 0) & (strcmp(argv[1], "enable") != 0) )
	48	fprintf(stderr,"\nUsage: %s enable\|disable\|read \n",argv[0]);
	49
	50	close(fileNum);
	51
	52	return (0);
	53	}

Examples/hello_nand/build/Makefile
1
2	1	OBJS := start.o main.o jz_serial.o
3	2
4		CROSS := mipsel-elf-
	3	CROSS := mipsel-openwrt-linux-
5	4
6	5	CFLAGS := -O2 -G 0 -mno-abicalls -fno-pic -mips32 -Iinclude
7	6	AFLAGS = -D__ASSEMBLY__ $(CFLAGS)

Examples/hello_nand/build/load_u-boot
1		sudo usbboot -f ./usbboot_2gb_nand.cfg -c "boot"
2		sudo usbboot -f ./usbboot_2gb_nand.cfg -c "nprog 0 openwrt-xburst-u-boot.bin 0 0 -n"

Examples/hello_sram/build/1
1
2		OBJS := start.o main.o jz_serial.o
3
4		CROSS := mipsel-elf-
5
6		CFLAGS := -O2 -G 0 -mno-abicalls -fno-pic -mips32 -Iinclude
7		AFLAGS = -D__ASSEMBLY__ $(CFLAGS)
8		LDFLAGS := -T ld.script -nostdlib -EL
9
10		.c.o:
11		$(CROSS)gcc $(CFLAGS) -c $< -o $@
12		.S.o:
13		$(CROSS)gcc $(AFLAGS) -c $< -o $@
14
15		jz_xloader.bin: jz_xloader
16		$(CROSS)objdump -D jz_xloader $< > jz_xloader.dump
17		$(CROSS)objcopy -O binary $< $@
18
19		jz_xloader: $(OBJS)
20		$(CROSS)ld $(LDFLAGS) $^ -o $@
21
22		upload:
23		usbtool 1
24		clean:
25		rm -fr *.o jz_xloader jz_xloader.bin jz_xloader.dump

Examples/hello_sram/build/Makefile
1	1
2	2	OBJS := start.o main.o jz_serial.o
3	3
4		CROSS := mipsel-elf-
	4	CROSS := mipsel-openwrt-linux-
5	5
6	6	CFLAGS := -O2 -G 0 -mno-abicalls -fno-pic -mips32 -Iinclude
7	7	AFLAGS = -D__ASSEMBLY__ $(CFLAGS)

Examples/sram/logic/sram_bus.ucf
1		NET clk LOC = "P38";
2		NET reset LOC = "P71";
3		NET led LOC = "P44";
	1	NET clk LOC = "P38";
	2	NET reset LOC = "P30";
	3	NET led LOC = "P44";
	4	NET irq_pin LOC = "P71";
4	5
5	6	#ADDRESS BUS
6	7	NET "addr<12>" LOC = "P90";

Examples/sram/logic/sram_bus.v
1	1	`timescale 1ns / 1ps
2		module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
	2	module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led, irq_pin);
3	3	parameter B = (7);
4	4
5	5	input clk, nwe, ncs, noe, reset;
6	6	input [12:0] addr;
7	7	inout [B:0] sram_data;
8	8	output led;
	9	input irq_pin;
9	10
10	11	// synchronize signals
11	12	reg sncs, snwe;
...	...
39	40
40	41	// write access cpu to bram
41	42	always @(posedge clk)
42		if(reset) {w_st, we, wdBus} <= 0;
	43	if(~reset) {w_st, we, wdBus} <= 0;
43	44	else begin
44	45	wdBus <= buffer_data;
45	46	case (w_st)
...	...
71	72
72	73	reg [24:0] counter;
73	74	always @(posedge clk) begin
74		if (reset)
	75	if (~reset)
75	76	counter <= {25{1'b0}};
76	77	else
77	78	counter <= counter + 1;

Examples/sram/src/Makefile
1	1	CC = mipsel-openwrt-linux-gcc
2	2
3		all: jz_init_sram jz_test_gpio enable_rx
	3	all: jz_init_sram jz_test_gpio enable_rx enable_irq
4	4
5	5	DEBUG = -O3 -g0
6	6
...	...
29	29	enable_rx: $(COMMON_OBJECTS)
30	30	$(CC) $(LDFLAGS) $(COMMON_OBJECTS) enable_rx.c -o enable_rx
31	31
	32	enable_irq: $(COMMON_OBJECTS)
	33	$(CC) $(LDFLAGS) $(COMMON_OBJECTS) enable_irq.c -o enable_irq
	34
32	35	.c.o:
33	36	$(CC) -c $(CCFLAGS) $< -o $@
34	37
...	...
36	39	scp jz_test_gpio jz_init_sram root@$(NANO_IP):
37	40
38	41	clean:
39		rm -f .o jz_init_sram jz_test_gpio enable_rx ${EXEC} ~
	42	rm -f .o jz_init_sram jz_test_gpio enable_rx ${EXEC} ~ enable_irq
40	43
41	44	indent:
42	45	indent -bad -bap -nbc -bl -nce -i2 --no-tabs --line-length120 $(COMMON_SOURCES) $(H_SOURCES)

Examples/sram/src/jz47xx_gpio.c
44	44	}
45	45
46	46	void
	47	jz_gpio_as_irq (JZ_PIO * pio, unsigned int o)
	48	{
	49	pio->PXFUNC = (1 << (o));
	50	pio->PXSELS = (1 << (o));
	51	pio->PXDIRC = (1 << (o));
	52	}
	53
	54	void
47	55	jz_gpio_set_pin (JZ_PIO * pio, unsigned int o)
48	56	{
49	57	pio->PXDATS = (1 << (o));

lm32/logic/milkymist-avnet
	1	Subproject commit 0219d98a994a35c46d700460caa78f84c971b9af

lm32/logic/sakc/cores/ps2/rtl/ps2.v
	1	/*
	2	* PS2 Interface
	3	* Copyright (C) 2009 Takeshi Matsuya
	4	* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, version 3 of the License.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	module ps2 #(
	20	parameter csr_addr = 4'h0,
	21	parameter clk_freq = 100000000
	22	) (
	23	input sys_rst,
	24	input sys_clk,
	25
	26	input [13:0] csr_a,
	27	input csr_we,
	28	input [31:0] csr_di,
	29	output reg [31:0] csr_do,
	30
	31	inout ps2_clk,
	32	inout ps2_data,
	33	output reg irq
	34	);
	35
	36	/* CSR interface */
	37	wire csr_selected = csr_a[13:10] == csr_addr;
	38	reg tx_busy;
	39
	40	//-----------------------------------------------------------------
	41	// divisor
	42	//-----------------------------------------------------------------
	43	reg [9:0] enable_counter;
	44	wire enable;
	45	assign enable = (enable_counter == 10'd0);
	46
	47	parameter divisor = clk_freq/12800/16;
	48
	49	always @(posedge sys_clk) begin
	50	if(sys_rst)
	51	enable_counter <= divisor - 10'd1;
	52	else begin
	53	enable_counter <= enable_counter - 10'd1;
	54	if(enable)
	55	enable_counter <= divisor - 10'd1;
	56	end
	57	end
	58
	59	//-----------------------------------------------------------------
	60	// Synchronize ps2 clock and data
	61	//-----------------------------------------------------------------
	62	reg ps2_clk_1;
	63	reg ps2_data_1;
	64	reg ps2_clk_2;
	65	reg ps2_data_2;
	66	reg ps2_clk_out;
	67	reg ps2_data_out1, ps2_data_out2;
	68
	69	always @(posedge sys_clk) begin
	70	ps2_clk_1 <= ps2_clk;
	71	ps2_data_1 <= ps2_data;
	72	ps2_clk_2 <= ps2_clk_1;
	73	ps2_data_2 <= ps2_data_1;
	74	end
	75
	76	/* PS2 */
	77	reg [7:0] kcode;
	78	reg rx_clk_data;
	79	reg [5:0] rx_clk_count;
	80	reg [4:0] rx_bitcount;
	81	reg [10:0] rx_data;
	82	reg [10:0] tx_data;
	83	reg we_reg;
	84
	85	/* FSM */
	86	reg [2:0] state;
	87	reg [2:0] next_state;
	88
	89	parameter RECEIVE = 3'd0;
	90	parameter WAIT_READY = 3'd1;
	91	parameter CLOCK_LOW = 3'd2;
	92	parameter CLOCK_HIGH = 3'd3;
	93	parameter CLOCK_HIGH1 = 3'd4;
	94	parameter CLOCK_HIGH2 = 3'd5;
	95	parameter WAIT_CLOCK_LOW = 3'd6;
	96	parameter TRANSMIT = 3'd7;
	97
	98	assign state_receive = state == RECEIVE;
	99	assign state_transmit = state == TRANSMIT;
	100
	101	always @(posedge sys_clk) begin
	102	if(sys_rst)
	103	state = RECEIVE;
	104	else begin
	105	state = next_state;
	106	end
	107	end
	108
	109	/* ps2 clock falling edge 100us counter */
	110	//parameter divisor_100us = clk_freq/10000;
	111	parameter divisor_100us = 1;
	112	reg [16:0] watchdog_timer;
	113	wire watchdog_timer_done;
	114	assign watchdog_timer_done = (watchdog_timer == 17'd0);
	115	always @(sys_clk) begin
	116	if(sys_rst\|\|ps2_clk_out)
	117	watchdog_timer <= divisor_100us - 1;
	118	else if(~watchdog_timer_done)
	119	watchdog_timer <= watchdog_timer - 1;
	120	end
	121
	122	always @(*) begin
	123	ps2_clk_out = 1'b1;
	124	ps2_data_out1 = 1'b1;
	125	tx_busy = 1'b1;
	126
	127	next_state = state;
	128
	129	case(state)
	130	RECEIVE: begin
	131	tx_busy = 1'b0;
	132	if(we_reg) begin
	133	next_state = WAIT_READY;
	134	end
	135	end
	136	WAIT_READY: begin
	137	if(rx_bitcount == 5'd0) begin
	138	ps2_clk_out = 1'b0;
	139	next_state = CLOCK_LOW;
	140	end
	141	end
	142	CLOCK_LOW: begin
	143	ps2_clk_out = 1'b0;
	144	if(watchdog_timer_done) begin
	145	next_state = CLOCK_HIGH;
	146	end
	147	end
	148	CLOCK_HIGH: begin
	149	next_state = CLOCK_HIGH1;
	150	end
	151	CLOCK_HIGH1: begin
	152	next_state = CLOCK_HIGH2;
	153	end
	154	CLOCK_HIGH2: begin
	155	ps2_data_out1 = 1'b0;
	156	next_state = WAIT_CLOCK_LOW;
	157	end
	158	WAIT_CLOCK_LOW: begin
	159	ps2_data_out1 = 1'b0;
	160	if(ps2_clk_2 == 1'b0) begin
	161	next_state = TRANSMIT;
	162	end
	163	end
	164	TRANSMIT: begin
	165	if(rx_bitcount == 5'd10) begin
	166	next_state = RECEIVE;
	167	end
	168	end
	169	endcase
	170	end
	171
	172	//-----------------------------------------------------------------
	173	// PS2 RX/TX Logic
	174	//-----------------------------------------------------------------
	175	always @(posedge sys_clk) begin
	176	if(sys_rst) begin
	177	rx_clk_data <= 1'd1;
	178	rx_clk_count <= 5'd0;
	179	rx_bitcount <= 5'd0;
	180	rx_data <= 11'b11111111111;
	181	irq <= 1'd0;
	182	csr_do <= 32'd0;
	183	we_reg <= 1'b0;
	184	ps2_data_out2 <= 1'b1;
	185	end else begin
	186	irq <= 1'b0;
	187	we_reg <= 1'b0;
	188	csr_do <= 32'd0;
	189	if(csr_selected) begin
	190	case(csr_a[0])
	191	1'b0: csr_do <= kcode;
	192	1'b1: csr_do <= tx_busy;
	193	endcase
	194	if(csr_we && csr_a[0] == 1'b0) begin
	195	tx_data <= {2'b11, ~(^csr_di[7:0]), csr_di[7:0]}; // STOP+PARITY+DATA
	196	we_reg <= 1'b1;
	197	end
	198	end
	199	if(enable) begin
	200	if(rx_clk_data == ps2_clk_2) begin
	201	rx_clk_count <= rx_clk_count + 5'd1;
	202	end else begin
	203	rx_clk_count <= 5'd0;
	204	rx_clk_data <= ps2_clk_2;
	205	end
	206	if(state_receive && rx_clk_data == 1'b0 && rx_clk_count == 5'd4) begin
	207	rx_data <= {ps2_data_2, rx_data[10:1]};
	208	rx_bitcount <= rx_bitcount + 5'd1;
	209	if(rx_bitcount == 5'd10) begin
	210	irq <= 1'b1;
	211	kcode <= rx_data[9:2];
	212	end
	213	end
	214	if(state_transmit && rx_clk_data == 1'b0 && rx_clk_count == 5'd0) begin
	215	ps2_data_out2 <= tx_data[rx_bitcount];
	216	rx_bitcount <= rx_bitcount + 5'd1;
	217	if(rx_bitcount == 5'd10) begin
	218	ps2_data_out2 <= 1'b1;
	219	end
	220	end
	221	if(rx_clk_count == 5'd16) begin
	222	rx_bitcount <= 5'd0;
	223	rx_data <= 11'b11111111111;
	224	end
	225	end
	226	end
	227	end
	228
	229	assign ps2_clk = ps2_clk_out ? 1'hz : 1'b0;
	230	assign ps2_data = ps2_data_out1 & ps2_data_out2 ? 1'hz : 1'b0;
	231
	232	endmodule

lm32/logic/sakc/cores/uart/doc/Makefile
	1	TEX=uart.tex
	2
	3	DVI=$(TEX:.tex=.dvi)
	4	PS=$(TEX:.tex=.ps)
	5	PDF=$(TEX:.tex=.pdf)
	6	AUX=$(TEX:.tex=.aux)
	7	LOG=$(TEX:.tex=.log)
	8
	9	all: $(PDF)
	10
	11	%.dvi: %.tex
	12	latex $<
	13
	14	%.ps: %.dvi
	15	dvips $<
	16
	17	%.pdf: %.ps
	18	ps2pdf $<
	19
	20	clean:
	21	rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG)
	22
	23	.PHONY: clean

lm32/logic/sakc/cores/uart/doc/uart.tex
	1	\documentclass[a4paper,11pt]{article}
	2	\usepackage{fullpage}
	3	\usepackage[latin1]{inputenc}
	4	\usepackage[T1]{fontenc}
	5	\usepackage[normalem]{ulem}
	6	\usepackage[english]{babel}
	7	\usepackage{listings,babel}
	8	\lstset{breaklines=true,basicstyle=\ttfamily}
	9	\usepackage{graphicx}
	10	\usepackage{moreverb}
	11	\usepackage{amsmath}
	12	\usepackage{url}
	13	\usepackage{tabularx}
	14
	15	\title{Simple UART}
	16	\author{S\'ebastien Bourdeauducq}
	17	\date{December 2009}
	18	\begin{document}
	19	\setlength{\parindent}{0pt}
	20	\setlength{\parskip}{5pt}
	21	\maketitle{}
	22	\section{Specifications}
	23	The UART is based on a very simple design from Das Labor. Its purpose is basically to provide a debug console.
	24
	25	The UART operates with 8 bits per character, no parity, and 1 stop bit. The default baudrate is configured during synthesis and can be modified at runtime using the divisor register.
	26
	27	The divisor is computed as follows :
	28	\begin{equation*}
	29	\text{divisor} = \frac{\text{Clock frequency (Hz)}}{16 \cdot \text{Bitrate (bps)}}
	30	\end{equation*}
	31
	32	\section{Registers}
	33	\begin{tabularx}{\textwidth}{\|l\|l\|l\|X\|}
	34	\hline
	35	\bf{Offset} & \bf{Read/Write} & \bf{Default} & \bf{Description} \\
	36	\hline
	37	0x0 & RW & 0x00 & Data register. Received bytes and bytes to transmit are read/written from/to this register. \\
	38	\hline
	39	0x4 & RW & for default bitrate & Divisor register (for bitrate selection). \\
	40	\hline
	41	\end{tabularx}\\
	42
	43	\section{Interrupts}
	44	The core has two active-high edge-sensitive interrupts outputs.
	45
	46	The ``RX'' interrupt is sent whenever a new character is received. The CPU should then read the data register immediately. If a new character is sent before the CPU has had time to read it, the first character will be lost.
	47
	48	The ``TX'' interrupt is sent as soon as the UART finished transmitting a character. When the CPU has written to the data register, it must wait for the interrupt before writing again.
	49
	50	\section{Using the core}
	51	Connect the CSR signals and the interrupts to the system bus and the interrupt controller. The \verb!uart_txd! and \verb!uart_rxd! signals should go to the FPGA pads. You must also provide the desired default baudrate and the system clock frequency in Hz using the parameters.
	52
	53	\section*{Copyright notice}
	54	Copyright \copyright 2007-2009 S\'ebastien Bourdeauducq. \\
	55	Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
	56
	57	\end{document}

lm32/logic/sakc/cores/uart/rtl/uart.v
	1	/*
	2	* Milkymist VJ SoC
	3	* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
	4	*
	5	* This program is free software: you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation, version 3 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	module uart #(
	19	parameter csr_addr = 4'h0,
	20	parameter clk_freq = 100000000,
	21	parameter baud = 115200
	22	) (
	23	input sys_clk,
	24	input sys_rst,
	25
	26	input [13:0] csr_a,
	27	input csr_we,
	28	input [31:0] csr_di,
	29	output reg [31:0] csr_do,
	30
	31	output rx_irq,
	32	output tx_irq,
	33
	34	input uart_rxd,
	35	output uart_txd
	36	);
	37
	38	reg [15:0] divisor;
	39	wire [7:0] rx_data;
	40	wire [7:0] tx_data;
	41	wire tx_wr;
	42
	43	uart_transceiver transceiver(
	44	.sys_clk(sys_clk),
	45	.sys_rst(sys_rst),
	46
	47	.uart_rxd(uart_rxd),
	48	.uart_txd(uart_txd),
	49
	50	.divisor(divisor),
	51
	52	.rx_data(rx_data),
	53	.rx_done(rx_irq),
	54
	55	.tx_data(tx_data),
	56	.tx_wr(tx_wr),
	57	.tx_done(tx_irq)
	58	);
	59
	60	/* CSR interface */
	61	wire csr_selected = csr_a[13:10] == csr_addr;
	62
	63	assign tx_data = csr_di[7:0];
	64	assign tx_wr = csr_selected & csr_we & (csr_a[0] == 1'b0);
	65
	66	parameter default_divisor = clk_freq/baud/16;
	67
	68	always @(posedge sys_clk) begin
	69	if(sys_rst) begin
	70	divisor <= default_divisor;
	71	csr_do <= 32'd0;
	72	end else begin
	73	csr_do <= 32'd0;
	74	if(csr_selected) begin
	75	case(csr_a[0])
	76	1'b0: csr_do <= rx_data;
	77	1'b1: csr_do <= divisor;
	78	endcase
	79	if(csr_we) begin
	80	if(csr_a[0] == 1'b1)
	81	divisor <= csr_di[15:0];
	82	end
	83	end
	84	end
	85	end
	86
	87	endmodule

lm32/logic/sakc/cores/uart/rtl/uart_transceiver.v
	1	/*
	2	* Milkymist VJ SoC
	3	* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
	4	* Copyright (C) 2007 Das Labor
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, version 3 of the License.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	module uart_transceiver(
	20	input sys_rst,
	21	input sys_clk,
	22
	23	input uart_rxd,
	24	output reg uart_txd,
	25
	26	input [15:0] divisor,
	27
	28	output reg [7:0] rx_data,
	29	output reg rx_done,
	30
	31	input [7:0] tx_data,
	32	input tx_wr,
	33	output reg tx_done
	34	);
	35
	36	//-----------------------------------------------------------------
	37	// enable16 generator
	38	//-----------------------------------------------------------------
	39	reg [15:0] enable16_counter;
	40
	41	wire enable16;
	42	assign enable16 = (enable16_counter == 16'd0);
	43
	44	always @(posedge sys_clk) begin
	45	if(sys_rst)
	46	enable16_counter <= divisor - 16'b1;
	47	else begin
	48	enable16_counter <= enable16_counter - 16'd1;
	49	if(enable16)
	50	enable16_counter <= divisor - 16'b1;
	51	end
	52	end
	53
	54	//-----------------------------------------------------------------
	55	// Synchronize uart_rxd
	56	//-----------------------------------------------------------------
	57	reg uart_rxd1;
	58	reg uart_rxd2;
	59
	60	always @(posedge sys_clk) begin
	61	uart_rxd1 <= uart_rxd;
	62	uart_rxd2 <= uart_rxd1;
	63	end
	64
	65	//-----------------------------------------------------------------
	66	// UART RX Logic
	67	//-----------------------------------------------------------------
	68	reg rx_busy;
	69	reg [3:0] rx_count16;
	70	reg [3:0] rx_bitcount;
	71	reg [7:0] rxd_reg;
	72
	73	always @(posedge sys_clk) begin
	74	if(sys_rst) begin
	75	rx_done <= 1'b0;
	76	rx_busy <= 1'b0;
	77	rx_count16 <= 4'd0;
	78	rx_bitcount <= 4'd0;
	79	end else begin
	80	rx_done <= 1'b0;
	81
	82	if(enable16) begin
	83	if(~rx_busy) begin // look for start bit
	84	if(~uart_rxd2) begin // start bit found
	85	rx_busy <= 1'b1;
	86	rx_count16 <= 4'd7;
	87	rx_bitcount <= 4'd0;
	88	end
	89	end else begin
	90	rx_count16 <= rx_count16 + 4'd1;
	91
	92	if(rx_count16 == 4'd0) begin // sample
	93	rx_bitcount <= rx_bitcount + 4'd1;
	94
	95	if(rx_bitcount == 4'd0) begin // verify startbit
	96	if(uart_rxd2)
	97	rx_busy <= 1'b0;
	98	end else if(rx_bitcount == 4'd9) begin
	99	rx_busy <= 1'b0;
	100	if(uart_rxd2) begin // stop bit ok
	101	rx_data <= rxd_reg;
	102	rx_done <= 1'b1;
	103	end // ignore RX error
	104	end else
	105	rxd_reg <= {uart_rxd2, rxd_reg[7:1]};
	106	end
	107	end
	108	end
	109	end
	110	end
	111
	112	//-----------------------------------------------------------------
	113	// UART TX Logic
	114	//-----------------------------------------------------------------
	115	reg tx_busy;
	116	reg [3:0] tx_bitcount;
	117	reg [3:0] tx_count16;
	118	reg [7:0] txd_reg;
	119
	120	always @(posedge sys_clk) begin
	121	if(sys_rst) begin
	122	tx_done <= 1'b0;
	123	tx_busy <= 1'b0;
	124	uart_txd <= 1'b1;
	125	end else begin
	126	tx_done <= 1'b0;
	127	if(tx_wr) begin
	128	txd_reg <= tx_data;
	129	tx_bitcount <= 4'd0;
	130	tx_count16 <= 4'd1;
	131	tx_busy <= 1'b1;
	132	uart_txd <= 1'b0;
	133	`ifdef SIMULATION
	134	$display("UART: %c", tx_data);
	135	`endif
	136	end else if(enable16 && tx_busy) begin
	137	tx_count16 <= tx_count16 + 4'd1;
	138
	139	if(tx_count16 == 4'd0) begin
	140	tx_bitcount <= tx_bitcount + 4'd1;
	141
	142	if(tx_bitcount == 4'd8) begin
	143	uart_txd <= 1'b1;
	144	end else if(tx_bitcount == 4'd9) begin
	145	uart_txd <= 1'b1;
	146	tx_busy <= 1'b0;
	147	tx_done <= 1'b1;
	148	end else begin
	149	uart_txd <= txd_reg[0];
	150	txd_reg <= {1'b0, txd_reg[7:1]};
	151	end
	152	end
	153	end
	154	end
	155	end
	156
	157	endmodule

lm32/logic/sakc/cores/vgafb/doc/Makefile
	1	TEX=vgafb.tex
	2
	3	DVI=$(TEX:.tex=.dvi)
	4	PS=$(TEX:.tex=.ps)
	5	PDF=$(TEX:.tex=.pdf)
	6	AUX=$(TEX:.tex=.aux)
	7	LOG=$(TEX:.tex=.log)
	8
	9	all: $(PDF)
	10
	11	%.dvi: %.tex
	12	latex $<
	13
	14	%.ps: %.dvi
	15	dvips $<
	16
	17	%.pdf: %.ps
	18	ps2pdf $<
	19
	20	clean:
	21	rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG)
	22
	23	.PHONY: clean

lm32/logic/sakc/cores/vgafb/doc/vgafb.tex
	1	\documentclass[a4paper,11pt]{article}
	2	\usepackage{fullpage}
	3	\usepackage[latin1]{inputenc}
	4	\usepackage[T1]{fontenc}
	5	\usepackage[normalem]{ulem}
	6	\usepackage[english]{babel}
	7	\usepackage{listings,babel}
	8	\lstset{breaklines=true,basicstyle=\ttfamily}
	9	\usepackage{graphicx}
	10	\usepackage{moreverb}
	11	\usepackage{url}
	12	\usepackage{amsmath}
	13
	14	\title{VGA framebuffer}
	15	\author{S\'ebastien Bourdeauducq}
	16	\date{December 2009}
	17	\begin{document}
	18	\setlength{\parindent}{0pt}
	19	\setlength{\parskip}{5pt}
	20	\maketitle{}
	21	\section{Specifications}
	22	The VGA framebuffer core enables a system-on-chip to support a VGA video output with the picture read from a memory framebuffer.
	23	The core directly drives a 3-channel 8-bit digital to analog converter and the horizontal and vertical synchronization signals.
	24	The framebuffer is read with a 4x64 FastMemoryLink (FML) master; and a CSR interface is implemented for configuring the video output.
	25
	26	\section{Registers}
	27	\subsection{Control register, offset 0x00}
	28	This register enables or disables the video output by setting or clearing the reset bit 0. At reset, the default value is 0x1.
	29
	30	\subsection{Horizontal video parameters, offsets 0x04, 0x08, 0x0c and 0x10}
	31	Those registers set respectively:
	32	\begin{itemize}
	33	\item the horizontal size of the active video area (the horizontal resolution)
	34	\item the position of the beginning of the horizontal sync pulse in the scan line, in pixel clocks
	35	\item the position of the end of the horizontal sync pulse in the scan line, in pixel clocks
	36	\item the total length of the horizontal scan line minus one, in pixels
	37	\end{itemize}
	38	The default values are for the standard VGA resolution of 640x480 at 60Hz with a 25MHz pixel clock.
	39
	40	\subsection{Vertical video parameters, offsets 0x14, 0x18, 0x1c and 0x20}
	41	Those registers set respectively:
	42	\begin{itemize}
	43	\item the vertical size of the active video area (the vertical resolution)
	44	\item the position of the beginning of the vertical sync pulse. The unit is the horizontal scan line.
	45	\item the position of the end of the vertical sync pulse. Same unit as above.
	46	\item the total count of horizontal scan lines minus one. Same unit as above.
	47	\end{itemize}
	48	The default values are for the standard VGA resolution of 640x480 at 60Hz with a 25MHz pixel clock.
	49
	50	\subsection{DMA control registers, offsets 0x24, 0x28 and 0x2c}
	51	The register 0x24 defines the base address of the framebuffer. That framebuffer is basic progressive scan buffer using the RGB565 pixel format.
	52
	53	When register 0x24 is written, the framebuffer address is not updated immediately. Instead, the VGA core waits for the end of the vertical active video area and only starts fetching data from the new framebuffer at the beginning of the next frame. This enables the use of multiple framebuffers without any tearing or flickering artifacts. The address from which the core is currently reading data is available in register 0x28.
	54	When registers 0x24 and 0x28 have different values, a framebuffer address change is pending. When they have the same values, the frame being displayed is the latest that was asked for.
	55
	56	The framebuffer must be aligned to the start of a FML burst ($\frac{4 \cdot 64}{8}$ bytes).
	57
	58	Register 0x2c defines the number of FML bursts required to fill a complete screen. This is typically set to:
	59	\[
	60	\frac{\text{horizontal resolution} \cdot \text{vertical resolution} \cdot 16}{4 \cdot 64}
	61	\]
	62
	63	The screen resolution must be set so that this number is integer. This is the case with common VGA resolutions.
	64
	65	\section{Connections}
	66	The pixel clock is not generated internally and must be fed to the core using the \verb!vga_clk! port. No relationship is expected with the system clock (the two domains are entirely independent). That pixel clock should also be fed to the synchronous DAC.
	67
	68	The other ports should be self-explanatory.
	69
	70	\section*{Copyright notice}
	71	Copyright \copyright 2007-2009 S\'ebastien Bourdeauducq. \\
	72	Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
	73
	74	\end{document}

lm32/logic/sakc/cores/vgafb/rtl/vgafb.v
	1	/*
	2	* Milkymist VJ SoC
	3	* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
	4	*
	5	* This program is free software: you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation, version 3 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	module vgafb #(
	19	parameter csr_addr = 4'h0,
	20	parameter fml_depth = 26
	21	) (
	22	input sys_clk,
	23	input sys_rst,
	24
	25	/* Configuration interface */
	26	input [13:0] csr_a,
	27	input csr_we,
	28	input [31:0] csr_di,
	29	output [31:0] csr_do,
	30
	31	/* Framebuffer FML 4x64 interface */
	32	output [fml_depth-1:0] fml_adr,
	33	output fml_stb,
	34	input fml_ack,
	35	input [63:0] fml_di,
	36
	37	/* VGA pixel clock */
	38	input vga_clk,
	39
	40	/* VGA signal pads */
	41	output vga_psave_n,
	42	output reg vga_hsync_n,
	43	output reg vga_vsync_n,
	44	output vga_sync_n,
	45	output vga_blank_n,
	46	output reg [7:0] vga_r,
	47	output reg [7:0] vga_g,
	48	output reg [7:0] vga_b,
	49	output [1:0] vga_clk_sel
	50	);
	51
	52	/*
	53	* Control interface
	54	*/
	55	wire vga_rst;
	56
	57	wire [10:0] hres;
	58	wire [10:0] hsync_start;
	59	wire [10:0] hsync_end;
	60	wire [10:0] hscan;
	61
	62	wire [10:0] vres;
	63	wire [10:0] vsync_start;
	64	wire [10:0] vsync_end;
	65	wire [10:0] vscan;
	66
	67	wire [fml_depth-1:0] baseaddress;
	68	wire baseaddress_ack;
	69
	70	wire [17:0] nbursts;
	71
	72	vgafb_ctlif #(
	73	.csr_addr(csr_addr),
	74	.fml_depth(fml_depth)
	75	) ctlif (
	76	.sys_clk(sys_clk),
	77	.sys_rst(sys_rst),
	78
	79	.csr_a(csr_a),
	80	.csr_we(csr_we),
	81	.csr_di(csr_di),
	82	.csr_do(csr_do),
	83
	84	.vga_rst(vga_rst),
	85
	86	.hres(hres),
	87	.hsync_start(hsync_start),
	88	.hsync_end(hsync_end),
	89	.hscan(hscan),
	90
	91	.vres(vres),
	92	.vsync_start(vsync_start),
	93	.vsync_end(vsync_end),
	94	.vscan(vscan),
	95
	96	.baseaddress(baseaddress),
	97	.baseaddress_ack(baseaddress_ack),
	98
	99	.nbursts(nbursts),
	100
	101	.vga_clk_sel(vga_clk_sel)
	102	);
	103
	104	/*
	105	* Generate signal data
	106	*/
	107	reg hsync_n;
	108	reg vsync_n;
	109	wire pixel_valid;
	110	wire [15:0] pixel_fb;
	111	wire pixel_ack;
	112	wire [15:0] pixel;
	113
	114	wire fifo_full;
	115
	116	reg hactive;
	117	reg vactive;
	118	wire active = hactive & vactive;
	119	assign pixel = active ? pixel_fb : 16'h0000;
	120
	121	wire generate_en;
	122
	123	reg [10:0] hcounter;
	124	reg [10:0] vcounter;
	125
	126	always @(posedge sys_clk) begin
	127	if(vga_rst) begin
	128	hcounter <= 10'd0;
	129	vcounter <= 10'd0;
	130	hactive <= 1'b0;
	131	hsync_n <= 1'b1;
	132	vactive <= 1'b0;
	133	vsync_n <= 1'b1;
	134	end else begin
	135	if(generate_en) begin
	136	hcounter <= hcounter + 10'd1;
	137
	138	if(hcounter == 10'd0) hactive <= 1'b1;
	139	if(hcounter == hres) hactive <= 1'b0;
	140	if(hcounter == hsync_start) hsync_n <= 1'b0;
	141	if(hcounter == hsync_end) hsync_n <= 1'b1;
	142	if(hcounter == hscan) begin
	143	hcounter <= 10'd0;
	144	if(vcounter == vscan)
	145	vcounter <= 10'd0;
	146	else
	147	vcounter <= vcounter + 10'd1;
	148	end
	149
	150	if(vcounter == 10'd0) vactive <= 1'b1;
	151	if(vcounter == vres) vactive <= 1'b0;
	152	if(vcounter == vsync_start) vsync_n <= 1'b0;
	153	if(vcounter == vsync_end) vsync_n <= 1'b1;
	154	end
	155	end
	156	end
	157
	158	assign generate_en = ~fifo_full & (~active \| pixel_valid);
	159	assign pixel_ack = ~fifo_full & active & pixel_valid;
	160
	161	vgafb_pixelfeed #(
	162	.fml_depth(fml_depth)
	163	) pixelfeed (
	164	.sys_clk(sys_clk),
	165	.sys_rst(sys_rst),
	166	.vga_rst(vga_rst),
	167
	168	.nbursts(nbursts),
	169	.baseaddress(baseaddress),
	170	.baseaddress_ack(baseaddress_ack),
	171
	172	.fml_adr(fml_adr),
	173	.fml_stb(fml_stb),
	174	.fml_ack(fml_ack),
	175	.fml_di(fml_di),
	176
	177	.pixel_valid(pixel_valid),
	178	.pixel(pixel_fb),
	179	.pixel_ack(pixel_ack)
	180	);
	181
	182	/*
	183	* System clock to VGA clock domain crossing is
	184	* acheived by an asynchronous FIFO.
	185	*
	186	* Bits 0-15 are RGB565 pixel data
	187	* Bit 16 is negated Horizontal Sync
	188	* Bit 17 is negated Verical Sync
	189	*/
	190	wire [17:0] fifo_do;
	191
	192	vgafb_asfifo #(
	193	.DATA_WIDTH(18),
	194	.ADDRESS_WIDTH(6)
	195	) fifo (
	196	.Data_out(fifo_do),
	197	.Empty_out(),
	198	.ReadEn_in(1'b1),
	199	.RClk(vga_clk),
	200
	201	.Data_in({vsync_n, hsync_n, pixel}),
	202	.Full_out(fifo_full),
	203	.WriteEn_in(generate_en),
	204	.WClk(sys_clk),
	205
	206	.Clear_in(vga_rst)
	207	);
	208
	209	/*
	210	* Drive the VGA pads.
	211	* RGB565 -> RGB888 color space conversion is also performed here
	212	* by bit shifting and replicating the most significant bits of
	213	* the input into the least significant bits of the output left
	214	* undefined by the shifting.
	215	*/
	216
	217	assign vga_sync_n = 1'b0; /* Sync-on-Green is not implemented */
	218	assign vga_psave_n = 1'b1;
	219	assign vga_blank_n = 1'b1;
	220
	221	always @(posedge vga_clk) begin
	222	vga_vsync_n <= fifo_do[17];
	223	vga_hsync_n <= fifo_do[16];
	224	vga_r <= {fifo_do[15:11], fifo_do[15:13]};
	225	vga_g <= {fifo_do[10:5], fifo_do[10:9]};
	226	vga_b <= {fifo_do[4:0], fifo_do[4:2]};
	227	end
	228
	229	endmodule

lm32/logic/sakc/cores/vgafb/rtl/vgafb_asfifo.v
	1	//==========================================
	2	// Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
	3	// Coder : Alex Claros F.
	4	// Date : 15/May/2005.
	5	// Notes : This implementation is based on the article
	6	// 'Asynchronous FIFO in Virtex-II FPGAs'
	7	// writen by Peter Alfke. This TechXclusive
	8	// article can be downloaded from the
	9	// Xilinx website. It has some minor modifications.
	10	//=========================================
	11
	12	`timescale 1ns / 1ps
	13
	14	module vgafb_asfifo
	15	#(parameter DATA_WIDTH = 8,
	16	ADDRESS_WIDTH = 4,
	17	FIFO_DEPTH = (1 << ADDRESS_WIDTH))
	18	//Reading port
	19	(output wire [DATA_WIDTH-1:0] Data_out,
	20	output reg Empty_out,
	21	input wire ReadEn_in,
	22	input wire RClk,
	23	//Writing port.
	24	input wire [DATA_WIDTH-1:0] Data_in,
	25	output reg Full_out,
	26	input wire WriteEn_in,
	27	input wire WClk,
	28
	29	input wire Clear_in);
	30
	31	/////Internal connections & variables//////
	32	reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0];
	33	wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;
	34	wire EqualAddresses;
	35	wire NextWriteAddressEn, NextReadAddressEn;
	36	wire Set_Status, Rst_Status;
	37	reg Status;
	38	wire PresetFull, PresetEmpty;
	39
	40	//////////////Code///////////////
	41	//Data ports logic:
	42	//(Uses a dual-port RAM).
	43	//'Data_out' logic:
	44	assign Data_out = Mem[pNextWordToRead];
	45	// always @ (posedge RClk)
	46	// if (!PresetEmpty)
	47	// Data_out <= Mem[pNextWordToRead];
	48	// if (ReadEn_in & !Empty_out)
	49
	50	//'Data_in' logic:
	51	always @ (posedge WClk)
	52	if (WriteEn_in & !Full_out)
	53	Mem[pNextWordToWrite] <= Data_in;
	54
	55	//Fifo addresses support logic:
	56	//'Next Addresses' enable logic:
	57	assign NextWriteAddressEn = WriteEn_in & ~Full_out;
	58	assign NextReadAddressEn = ReadEn_in & ~Empty_out;
	59
	60	//Addreses (Gray counters) logic:
	61	vgafb_graycounter #(
	62	.COUNTER_WIDTH( ADDRESS_WIDTH )
	63	) GrayCounter_pWr (
	64	.GrayCount_out(pNextWordToWrite),
	65	.Enable_in(NextWriteAddressEn),
	66	.Clear_in(Clear_in),
	67
	68	.Clk(WClk)
	69	);
	70
	71	vgafb_graycounter #(
	72	.COUNTER_WIDTH( ADDRESS_WIDTH )
	73	) GrayCounter_pRd (
	74	.GrayCount_out(pNextWordToRead),
	75	.Enable_in(NextReadAddressEn),
	76	.Clear_in(Clear_in),
	77	.Clk(RClk)
	78	);
	79
	80
	81	//'EqualAddresses' logic:
	82	assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
	83
	84	//'Quadrant selectors' logic:
	85	assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
	86	(pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);
	87
	88	assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) &
	89	(pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
	90
	91	//'Status' latch logic:
	92	always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
	93	if (Rst_Status \| Clear_in)
	94	Status = 0; //Going 'Empty'.
	95	else if (Set_Status)
	96	Status = 1; //Going 'Full'.
	97
	98	//'Full_out' logic for the writing port:
	99	assign PresetFull = Status & EqualAddresses; //'Full' Fifo.
	100
	101	always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
	102	if (PresetFull)
	103	Full_out <= 1;
	104	else
	105	Full_out <= 0;
	106
	107	//'Empty_out' logic for the reading port:
	108	assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.
	109
	110	always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
	111	if (PresetEmpty)
	112	Empty_out <= 1;
	113	else
	114	Empty_out <= 0;
	115
	116	endmodule

lm32/logic/sakc/cores/vgafb/rtl/vgafb_asfifo_xilinx.v
	1	/*
	2	* Milkymist VJ SoC
	3	* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
	4	*
	5	* This program is free software: you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation, version 3 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	/* FIXME: this module does not work. Find out why. */
	19
	20	module vgafb_asfifo #(
	21	/* NB: those are fixed in this implementation */
	22	parameter DATA_WIDTH = 18,
	23	parameter ADDRESS_WIDTH = 11
	24	) (
	25	/* Reading port */
	26	output [17:0] Data_out,
	27	output Empty_out,
	28	input ReadEn_in,
	29	input RClk,
	30
	31	/* Writing port */
	32	input [17:0] Data_in,
	33	output Full_out,
	34	input WriteEn_in,
	35	input WClk,
	36
	37	input Clear_in
	38	);
	39
	40	wire full;
	41	wire empty;
	42
	43	FIFO16 #(
	44	.DATA_WIDTH(9),
	45	.FIRST_WORD_FALL_THROUGH("TRUE")
	46	) fifo_lo (
	47	.ALMOSTEMPTY(),
	48	.ALMOSTFULL(),
	49	.DO(Data_out[7:0]),
	50	.DOP(Data_out[8]),
	51	.EMPTY(empty),
	52	.FULL(full),
	53	.RDCOUNT(),
	54	.RDERR(),
	55	.WRCOUNT(),
	56	.WRERR(),
	57	.DI(Data_in[7:0]),
	58	.DIP(Data_in[8]),
	59	.RDCLK(RClk),
	60	.RDEN(ReadEn_in & ~empty & ~Clear_in),
	61	.RST(Clear_in),
	62	.WRCLK(WClk),
	63	.WREN(WriteEn_in & ~full & ~Clear_in)
	64	);
	65
	66	assign Empty_out = empty;
	67	assign Full_out = full;
	68
	69	FIFO16 #(
	70	.DATA_WIDTH(9),
	71	.FIRST_WORD_FALL_THROUGH("TRUE")
	72	) fifo_hi (
	73	.ALMOSTEMPTY(),
	74	.ALMOSTFULL(),
	75	.DO(Data_out[16:9]),
	76	.DOP(Data_out[17]),
	77	.EMPTY(),
	78	.FULL(),
	79	.RDCOUNT(),
	80	.RDERR(),
	81	.WRCOUNT(),
	82	.WRERR(),
	83	.DI(Data_in[16:9]),
	84	.DIP(Data_in[17]),
	85	.RDCLK(RClk),
	86	.RDEN(ReadEn_in & ~empty & ~Clear_in),
	87	.RST(Clear_in),
	88	.WRCLK(WClk),
	89	.WREN(WriteEn_in & ~full & ~Clear_in)
	90	);
	91
	92	endmodule
	93

lm32/logic/sakc/cores/vgafb/rtl/vgafb_ctlif.v
	1	/*
	2	* Milkymist VJ SoC
	3	* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
	4	*
	5	* This program is free software: you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation, version 3 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	module vgafb_ctlif #(
	19	parameter csr_addr = 4'h0,
	20	parameter fml_depth = 26
	21	) (
	22	input sys_clk,
	23	input sys_rst,
	24
	25	input [13:0] csr_a,
	26	input csr_we,
	27	input [31:0] csr_di,
	28	output reg [31:0] csr_do,
	29
	30	output reg vga_rst,
	31
	32	output reg [10:0] hres,
	33	output reg [10:0] hsync_start,
	34	output reg [10:0] hsync_end,
	35	output reg [10:0] hscan,
	36
	37	output reg [10:0] vres,
	38	output reg [10:0] vsync_start,
	39	output reg [10:0] vsync_end,
	40	output reg [10:0] vscan,
	41
	42	output reg [fml_depth-1:0] baseaddress,
	43	input baseaddress_ack,
	44
	45	output reg [17:0] nbursts,
	46
	47	output reg [1:0] vga_clk_sel
	48	);
	49
	50	reg [fml_depth-1:0] baseaddress_act;
	51
	52	always @(posedge sys_clk) begin
	53	if(sys_rst)
	54	baseaddress_act <= {fml_depth{1'b0}};
	55	else if(baseaddress_ack)
	56	baseaddress_act <= baseaddress;
	57	end
	58
	59	wire csr_selected = csr_a[13:10] == csr_addr;
	60
	61	always @(posedge sys_clk) begin
	62	if(sys_rst) begin
	63	csr_do <= 32'd0;
	64
	65	vga_rst <= 1'b1;
	66
	67	hres <= 10'd640;
	68	hsync_start <= 10'd656;
	69	hsync_end <= 10'd752;
	70	hscan <= 10'd799;
	71
	72	vres <= 10'd480;
	73	vsync_start <= 10'd491;
	74	vsync_end <= 10'd493;
	75	vscan <= 10'd523;
	76
	77	baseaddress <= {fml_depth{1'b0}};
	78
	79	nbursts <= 18'd19200;
	80	vga_clk_sel <= 2'd00;
	81	end else begin
	82	csr_do <= 32'd0;
	83	if(csr_selected) begin
	84	if(csr_we) begin
	85	case(csr_a[3:0])
	86	4'd0: vga_rst <= csr_di[0];
	87	4'd1: hres <= csr_di[10:0];
	88	4'd2: hsync_start <= csr_di[10:0];
	89	4'd3: hsync_end <= csr_di[10:0];
	90	4'd4: hscan <= csr_di[10:0];
	91	4'd5: vres <= csr_di[10:0];
	92	4'd6: vsync_start <= csr_di[10:0];
	93	4'd7: vsync_end <= csr_di[10:0];
	94	4'd8: vscan <= csr_di[10:0];
	95	4'd9: baseaddress <= csr_di[fml_depth-1:0];
	96	// 10: baseaddress_act is read-only for Wishbone
	97	4'd11: nbursts <= csr_di[17:0];
	98	4'd12: vga_clk_sel <= csr_di[1:0];
	99	endcase
	100	end
	101
	102	case(csr_a[3:0])
	103	4'd0: csr_do <= vga_rst;
	104	4'd1: csr_do <= hres;
	105	4'd2: csr_do <= hsync_start;
	106	4'd3: csr_do <= hsync_end;
	107	4'd4: csr_do <= hscan;
	108	4'd5: csr_do <= vres;
	109	4'd6: csr_do <= vsync_start;
	110	4'd7: csr_do <= vsync_end;
	111	4'd8: csr_do <= vscan;
	112	4'd9: csr_do <= baseaddress;
	113	4'd10: csr_do <= baseaddress_act;
	114	4'd11: csr_do <= nbursts;
	115	4'd12: csr_do <= vga_clk_sel;
	116	endcase
	117	end
	118	end
	119	end
	120
	121	endmodule

lm32/logic/sakc/cores/vgafb/rtl/vgafb_fifo64to16.v
	1	/*
	2	* Milkymist VJ SoC
	3	* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
	4	*
	5	* This program is free software: you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation, version 3 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	module vgafb_fifo64to16(
	19	input sys_clk,
	20	input vga_rst,
	21
	22	input stb,
	23	input [63:0] di,
	24
	25	output do_valid,
	26	output reg [15:0] do,
	27	input next /* should only be asserted when do_valid = 1 */
	28	);
	29
	30	/*
	31	* FIFO can hold 4 64-bit words
	32	* that is 16 16-bit words.
	33	*/
	34
	35	reg [63:0] storage[0:3];
	36	reg [1:0] produce; /* in 64-bit words */
	37	reg [3:0] consume; /* in 16-bit words */
	38	/*
	39	* 16-bit words stored in the FIFO, 0-16 (17 possible values)
	40	*/
	41	reg [4:0] level;
	42
	43	wire [63:0] do64;
	44	assign do64 = storage[consume[3:2]];
	45
	46	always @(*) begin
	47	case(consume[1:0])
	48	2'd0: do <= do64[63:48];
	49	2'd1: do <= do64[47:32];
	50	2'd2: do <= do64[31:16];
	51	2'd3: do <= do64[15:0];
	52	endcase
	53	end
	54
	55	always @(posedge sys_clk) begin
	56	if(vga_rst) begin
	57	produce = 2'd0;
	58	consume = 4'd0;
	59	level = 5'd0;
	60	end else begin
	61	if(stb) begin
	62	storage[produce] = di;
	63	produce = produce + 2'd1;
	64	level = level + 5'd4;
	65	end
	66	if(next) begin /* next should only be asserted when do_valid = 1 */
	67	consume = consume + 4'd1;
	68	level = level - 5'd1;
	69	end
	70	end
	71	end
	72
	73	assign do_valid = ~(level == 5'd0);
	74
	75	endmodule

lm32/logic/sakc/cores/vgafb/rtl/vgafb_graycounter.v
	1	//==========================================
	2	// Function : Code Gray counter.
	3	// Coder : Alex Claros F.
	4	// Date : 15/May/2005.
	5	//=======================================
	6
	7	`timescale 1ns/1ps
	8
	9	module vgafb_graycounter
	10	#(parameter COUNTER_WIDTH = 2)
	11
	12	(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
	13
	14	input wire Enable_in, //Count enable.
	15	input wire Clear_in, //Count reset.
	16
	17	input wire Clk);
	18
	19	/////////Internal connections & variables///////
	20	reg [COUNTER_WIDTH-1:0] BinaryCount;
	21
	22	/////////Code///////////////////////
	23
	24	always @ (posedge Clk)
	25	if (Clear_in) begin
	26	BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
	27	GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
	28	end
	29	else if (Enable_in) begin
	30	BinaryCount <= BinaryCount + 1;
	31	GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
	32	BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
	33	end
	34
	35	endmodule

lm32/logic/sakc/cores/vgafb/rtl/vgafb_pixelfeed.v
	1	/*
	2	* Milkymist VJ SoC
	3	* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
	4	*
	5	* This program is free software: you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation, version 3 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	module vgafb_pixelfeed #(
	19	parameter fml_depth = 26
	20	) (
	21	input sys_clk,
	22	/* We must take into account both resets :
	23	* VGA reset should not interrupt a pending FML request
	24	* but system reset should.
	25	*/
	26	input sys_rst,
	27	input vga_rst,
	28
	29	input [17:0] nbursts,
	30	input [fml_depth-1:0] baseaddress,
	31	output baseaddress_ack,
	32
	33	output reg [fml_depth-1:0] fml_adr,
	34	output reg fml_stb,
	35	input fml_ack,
	36	input [63:0] fml_di,
	37
	38	output pixel_valid,
	39	output [15:0] pixel,
	40	input pixel_ack
	41	);
	42
	43	/* FIFO that stores the 64-bit bursts and slices it in 16-bit words */
	44
	45	reg fifo_stb;
	46	wire fifo_valid;
	47
	48	vgafb_fifo64to16 fifo64to16(
	49	.sys_clk(sys_clk),
	50	.vga_rst(vga_rst),
	51
	52	.stb(fifo_stb),
	53	.di(fml_di),
	54
	55	.do_valid(fifo_valid),
	56	.do(pixel),
	57	.next(pixel_ack)
	58	);
	59
	60	assign pixel_valid = fifo_valid;
	61
	62	/* BURST COUNTER */
	63	reg sof;
	64	wire counter_en;
	65
	66	reg [17:0] bcounter;
	67
	68	always @(posedge sys_clk) begin
	69	if(vga_rst) begin
	70	bcounter <= 18'd1;
	71	sof <= 1'b1;
	72	end else begin
	73	if(counter_en) begin
	74	if(bcounter == nbursts) begin
	75	bcounter <= 18'd1;
	76	sof <= 1'b1;
	77	end else begin
	78	bcounter <= bcounter + 18'd1;
	79	sof <= 1'b0;
	80	end
	81	end
	82	end
	83	end
	84
	85	/* FML ADDRESS GENERATOR */
	86	wire next_address;
	87
	88	assign baseaddress_ack = sof & next_address;
	89
	90	always @(posedge sys_clk) begin
	91	if(sys_rst) begin
	92	fml_adr <= {fml_depth{1'b0}};
	93	end else begin
	94	if(next_address) begin
	95	if(sof)
	96	fml_adr <= baseaddress;
	97	else
	98	fml_adr <= fml_adr + {{fml_depth-6{1'b0}}, 6'd32};
	99	end
	100	end
	101	end
	102
	103	/* CONTROLLER */
	104	reg [2:0] state;
	105	reg [2:0] next_state;
	106
	107	parameter IDLE = 3'd0;
	108	parameter WAIT = 3'd1;
	109	parameter FETCH2 = 3'd2;
	110	parameter FETCH3 = 3'd3;
	111	parameter FETCH4 = 3'd4;
	112
	113	always @(posedge sys_clk) begin
	114	if(sys_rst)
	115	state <= IDLE;
	116	else
	117	state <= next_state;
	118	end
	119
	120	/*
	121	* Do not put spurious data into the FIFO if the VGA reset
	122	* is asserted and released during the FML access. Getting
	123	* the FIFO out of sync would result in distorted pictures
	124	* we really want to avoid.
	125	*/
	126
	127	reg ignore;
	128	reg ignore_clear;
	129
	130	always @(posedge sys_clk) begin
	131	if(vga_rst)
	132	ignore <= 1'b1;
	133	else if(ignore_clear)
	134	ignore <= 1'b0;
	135	end
	136
	137	reg next_burst;
	138
	139	assign counter_en = next_burst;
	140	assign next_address = next_burst;
	141
	142	always @(*) begin
	143	next_state = state;
	144
	145	fifo_stb = 1'b0;
	146	next_burst = 1'b0;
	147
	148	fml_stb = 1'b0;
	149	ignore_clear = 1'b0;
	150
	151	case(state)
	152	IDLE: begin
	153	if(~fifo_valid & ~vga_rst) begin
	154	/* We're in need of pixels ! */
	155	next_burst = 1'b1;
	156	ignore_clear = 1'b1;
	157	next_state = WAIT;
	158	end
	159	end
	160	WAIT: begin
	161	fml_stb = 1'b1;
	162	if(fml_ack) begin
	163	if(~ignore) fifo_stb = 1'b1;
	164	next_state = FETCH2;
	165	end
	166	end
	167	FETCH2: begin
	168	if(~ignore) fifo_stb = 1'b1;
	169	next_state = FETCH3;
	170	end
	171	FETCH3: begin
	172	if(~ignore) fifo_stb = 1'b1;
	173	next_state = FETCH4;
	174	end
	175	FETCH4: begin
	176	if(~ignore) fifo_stb = 1'b1;
	177	next_state = IDLE;
	178	end
	179	endcase
	180	end
	181
	182	endmodule

lm32/logic/sakc/cores/vgafb/test/Makefile
	1	SOURCES_PIXELFEED=tb_pixelfeed.v ../rtl/vgafb_pixelfeed.v ../rtl/vgafb_fifo64to16.v
	2
	3	all: pixelfeed
	4
	5	pixelfeed: $(SOURCES_PIXELFEED)
	6	cver $(SOURCES_PIXELFEED)
	7
	8	clean:
	9	rm -f verilog.log
	10
	11	.PHONY: clean pixelfeed

lm32/logic/sakc/cores/vgafb/test/tb_pixelfeed.v
	1	/*
	2	* Milkymist VJ SoC
	3	* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
	4	*
	5	* This program is free software: you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation, version 3 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	module tb_pixelfeed();
	19
	20	reg sys_clk;
	21	initial sys_clk = 1'b0;
	22	always #5 sys_clk = ~sys_clk;
	23
	24	reg sys_rst;
	25	reg vga_rst;
	26
	27	wire pixel_valid;
	28	wire fml_stb;
	29	wire [25:0] fml_adr;
	30
	31	initial begin
	32	sys_rst = 1'b1;
	33	vga_rst = 1'b1;
	34	#20 sys_rst = 1'b0;
	35	#20 vga_rst = 1'b0;
	36	end
	37
	38	vgafb_pixelfeed dut(
	39	.sys_clk(sys_clk),
	40	.sys_rst(sys_rst),
	41	.vga_rst(vga_rst),
	42
	43	.nbursts(18'd100),
	44	.baseaddress(26'd1024),
	45	.baseaddress_ack(),
	46
	47	.fml_adr(fml_adr),
	48	.fml_stb(fml_stb),
	49	.fml_ack(fml_stb),
	50	.fml_di(64'hcafebabedeadbeef),
	51
	52	.pixel_valid(pixel_valid),
	53	.pixel(),
	54	.pixel_ack(pixel_valid)
	55	);
	56
	57	always @(posedge sys_clk) $display("%x", fml_adr);
	58
	59	initial #600 $finish;
	60
	61	endmodule

lm32/logic/sakc/system_tb.v
51	51	$dumpvars(-1, dut);
52	52
53	53	// reset
54		#0 rst <= 1;
55		#80 rst <= 0;
	54	#0 rst <= 0;
	55	#80 rst <= 1;
56	56
57	57	#(tck*10000) $finish;
58	58	end

plasma/logic/mlite_pack.vhd
425	425	nwe : in std_logic;
426	426	noe : in std_logic;
427	427	ncs : in std_logic;
	428	irq_pin : in std_logic;
428	429	led : out std_logic);
429	430	end component; --plasma
430	431

plasma/logic/plasma.ucf
1		NET clk LOC = "P38";
	1	NET clk_in LOC = "P38";
2	2	NET rst_in LOC = "P30";
3	3	NET uart_write LOC = "P67";
4	4	NET uart_read LOC = "P68";
5		NET led LOC = "P44";
	5	NET led LOC = "P44";
	6	NET irq_pin LOC = "P71";
6	7
7	8	#ADDRESS BUS
8	9	NET "addr<12>" LOC = "P90";

plasma/logic/plasma.vhd
41	41	nwe : in std_logic;
42	42	noe : in std_logic;
43	43	ncs : in std_logic;
	44	irq_pin : in std_logic;
44	45	led : out std_logic
45	46	);
46	47	end; --entity plasma
...	...
147	148	variable bus_dec : std_logic_vector(6 downto 0);
148	149	begin
149	150	bus_dec := cpu_address(30 downto 28) & cpu_address(7 downto 4);
	151	-- if cpu_address(30 downto 28) = "000" then
	152	-- cpu_data_r <= ram_data_r;
	153	-- else
150	154	case bus_dec is
151	155	when "000----" => cpu_data_r <= ram_data_r;
152	156	when "0100000" => cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
...	...
158	162	when "0100110" => cpu_data_r <= ZERO;
159	163	when others => cpu_data_r <= ZERO;
160	164	end case;
	165	-- end if;
161	166	end process;
162	167
163	168	--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

plasma/logic/plasma_TB.vhd
28	28	signal nwe : std_logic;
29	29	signal noe : std_logic;
30	30	signal ncs : std_logic;
	31	signal irq_pin : std_logic;
31	32	signal led : std_logic;
32
33	33	signal TxD : std_logic;
34	34	signal RxD : std_logic;
35	35
...	...
51	51	nwe => nwe,
52	52	noe => noe,
53	53	ncs => ncs,
	54	irq_pin => irq_pin,
54	55	led => led
55	56	);
56	57

plasma/logic/ram.vhd
	1	---------------------------------------------------------------------
	2	-- TITLE: Random Access Memory
	3	-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
	4	-- DATE CREATED: 4/21/01
	5	-- FILENAME: ram.vhd
	6	-- PROJECT: Plasma CPU core
	7	-- COPYRIGHT: Software placed into the public domain by the author.
	8	-- Software 'as is' without warranty. Author liable for nothing.
	9	-- DESCRIPTION:
	10	-- Implements the RAM, reads the executable from either "code.txt",
	11	-- or for Altera "code[0-3].hex".
	12	-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
	13	---------------------------------------------------------------------
	14	library ieee;
	15	use ieee.std_logic_1164.all;
	16	use ieee.std_logic_misc.all;
	17	use ieee.std_logic_arith.all;
	18	use ieee.std_logic_unsigned.all;
	19	use ieee.std_logic_textio.all;
	20	use std.textio.all;
	21	use work.mlite_pack.all;
	22
	23	entity ram is
	24	generic(memory_type : string := "DEFAULT");
	25	port(clk : in std_logic;
	26	enable : in std_logic;
	27	write_byte_enable : in std_logic_vector(3 downto 0);
	28	address : in std_logic_vector(31 downto 2);
	29	data_write : in std_logic_vector(31 downto 0);
	30	data_read : out std_logic_vector(31 downto 0));
	31	end; --entity ram
	32
	33	architecture logic of ram is
	34	constant ADDRESS_WIDTH : natural := 13;
	35	begin
	36
	37	generic_ram:
	38	if memory_type /= "ALTERA_LPM" generate
	39	begin
	40	--Simulate a synchronous RAM
	41	ram_proc: process(clk, enable, write_byte_enable,
	42	address, data_write) --mem_write, mem_sel
	43	variable mem_size : natural := 2 ** ADDRESS_WIDTH;
	44	variable data : std_logic_vector(31 downto 0);
	45	subtype word is std_logic_vector(data_write'length-1 downto 0);
	46	type storage_array is
	47	array(natural range 0 to mem_size/4 - 1) of word;
	48	variable storage : storage_array;
	49	variable index : natural := 0;
	50	file load_file : text open read_mode is "code.txt";
	51	variable hex_file_line : line;
	52	begin
	53
	54	--Load in the ram executable image
	55	if index = 0 then
	56	while not endfile(load_file) loop
	57	--The following two lines had to be commented out for synthesis
	58	readline(load_file, hex_file_line);
	59	hread(hex_file_line, data);
	60	storage(index) := data;
	61	index := index + 1;
	62	end loop;
	63	end if;
	64
	65	if rising_edge(clk) then
	66	index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
	67	data := storage(index);
	68
	69	if enable = '1' then
	70	if write_byte_enable(0) = '1' then
	71	data(7 downto 0) := data_write(7 downto 0);
	72	end if;
	73	if write_byte_enable(1) = '1' then
	74	data(15 downto 8) := data_write(15 downto 8);
	75	end if;
	76	if write_byte_enable(2) = '1' then
	77	data(23 downto 16) := data_write(23 downto 16);
	78	end if;
	79	if write_byte_enable(3) = '1' then
	80	data(31 downto 24) := data_write(31 downto 24);
	81	end if;
	82	end if;
	83
	84	if write_byte_enable /= "0000" then
	85	storage(index) := data;
	86	end if;
	87	end if;
	88
	89	data_read <= data;
	90	end process;
	91	end generate; --generic_ram
	92
	93
	94	altera_ram:
	95	if memory_type = "ALTERA_LPM" generate
	96	signal byte_we : std_logic_vector(3 downto 0);
	97	begin
	98	byte_we <= write_byte_enable when enable = '1' else "0000";
	99	lpm_ram_io_component0 : lpm_ram_dq
	100	GENERIC MAP (
	101	intended_device_family => "UNUSED",
	102	lpm_width => 8,
	103	lpm_widthad => ADDRESS_WIDTH-2,
	104	lpm_indata => "REGISTERED",
	105	lpm_address_control => "REGISTERED",
	106	lpm_outdata => "UNREGISTERED",
	107	lpm_file => "code0.hex",
	108	use_eab => "ON",
	109	lpm_type => "LPM_RAM_DQ")
	110	PORT MAP (
	111	data => data_write(31 downto 24),
	112	address => address(ADDRESS_WIDTH-1 downto 2),
	113	inclock => clk,
	114	we => byte_we(3),
	115	q => data_read(31 downto 24));
	116
	117	lpm_ram_io_component1 : lpm_ram_dq
	118	GENERIC MAP (
	119	intended_device_family => "UNUSED",
	120	lpm_width => 8,
	121	lpm_widthad => ADDRESS_WIDTH-2,
	122	lpm_indata => "REGISTERED",
	123	lpm_address_control => "REGISTERED",
	124	lpm_outdata => "UNREGISTERED",
	125	lpm_file => "code1.hex",
	126	use_eab => "ON",
	127	lpm_type => "LPM_RAM_DQ")
	128	PORT MAP (
	129	data => data_write(23 downto 16),
	130	address => address(ADDRESS_WIDTH-1 downto 2),
	131	inclock => clk,
	132	we => byte_we(2),
	133	q => data_read(23 downto 16));
	134
	135	lpm_ram_io_component2 : lpm_ram_dq
	136	GENERIC MAP (
	137	intended_device_family => "UNUSED",
	138	lpm_width => 8,
	139	lpm_widthad => ADDRESS_WIDTH-2,
	140	lpm_indata => "REGISTERED",
	141	lpm_address_control => "REGISTERED",
	142	lpm_outdata => "UNREGISTERED",
	143	lpm_file => "code2.hex",
	144	use_eab => "ON",
	145	lpm_type => "LPM_RAM_DQ")
	146	PORT MAP (
	147	data => data_write(15 downto 8),
	148	address => address(ADDRESS_WIDTH-1 downto 2),
	149	inclock => clk,
	150	we => byte_we(1),
	151	q => data_read(15 downto 8));
	152
	153	lpm_ram_io_component3 : lpm_ram_dq
	154	GENERIC MAP (
	155	intended_device_family => "UNUSED",
	156	lpm_width => 8,
	157	lpm_widthad => ADDRESS_WIDTH-2,
	158	lpm_indata => "REGISTERED",
	159	lpm_address_control => "REGISTERED",
	160	lpm_outdata => "UNREGISTERED",
	161	lpm_file => "code3.hex",
	162	use_eab => "ON",
	163	lpm_type => "LPM_RAM_DQ")
	164	PORT MAP (
	165	data => data_write(7 downto 0),
	166	address => address(ADDRESS_WIDTH-1 downto 2),
	167	inclock => clk,
	168	we => byte_we(0),
	169	q => data_read(7 downto 0));
	170
	171	end generate; --altera_ram
	172
	173
	174	--For XILINX see ram_xilinx.vhd
	175
	176	end; --architecture logic

plasma/logic/ram_image.vhd
45	45	INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
46	46	INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
47	47	INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
48		INIT_04 => X"3c34ac343c34a42434a42434a42434a02434a02434a02434a02434a024343c27",
49		INIT_05 => X"8cac343caf008c34a730009434a330009034af008ca730009434a3300090ac34",
50		INIT_06 => X"82240c00142400100080afafaf270003ac3c1030008c343c0008af008c34af00",
51		INIT_07 => X"26240c2608240c00102c3002242400afafafaf2727038f8f8f0000140082260c",
52		INIT_08 => X"2703008f8c3c10000caf2730038c343c2703008f240caf2727038f8f8f8f0216",
53		INIT_09 => X"000000000000000000000000000000000024038c001424ac00008c243c3c243c",
54		INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
55		INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
56		INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
57		INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
58		INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
59		INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
60		INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
61		INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
62		INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
63		INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
64		INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
65		INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
66		INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
67		INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
68		INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
	48	INIT_04 => X"1c24001030008c24ac24ac9424003c00180003241c24a4248c0018ac2400003c",
	49	INIT_05 => X"a00024241028302400a03c24243c3c0003001030008cacac242400003c000300",
	50	INIT_06 => X"100010000c00102a0200260c24af08af2424240000afafafafaf270103001424",
	51	INIT_07 => X"240c001a001427038f8f8f8f8f8f8f02240c240c000824102c24142c24142e24",
	52	INIT_08 => X"008c34ac3c3c24240c3c240c3caf0cafafafafafafafafaf270008260c24240c",
	53	INIT_09 => X"3c240c3c240c3c240c3c3c3c3c3c3c003c3c0c003c240c3c3c1430248c3c1030",
	54	INIT_0A => X"0000142c2400000c240c3c270c260c260c260c260c240c3c240c3c240c3c240c",
	55	INIT_0B => X"000c000c00000c240c3c3c08240c3c000c000c8e0000008c0024003c3c102c26",
	56	INIT_0C => X"0200000010000c240c3c3c080002a208000c000c00000c240c3c0008923c08ae",
	57	INIT_0D => X"000010000c240c3c3c080216a002260c00000010000c240c3c3c080216260c90",
	58	INIT_0E => X"260c8c02240c3c00000010000c240c3c3c08240c000c000c0014002490020000",
	59	INIT_0F => X"120008a23c243c3c08240c3c021402240c000c260c8c021032021002240c000c",
	60	INIT_10 => X"3c083c0c003c000c0014343c000c240c3c3c0800003c0016260c262610000c3c",
	61	INIT_11 => X"008c343c3c08240c000c000c2608240c3c000c020c240c3c00000c240c3c020c",
	62	INIT_12 => X"82000c2682000c241400100082260c00240800100080afafaf270003ac001030",
	63	INIT_13 => X"038f8f8f8f0216260c2424142c3002242400afafafaf272703008f8f8f001400",
	64	INIT_14 => X"038c0014ac00248c3c24243c3c2703008f8c3c10000caf2730038c343c240827",
	65	INIT_15 => X"6531006e706e724f303030206e6569612020740a00616d20423a20616f430a24",
	66	INIT_16 => X"617965613673647475350a62697965340079617965330a7769796532006f6179",
	67	INIT_17 => X"0a3d6541206820720a3e00616f446f42316f4600753900736838006979656137",
	68	INIT_18 => X"00000000000000000000000000000000000037336820660a0d786e6e0a786e75",
69	69	INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
70	70	INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
71	71	INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
...	...
122	122	INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
123	123	INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
124	124	INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
125		INIT_04 => X"026482420264820264820264820264a2026582026482026482026482026403bd",
126		INIT_05 => X"62624202a2004262a242004262a242004262a20082a242004262a24200a28242",
127		INIT_06 => X"04040000511180400082b0b1bfbd00e044024042006243020000a2006263a200",
128		INIT_07 => X"108400100084000040824412111080b0b1b2bfbdbde0b0b1bf00004000021000",
129		INIT_08 => X"bde000bf4202400000bfbd42e0424202bde000bf0400bfbdbde0b0b1b2bf1211",
130		INIT_09 => X"000000000000000000040000802400800042e0a2006463404500624402054302",
131		INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
132		INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
133		INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
134		INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
135		INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
136		INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
137		INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
138		INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
139		INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
140		INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
141		INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
142		INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
143		INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
144		INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
145		INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
146		INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
	125	INIT_04 => X"c0c60040420062636284658205620205c000e084c0a582c6a200c0a202a20502",
	126	INIT_05 => X"c2e5070740a285634040036642020300e000404200828283020382040200e000",
	127	INIT_06 => X"54405300000040220312310090b000bf1514130000b1b2b3b4b5bd00e004c3c6",
	128	INIT_07 => X"040000208095bde0b0b1b2b3b4b5bf4004000400000090404282404282400250",
	129	INIT_08 => X"00434283020403840004840004b000b1b2b3b4b5b6b7bebfbd12003100040400",
	130	INIT_09 => X"024400024400024400021e171615144002060000048400041543420382146063",
	131	INIT_0A => X"0000404242400000440002c400e400c400a40084004400024400024400024400",
	132	INIT_0B => X"4000400040000044000202004400024000000044008000444383030402406203",
	133	INIT_0C => X"4200004040000044000202000040500040004000400000440002000044020050",
	134	INIT_0D => X"0040400000440002020000136251100000004040000044000202000011100044",
	135	INIT_0E => X"300044504400020000404000004400020200040040000000a0a683a543420000",
	136	INIT_0F => X"1100005013111202004400020060130400400030004450400200601304004000",
	137	INIT_10 => X"0200060000040000004363030000440002020000400240535200101040000002",
	138	INIT_11 => X"0062a30502000400400000000300440002400040004400024000004400020000",
	139	INIT_12 => X"02400010020000045100400002100040110080400082b1bfb0bd00e0a4004042",
	140	INIT_13 => X"e0b0b1b2bf12111000646440624312111080bfb0b1b2bdbde000b0b1bf004000",
	141	INIT_14 => X"e0a20083404584820563440302bde000bf6203400000bfbd42e06263030400bd",
	142	INIT_15 => X"6d2e007374752074303078616b206d7262666957007320666f0a006474205342",
	143	INIT_16 => X"64206d772e73646f6d2e007974206d2e007464206d2e006f74206d2e00726420",
	144	INIT_17 => X"56207364006569654120007320526d2032702e006d2e0075652e0074206d772e",
	145	INIT_18 => X"0000000000000000000000000000000000003834207769430a3e2074433e2065",
	146	INIT_19 => X"0000000000000000000000000000000000000004000080240080000000000000",
147	147	INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
148	148	INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
149	149	INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
...	...
195	195
196	196	RAMB16_S9_inst2 : RAMB16_S9
197	197	generic map (
198		INIT_00 => X"00000000000000000000000000000000ff00000000ff18000600060004008400",
199		INIT_01 => X"000000000000000000000000000000000000012000002000d800d800ff700000",
	198	INIT_00 => X"00000000000000000000000000000000ff00000100ff18000e000e000c008c00",
	199	INIT_01 => X"000000000000000000000000000000000000022000002000d800d800ff700000",
200	200	INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
201	201	INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
202		INIT_04 => X"31030030300300220200210200200200000400000400000400000400000420ff",
203		INIT_05 => X"000055550000000300ff000002000000000400000000ff000002000000000031",
204		INIT_06 => X"00000000000080000000000000ff10000020ff00000000200000000000000000",
205		INIT_07 => X"ff0000ff0100000000000010ff009000000000ff00000000001000ff00000000",
206		INIT_08 => X"000000000020ff000100ff000000002000000000000000ff00000000000010ff",
207		INIT_09 => X"000000000000000000200000002028000000000000ff00001000000400100400",
208		INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
209		INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
210		INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
211		INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
212		INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
213		INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
214		INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
215		INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
216		INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
217		INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
218		INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
219		INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
220		INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
221		INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
222		INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
223		INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
	202	INIT_04 => X"ffff00ff00000000000000000018301800000000ff0000ff0000000000282830",
	203	INIT_05 => X"001000000000000c4000000c0c0000000000ff00000000000000202030000000",
	204	INIT_06 => X"002000000200000090190002ff00000000000088900000000000ff100021ffff",
	205	INIT_07 => X"0002000080ff00000000000000000010000200020000ff0000ffff00ffff00ff",
	206	INIT_08 => X"000000002030000a02000a02000002000000000000000000ff9100ff02000002",
	207	INIT_09 => X"000a02000a02000a02000000000000f810000028100a02000000ff3c00000000",
	208	INIT_0A => X"90000000ff8000020b02000b020b020b020b020b020b02000b02000b02000b02",
	209	INIT_0B => X"200280002000000b020000010b0200200200000000000000100c100000ff00ff",
	210	INIT_0C => X"10108088ff00000c0200000100f80001200280002000000b0200000100000100",
	211	INIT_0D => X"28300000000c0200000188ff00180002888098ff00000c0200000110ff000200",
	212	INIT_0E => X"000000100c02008880980000000c0200000100022002000010ff200000101020",
	213	INIT_0F => X"0080020010271000010c020088ff180002200200000010ff0088001800022002",
	214	INIT_10 => X"000100002810200000ff561200000c0200000100f81080ff0002ff00ff000210",
	215	INIT_11 => X"000000200001000220022000ff010b0200200220000b02009000000b02002002",
	216	INIT_12 => X"0020020000000200ff00000000000220000280000000000000ff00000010ff00",
	217	INIT_13 => X"000000000010ffff02000000000010ff009000000000ff00001000000000ff00",
	218	INIT_14 => X"000000ff00100000100c0c0000000000000020ff000200ff0000000020000200",
	219	INIT_15 => X"6f20003a69204d680a303174656c6179696f6e61006866726f0000656c624100",
	220	INIT_16 => X"0a726f20200a72207020007465776f20006520726f20007265776f2000642072",
	221	INIT_17 => X"6100736400786e736400006866202066387920007020006d63200065776f2020",
	222	INIT_18 => X"0404040404070404070606060606060505003e353169726f002068206f206820",
	223	INIT_19 => X"0000000000000000000000000000000000000020000000202800000804040404",
224	224	INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
225	225	INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
226	226	INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
...	...
272	272
273	273	RAMB16_S9_inst3 : RAMB16_S9
274	274	generic map (
275		INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a00c800e000dc00d001",
276		INIT_01 => X"504c4844403c3834302c2824201c18141000082410200060125c1058fc005450",
	275	INIT_00 => X"4c4844403c3834302c2824201c181410980e000704fd2a00b800d000b400b001",
	276	INIT_01 => X"504c4844403c3834302c2824201c18141000812410200060125c1058fc005450",
277	277	INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
278	278	INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
279		INIT_04 => X"31340030303000221400211200201000141400131300121200111100101000f8",
280		INIT_05 => X"000055550400003802ff00001800ff00001804000002ff00001600ff00000031",
281		INIT_06 => X"000dc800030a210d0000101418e021080000fc020000200000c6040000200400",
282		INIT_07 => X"fc57c8fc0030c800050a0f06fc1c211014181ce020081014182100f6000001c8",
283		INIT_08 => X"180800100000fd001010e801080020001808001049c810e820081014181c06f4",
284		INIT_09 => X"000000000000000000001010200000207084080000fa0400210000dc0000bc00",
285		INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
286		INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
287		INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
288		INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
289		INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
290		INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
291		INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
292		INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
293		INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
294		INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
295		INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
296		INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
297		INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
298		INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
299		INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
300		INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
	279	INIT_04 => X"f4fe00fc80000004000200004021004011000802fb0400fe00000700ff214000",
	280	INIT_05 => X"00213037020a0fbf210800c7c00000000800fc8000000000d020214000000800",
	281	INIT_06 => X"0c210e00880012102100013cc910db28080d0a212114181c2024d0210802f7ff",
	282	INIT_07 => X"083c000821d930081014181c202428210a3c0d3c00d4a9111a9fed1abff10ad0",
	283	INIT_08 => X"000050000000ff984600844600109314181c2024282c3034c802d8ff3c08203c",
	284	INIT_09 => X"00f84600e04600b0460000000000000900028021009c4600000cff1c00001001",
	285	INIT_0A => X"2100c20ad0210088d84600b446a846984680466c465846004046002846001046",
	286	INIT_0B => X"214621b12100c5fc46000037244600214600b10000080000213c800000d416cf",
	287	INIT_0C => X"212121219a00c50c4600003700090036214621b12100c5fc4600006d00003700",
	288	INIT_0D => X"21217600c50c4600003721fb002101882121218900c50c4600003721fb013c00",
	289	INIT_0E => X"04b100211c46002121211e00c50c460000370a3c214600b121fb210100212121",
	290	INIT_0F => X"0b21010010100000371c460021f42b203c214604b10021f00f210e2b203c2146",
	291	INIT_10 => X"0037028f210021a3001f783400c5204600003700090021f30188ff01fb008300",
	292	INIT_11 => X"0000200000370a3c214621b1cf61244600214621b1f046002100c5dc4600213c",
	293	INIT_12 => X"00213c0100003c0df8000d0000013c210a5721160000141810e000080021fc02",
	294	INIT_13 => X"081014181c06f8fc3c5730020a0f06fc1c211c101418e020082110141800f500",
	295	INIT_14 => X"080000fb0021040000b4940000180800100000fd008310e80108002000493c20",
	296	INIT_15 => X"724d000a6f4f656500303020646967206e726769000a6c6f740000726f6f4b84",
	297	INIT_16 => X"0065726d52006561204a00652072724d000a6265724d00642072724d000a7765",
	298	INIT_17 => X"6c002072003e20736400000a6c7444724b2043000a44000a6b43000a72726d52",
	299	INIT_18 => X"d8d8d8d8d8e4d8d840e09c5848180cd8b000203632746d6e0000656975006569",
	300	INIT_19 => X"0000000000000000000000000000000000000000101020000020703cd8d8d8d8",
301	301	INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
302	302	INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
303	303	INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",

plasma/logic/tbench.vhd
	1	---------------------------------------------------------------------
	2	-- TITLE: Test Bench
	3	-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
	4	-- DATE CREATED: 4/21/01
	5	-- FILENAME: tbench.vhd
	6	-- PROJECT: Plasma CPU core
	7	-- COPYRIGHT: Software placed into the public domain by the author.
	8	-- Software 'as is' without warranty. Author liable for nothing.
	9	-- DESCRIPTION:
	10	-- This entity provides a test bench for testing the Plasma CPU core.
	11	---------------------------------------------------------------------
	12	library ieee;
	13	use ieee.std_logic_1164.all;
	14	use work.mlite_pack.all;
	15	use ieee.std_logic_unsigned.all;
	16
	17	entity tbench is
	18	end; --entity tbench
	19
	20	architecture logic of tbench is
	21	constant memory_type : string :=
	22	"TRI_PORT_X";
	23	-- "DUAL_PORT_";
	24	-- "ALTERA_LPM";
	25	-- "XILINX_16X";
	26
	27	constant log_file : string :=
	28	-- "UNUSED";
	29	"output.txt";
	30
	31	signal clk : std_logic := '1';
	32	signal reset : std_logic := '1';
	33	signal interrupt : std_logic := '0';
	34	signal mem_write : std_logic;
	35	signal address : std_logic_vector(31 downto 2);
	36	signal data_write : std_logic_vector(31 downto 0);
	37	signal data_read : std_logic_vector(31 downto 0);
	38	signal pause1 : std_logic := '0';
	39	signal pause2 : std_logic := '0';
	40	signal pause : std_logic;
	41	signal no_ddr_start: std_logic;
	42	signal no_ddr_stop : std_logic;
	43	signal byte_we : std_logic_vector(3 downto 0);
	44	signal uart_write : std_logic;
	45	signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
	46	begin --architecture
	47	--Uncomment the line below to test interrupts
	48	interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
	49
	50	clk <= not clk after 50 ns;
	51	reset <= '0' after 500 ns;
	52	pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
	53	pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
	54	pause <= pause1 or pause2;
	55	gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
	56	gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
	57	gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
	58	gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
	59
	60	u1_plasma: plasma
	61	generic map (memory_type => memory_type,
	62	ethernet => '1',
	63	use_cache => '1',
	64	log_file => log_file)
	65	PORT MAP (
	66	clk => clk,
	67	reset => reset,
	68	uart_read => uart_write,
	69	uart_write => uart_write,
	70
	71	address => address,
	72	byte_we => byte_we,
	73	data_write => data_write,
	74	data_read => data_read,
	75	mem_pause_in => pause,
	76	no_ddr_start => no_ddr_start,
	77	no_ddr_stop => no_ddr_stop,
	78
	79	gpio0_out => open,
	80	gpioA_in => gpioA_in);
	81
	82	dram_proc: process(clk, address, byte_we, data_write, pause)
	83	constant ADDRESS_WIDTH : natural := 16;
	84	type storage_array is
	85	array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
	86	std_logic_vector(31 downto 0);
	87	variable storage : storage_array;
	88	variable data : std_logic_vector(31 downto 0);
	89	variable index : natural := 0;
	90	begin
	91	index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
	92	data := storage(index);
	93
	94	if byte_we(0) = '1' then
	95	data(7 downto 0) := data_write(7 downto 0);
	96	end if;
	97	if byte_we(1) = '1' then
	98	data(15 downto 8) := data_write(15 downto 8);
	99	end if;
	100	if byte_we(2) = '1' then
	101	data(23 downto 16) := data_write(23 downto 16);
	102	end if;
	103	if byte_we(3) = '1' then
	104	data(31 downto 24) := data_write(31 downto 24);
	105	end if;
	106
	107	if rising_edge(clk) then
	108	if address(30 downto 28) = "001" and byte_we /= "0000" then
	109	storage(index) := data;
	110	end if;
	111	end if;
	112
	113	if pause = '0' then
	114	data_read <= data;
	115	end if;
	116	end process;
	117
	118
	119	end; --architecture logic

Download the corresponding diff file

Branches:
master

Hardware Design: SIE

Hardware Design: SIE Commit Details

Change Details

interactive