Date:2010-10-12 17:21:30 (9 years 1 month ago)
Author:C├ęsar Pedraza
Commit:5fbd9db02f9bc966892cf290383d940e7e990da4
Message:fixed logic for Evalfit peripheral

Files: Examples/ehw4/logic/evalfit_peripheral.vhd (15 diffs)
Examples/ehw4/logic/reg_bank.v (3 diffs)

Change Details

Examples/ehw4/logic/evalfit_peripheral.vhd
33-- Evalua un arbol de 5 pentarboles, por ahora es valido hasta para *** 14 variables ***
44-- Funciona hasta con 14 vars.
55-- mapa:
6    -- 0 - 0x3F Cromosoma
6    -- 0 - 0x3F Cromosoma (cada uno con 64-bit)
77    -- 0x40 - 0x13F Objetivo. 16384 bits. Se empieza por el bit 0 MSB.
88
99
10    -- bit bit Contenido
10-- Mapa de cromosoma:
11    -- bit bit Contenido
1112    -- 28 a 31 Nivel del arbol
12    -- 32 a 47 LUT o tabla del arbol
13    -- 48 a 63 Variables de entrada del arbol (4 bits por variable)
13    -- 32 a 47 LUT o tabla del arbol LUT(32)MSB, LUT(47)LSB,
14    -- 48 a 63 Variables de entrada del arbol (4 bits por variable) 48-51 MSB, 60-63 LSB
1415
1516library IEEE;
1617use IEEE.STD_LOGIC_1164.ALL;
...... 
2525    Port ( clk, reset, habilita: in STD_LOGIC;
2626            maxcombs : in STD_LOGIC_VECTOR (0 to 15);
2727              nivel_max : in STD_LOGIC_VECTOR (0 to 3);
28               peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63);
29            peripheral_mem_en : out std_logic;
30               peripheral_mem_out : out STD_LOGIC_VECTOR (0 to 63);
31            peripheral_mem_we : out STD_LOGIC;
32            peripheral_mem_addr : out STD_LOGIC_VECTOR (0 to 8);
33            evalfit3_estado : out std_logic_vector(0 to 7);
28         peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63);
29            peripheral_mem_en : out std_logic;
30         peripheral_mem_out: out STD_LOGIC_VECTOR (0 to 63);
31            peripheral_mem_we : out STD_LOGIC;
32            peripheral_mem_addr: out STD_LOGIC_VECTOR (0 to 8);
33            evalfit3_estado : out std_logic_vector(0 to 15);
3434            errores : out STD_LOGIC_VECTOR (0 to 15);
3535            fin_ack : out std_logic;
3636            reg0_s : out STD_LOGIC_VECTOR (0 to 31);
...... 
5454    when "0101" => return ent(10);
5555    when "0110" => return ent(9);
5656    when "0111" => return ent(8);
57    when "1000" => return ent(7);
57     when "1000" => return ent(7);
5858    when "1001" => return ent(6);
5959    when "1010" => return ent(5);
6060    when "1011" => return ent(4);
...... 
9595signal nivel, nivel_sig, nivel_reg: std_logic_vector(0 to 3);
9696signal c1, c1_sig, c2, c2_sig, c3, c3_sig, c4, c4_sig: std_logic_vector(0 to 1);
9797signal conta, conta_sig, conta2, conta2_sig: std_logic_vector(0 to 15);
98signal estado_evalf3, estado_evalf3_sig: std_logic_vector(0 to 7);
98signal estado_evalf3, estado_evalf3_sig: std_logic_vector(0 to 15);
9999signal peripheral_mem_addr_aux, peripheral_mem_addr_sig, peripheral_mem_addr_crom_sig,peripheral_mem_addr_crom : STD_LOGIC_VECTOR (0 to 8);
100100
101101begin
...... 
132132peripheral_mem_en <= '0';
133133errores_sig <= errores_aux;
134134nivel_sig <= nivel_reg;
135estado_evalf3_sig <= x"FF";
135estado_evalf3_sig <= x"FFFF";
136136case ep is
137137    when reset1 => --poner la memoria a 0000
138138            WE_n2_sig <= "1111";
139139            WE_n3_sig <= "1111";
140140            WE_n4_sig <= "1111";
141141            conta2_sig <= (others => '0');
142            estado_evalf3_sig <= x"0001";
142143            es <= reset2;
143144    when reset2 =>
144145            DI_n2 <= "0000";
145146            DI_n3 <= "0000";
146147            DI_n4 <= "0000";
148            estado_evalf3_sig <= x"0002";
147149            if(conta2 = maxcombs)then
148150                WE_n2_sig <= "0000";
149151                WE_n3_sig <= "0000";
...... 
173175                es <= proceso;
174176                peripheral_mem_en <= '1';
175177            end if;
176            estado_evalf3_sig <= x"01";
178            estado_evalf3_sig <= x"0003";
177179
178180    when proceso =>
179181            peripheral_mem_en <= '1';
...... 
206208            peripheral_mem_addr_sig <= peripheral_mem_addr_aux + 1;
207209            peripheral_mem_addr_crom_sig <= peripheral_mem_addr_aux + 1;
208210            nivel_sig <= nivel;
209            estado_evalf3_sig <= x"02";
211            estado_evalf3_sig <= peripheral_mem_in(48 to 63);--x"FFE" & nivel;----x"02";
210212
211213    when n1 =>
212214            peripheral_mem_en <= '1';
213215            c1_sig <= c1 + 1;
214216            peripheral_mem_addr_sig <= peripheral_mem_addr_aux;
215217            es <= proceso;
216            estado_evalf3_sig <= x"03";
218            estado_evalf3_sig <= x"0004";
217219
218220    when n2 =>
219221            WE_n2_sig(conv_integer(c2)) <= '1';
...... 
222224            peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- esto es para que evalue el pentarbol y guarde en memoria la salida
223225            es <= precuenta;
224226            conta2_sig <= (others => '0');
225            estado_evalf3_sig <= x"04";
227            estado_evalf3_sig <= x"0005";
226228
227229    when n3 =>
228230            WE_n3_sig(conv_integer(c3)) <= '1';
...... 
231233            peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));--
232234            es <= precuenta;
233235            conta2_sig <= (others => '0');
234            estado_evalf3_sig <= x"05";
236            estado_evalf3_sig <= x"0006";
235237
236238    when n4 =>
237239            WE_n4_sig(conv_integer(c4)) <= '1';
...... 
240242            peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));--
241243            es <= precuenta;
242244            conta2_sig <= (others => '0');
243            estado_evalf3_sig <= x"06";
245            estado_evalf3_sig <= x"0007";
244246
245247    when precuenta =>
246248            WE_n2_sig <= WE_n2;
...... 
254256            conta_sig <= conta;
255257            conta2_sig <= conta + 1;
256258            es <= cuenta;
257            estado_evalf3_sig <= x"07";
259            estado_evalf3_sig <= x"0008";
258260
259261    when cuenta =>
260262            DI_n2(conv_integer(c2)) <= salida_nivel(2);
...... 
292294                errores_sig <= errores_aux;
293295            end if;
294296
295            estado_evalf3_sig <= x"08";
297            estado_evalf3_sig <= x"0009";
296298
297299    when final =>
298300             if(nivel_reg = "0010")then
...... 
305307            peripheral_mem_en <= '1';
306308            peripheral_mem_addr_sig <= peripheral_mem_addr_crom;
307309            es <= proceso;
308            estado_evalf3_sig <= x"09";
310            estado_evalf3_sig <= x"000A";
309311
310312    when final2 =>
311313            if(habilita = '1') then
...... 
314316                es <= inicio;
315317            end if;
316318            fin_ack_sig <= '1';
317            estado_evalf3_sig <= x"0A";
319            estado_evalf3_sig <= x"000B";
318320    when others => es <= inicio;
319321
320322    end case;
...... 
346348         peripheral_mem_addr_crom <= "000000000";
347349        errores_aux <= (others => '0');
348350        nivel_reg <= "0000";
349        estado_evalf3 <= x"00";
351        estado_evalf3 <= x"0000";
350352    elsif(rising_edge(clk))then
351353        ep <= es;
352354        c1 <= c1_sig;
Examples/ehw4/logic/reg_bank.v
2929    // Read control
3030    always @(posedge clk)
3131      if(reset)
32          rdBus = 8'h00;
32         rdBus = 8'h00;
3333      else begin
34        rdBus = reg_bank[address];
34            rdBus = reg_bank[address];
3535      end
3636
37
3837     // Store Inputs
3938    always @(posedge clk)
4039     begin
...... 
6766        reg_bank[20] = error[7:0];
6867        reg_bank[21] = error[15:8];
6968
70        reg_bank[22] = { 4'b0, status};
69        reg_bank[22] = {4'b0, status};
7170
7271// reg_bank[23] = regMT[7:0];
7372// reg_bank[24] = regMT[15:8];
...... 
7675      end
7776     end
7877
79
8078     assign max_com[7:0] = reg_bank[26];
8179     assign max_com[15:8] = reg_bank[27];
8280     assign max_lev = reg_bank[28];

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