Date:2010-05-01 05:21:55 (10 years 4 months ago)
Author:Carlos Camargo
Commit:622f59856f0e72d1a3ad6cc581fc8a125bcf9327
Message:Adding a simple plasma example read write char short int, adding simulations for this example

Files: Examples/blink/logic/simulation/blink_TB.do (1 diff)
plasma/Makefile (1 diff)
plasma/bootldr/bootldr.c (1 diff)
plasma/doc/char_short_int_read.png (0 diffs)
plasma/doc/char_write.png (0 diffs)
plasma/doc/short_write.png (0 diffs)
plasma/gpio/Makefile (1 diff)
plasma/gpio/gpio.c (1 diff)
plasma/logic/Makefile (3 diffs)
plasma/logic/mlite_pack.vhd (2 diffs)
plasma/logic/plasma.vhd (9 diffs)
plasma/logic/ram_image.vhd (4 diffs)
plasma/logic/simulation/output.txt (1 diff)
plasma/logic/simulation/plasma_3e_TB.do (1 diff)
plasma/logic/simulation/transcript (1 diff)
plasma/logic/tbench.vhd (1 diff)

Change Details

Examples/blink/logic/simulation/blink_TB.do
11vlib work
22vlog +acc "../blink.v"
33vlog +acc "../blink_TB.v"
4vlog +acc "/opt/cad/Xilinx/verilog/src/glbl.v"
4vlog +acc "glbl.v"
55vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver blink_TB_v glbl
66view wave
77do wave.do
plasma/Makefile
11TARGET = bootldr
2DIRS = tools bootldr logic
2DIRS = tools bootldr logic gpio
33
44all:
55    for n in $(DIRS); do $(MAKE) -C $$n || exit 1; done
plasma/bootldr/bootldr.c
122122
123123   DdrInit(); //Harmless if SDRAM instead of DDR
124124
125   puts("\nGreetings from the bootloader ");
125   puts("\n1233456Greetings from the bootloader ");
126126   puts(__DATE__);
127127   puts(" ");
128128   puts(__TIME__);
plasma/doc/char_short_int_read.png
plasma/doc/char_write.png
plasma/doc/short_write.png
plasma/gpio/Makefile
1VHDL_DIR = ../logic
2TOOLS_DIR = ../bin
3LIB_DIR = ../lib
4TARGET = gpio
5CROSS = mips-elf
6GCC = $(CROSS)-gcc
7AS = $(CROSS)-as
8LD = $(CROSS)-ld
9DUMP = $(CROSS)-objdump
10OBJCOPY = $(CROSS)-objcopy
11INC_PATH = ../include
12CFLAGS = -O2 -I$(INC_PATH) -Wall -c -s
13ILDFLAGS = -Ttext 0 -eentry -Map $@.map -s -N
14LDFLAGS = -Ttext 0x10000000 -eentry -Map $@.map -s -N
15
16#Internal RAM 0x00
17#External RAM 0x10000000
18
19vpath %.c $(LIB_DIR)
20vpath %.S $(LIB_DIR)
21
22.c.o:
23    $(GCC) $(CFLAGS) $<
24.S.o:
25    $(AS) -o $@ $<
26
27all: $(TARGET)
28
29clean:
30    -rm -rf *.o *.txt *.map *.lst *.bin opcodes_iram opcodes_ram test bootldr $(TARGET)
31
32$(TARGET): crt0.o $(TARGET).o no_os.o ddr_init.o
33    $(LD) $(ILDFLAGS) -o $@ $^
34    $(OBJCOPY) -I elf32-big -O binary $@ $@.bin
35
36vhdl_mem: $(TARGET)
37    $(TOOLS_DIR)/ramimage $(VHDL_DIR)/ram_xilinx.vhd $^.bin $(VHDL_DIR)/ram_image.vhd
38
39upload: $(TARGET)
40    sudo cat $^.bin > /dev/ttyUSB0
41
42run: $(TARGET)
43    $(TOOLS_DIR)/mlite $^.bin
plasma/gpio/gpio.c
1#include "plasma.h"
2
3#define MemoryRead(A) (*(volatile unsigned long*)(A))
4#define MemoryWrite(A,V) *(volatile unsigned long*)(A)=(V)
5
6typedef unsigned long uint32;
7typedef unsigned short uint16;
8
9
10int main(void)
11{
12  volatile unsigned char *data8;
13  volatile unsigned short *data16;
14  volatile unsigned int *data32;
15
16  unsigned char test8;
17  unsigned short test16;
18  unsigned int test32, tmp;
19
20  data8 = (unsigned char *)(0x20001000);
21  data16 = (unsigned short *)(0x20002000);
22  data32 = (unsigned int *)(0x20003000);
23
24  *data8 = 0x10;
25  data8++;
26  *data8 = 0x11;
27  data8++;
28  *data8 = 0x12;
29  data8++;
30  *data8 = 0x13;
31  data8++;
32  *data8 = 0x14;
33
34  *data16 = 0x2020;
35  data16++;
36  *data16 = 0x2121;
37  data16++;
38  *data16 = 0x2222;
39  data16++;
40
41  *data32 = 0x30303030;
42
43  test8 = *data8;
44  test16 = *data16;
45  test32 = *data32;
46  data8 += 4;
47  data16++;
48  data32++;
49  test8 = *data8;
50  test16 = *data16;
51  test32 = *data32;
52
53
54
55  tmp = test8 + test16 + test32;
56
57  *data32 = 0xAAAAAAAA;
58
59  return 0;
60}
61
plasma/logic/Makefile
1DESIGN = plasma_3e
1DESIGN = plasma
22PINS = $(DESIGN).ucf
33DEVICE = xc3s500e-fg320-4
44BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
...... 
1111SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
1212
1313SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd plasma_3e.vhd ram_image.vhd
14
15
16
1714
1815all: bits
1916
...... 
2219clean:
2320    rm -rf *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
2421    rm -rf *.bit rm -rf simulation/work simulation/*wlf
22    rm -rf simulation/transcript
2523
2624clean-build:
2725    rm -rf build
plasma/logic/mlite_pack.vhd
415415   component plasma
416416      generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
417417              log_file : string := "UNUSED";
418              ethernet : std_logic := '0';
419418              use_cache : std_logic := '0');
420419      port(clk : in std_logic;
421420           reset : in std_logic;
...... 
427426           data_write : out std_logic_vector(31 downto 0);
428427           data_read : in std_logic_vector(31 downto 0);
429428           mem_pause_in : in std_logic;
430           no_ddr_start : out std_logic;
431           no_ddr_stop : out std_logic;
432429
433430           gpio0_out : out std_logic_vector(31 downto 0);
434431           gpioA_in : in std_logic_vector(31 downto 0));
plasma/logic/plasma.vhd
2121-- 0x20000040 GPIO0 Out Clear bits
2222-- 0x20000050 GPIOA In
2323-- 0x20000060 Counter
2424-- IRQ bits:
2525-- 7 GPIO31
2626-- 6 ^GPIO31
2727-- 3 Counter(18)
2828-- 2 ^Counter(18)
2929-- 1 ^UartWriteBusy
...... 
3936entity plasma is
4037   generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
4138           log_file : string := "UNUSED";
42           ethernet : std_logic := '0';
4339           use_cache : std_logic := '0');
4440   port(clk : in std_logic;
4541        reset : in std_logic;
...... 
5147        byte_we : out std_logic_vector(3 downto 0);
5248        data_write : out std_logic_vector(31 downto 0);
5349        data_read : in std_logic_vector(31 downto 0);
54        mem_pause_in : in std_logic;
55        no_ddr_start : out std_logic;
56        no_ddr_stop : out std_logic;
57
50        mem_pause_in : in std_logic;
5851        gpio0_out : out std_logic_vector(31 downto 0);
5952        gpioA_in : in std_logic_vector(31 downto 0));
6053end; --entity plasma
...... 
6962   signal cpu_pause : std_logic;
7063
7164   signal data_read_uart : std_logic_vector(7 downto 0);
72   signal write_enable : std_logic;
73   signal eth_pause_in : std_logic;
74   signal eth_pause : std_logic;
65   signal write_enable : std_logic;
7566   signal mem_busy : std_logic;
7667
7768   signal enable_misc : std_logic;
7869   signal enable_uart : std_logic;
7970   signal enable_uart_read : std_logic;
8071   signal enable_uart_write : std_logic;
81   signal enable_eth : std_logic;
8272
8373   signal gpio0_reg : std_logic_vector(31 downto 0);
8474   signal uart_write_busy : std_logic;
...... 
8676   signal irq_mask_reg : std_logic_vector(7 downto 0);
8777   signal irq_status : std_logic_vector(7 downto 0);
8878   signal irq : std_logic;
89   signal irq_eth_rec : std_logic;
90   signal irq_eth_send : std_logic;
9179   signal counter_reg : std_logic_vector(31 downto 0);
9280
9381   signal ram_enable : std_logic;
...... 
9886
9987   signal cache_check : std_logic;
10088   signal cache_checking : std_logic;
101   signal cache_miss : std_logic;
89   signal cache_miss : std_logic;
10290   signal cache_hit : std_logic;
10391
10492begin --architecture
10593   write_enable <= '1' when cpu_byte_we /= "0000" else '0';
106   mem_busy <= eth_pause or mem_pause_in;
107   cache_hit <= cache_checking and not cache_miss;
108   cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
109      cache_miss or --Cache wait
110      (cpu_address(28) and not cache_hit and mem_busy); --DDR or flash --DDR in use
111   irq_status <= gpioA_in(31) & not gpioA_in(31) &
112                 irq_eth_send & irq_eth_rec &
113                 counter_reg(18) & not counter_reg(18) &
114                 not uart_write_busy & uart_data_avail;
115   irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
116   gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
117   gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
94   mem_busy <= mem_pause_in;
95   cache_hit <= cache_checking and not cache_miss;
96   cpu_pause <= '0'; --(uart_write_busy and enable_uart and write_enable) or --UART busy
97-- cache_miss or --Cache wait
98-- (cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
99-- gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
100-- gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
118101
119102   enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
120103   enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
121104   enable_uart_read <= enable_uart and not write_enable;
122105   enable_uart_write <= enable_uart and write_enable;
123   enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
124106   cpu_address(1 downto 0) <= "00";
125107
126108   u1_cpu: mlite_cpu
...... 
161143         cache_check => cache_check, --Stage1: address_next in first 2MB DDR
162144         cache_checking => cache_checking, --Stage2
163145         cache_miss => cache_miss); --Stage3
164   end generate; --opt_cache2
165
166   no_ddr_start <= not eth_pause and cache_checking;
167   no_ddr_stop <= not eth_pause and cache_miss;
168   eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
146   end generate; --opt_cache2
169147
170148   misc_proc: process(clk, reset, cpu_address, enable_misc,
171149      ram_data_r, data_read, data_read_uart, cpu_pause,
...... 
225203      end if;
226204   end process;
227205
228   ram_enable <= '1' when address_next(30 downto 28) = "000" or
229                  cache_check = '1' or cache_miss = '1' else '0';
206   ram_enable <= '1' when address_next(30 downto 28) = "000" or cache_check = '1' or cache_miss = '1' else '0';
230207   ram_byte_we <= byte_we_next when cache_miss = '0' else "1111";
231208   ram_address(31 downto 13) <= ZERO(31 downto 13);
232209   ram_address(12 downto 2) <= (address_next(12) or cache_check) & address_next(11 downto 2)
...... 
258235         busy_write => uart_write_busy,
259236         data_avail => uart_data_avail);
260237
261   dma_gen: if ethernet = '0' generate
262238      address <= cpu_address(31 downto 2);
263239      byte_we <= cpu_byte_we;
264240      data_write <= cpu_data_w;
265      eth_pause <= '0';
266241      gpio0_out(28 downto 24) <= ZERO(28 downto 24);
267      irq_eth_rec <= '0';
268      irq_eth_send <= '0';
269   end generate;
270
271   dma_gen2: if ethernet = '1' generate
272   u4_eth: eth_dma
273      port map(
274         clk => clk,
275         reset => reset,
276         enable_eth => gpio0_reg(24),
277         select_eth => enable_eth,
278         rec_isr => irq_eth_rec,
279         send_isr => irq_eth_send,
280
281         address => address, --to DDR
282         byte_we => byte_we,
283         data_write => data_write,
284         data_read => data_read,
285         pause_in => eth_pause_in,
286
287         mem_address => cpu_address(31 downto 2), --from CPU
288         mem_byte_we => cpu_byte_we,
289         data_w => cpu_data_w,
290         pause_out => eth_pause,
291
292         E_RX_CLK => gpioA_in(20),
293         E_RX_DV => gpioA_in(19),
294         E_RXD => gpioA_in(18 downto 15),
295         E_TX_CLK => gpioA_in(14),
296         E_TX_EN => gpio0_out(28),
297         E_TXD => gpio0_out(27 downto 24));
298   end generate;
299242
300243end; --architecture logic
301244
plasma/logic/ram_image.vhd
4545INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
4646INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
4747INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
48INIT_04 => X"1c24001030008c24ac24ac9424003c00180003241c24a4248c0018ac2400003c",
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...... 
122122INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
123123INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
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146INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
147147INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
148148INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
149149INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
...... 
195195
196196   RAMB16_S9_inst2 : RAMB16_S9
197197   generic map (
198INIT_00 => X"00000000000000000000000000000000ff00000100ff18000e000f000c008c00",
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plasma/logic/simulation/output.txt
1
2Greetings from the bootloader Apr 21 2010 19:05:48:
3
4Waiting for binary image linked at 0x10000000
5Other Menu Options:
61. Memory read word
72. Memory write word
83. Memory read byte
94. Memory write byte
105. Jump to address
116. Raw memory read
127. Raw memory write
138. Checksum
149. Dump
15F. Copy 128KB from DDR to flash
16>
17Waiting for binary image linked at 0x10000000
18Other Menu Options:
191. Memory read word
202. Memory write word
213. Memory read byte
224. Memory write byte
235. Jump to address
246. Raw memory read
257. Raw memory write
268. Checksum
279. Dump
28F. Copy 128KB from DDR to flash
29> 4
plasma/logic/simulation/plasma_3e_TB.do
1vlib work
2vmap work
3vcom -93 -work work ../mlite_pack.vhd
4vcom -93 -work work ../plasma.vhd
5vcom -93 -work work ../alu.vhd
6vcom -93 -work work ../control.vhd
7vcom -93 -work work ../mem_ctrl.vhd
8vcom -93 -work work ../mult.vhd
9vcom -93 -work work ../shifter.vhd
10vcom -93 -work work ../bus_mux.vhd
11vcom -93 -work work ../ddr_ctrl.vhd
12vcom -93 -work work ../mlite_cpu.vhd
13vcom -93 -work work ../pc_next.vhd
14vcom -93 -work work ../cache.vhd
15vcom -93 -work work ../eth_dma.vhd
16vcom -93 -work work ../pipeline.vhd
17vcom -93 -work work ../reg_bank.vhd
18vcom -93 -work work ../uart.vhd
19vcom -93 -work work ../plasma_3e.vhd
20vcom -93 -work work ../ram_image.vhd
21vcom -93 -work work ../tbench.vhd
22
23vsim -t 1ps tbench
24view wave
25add wave *
26
27view structure
28view signals
29run 15ms
plasma/logic/simulation/transcript
1# // ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-21-generic
2# //
3# // Copyright Mentor Graphics Corporation 2005
4# // All Rights Reserved.
5# //
6# // THIS WORK CONTAINS TRADE SECRET AND
7# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
8# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
9# // AND IS SUBJECT TO LICENSE TERMS.
10# //
11# do plasma_3e_TB.do
12# Reading /home/opt/cad/modeltech/linux/../modelsim.ini
13# "work" maps to directory work. (Default mapping)
14# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
15# -- Loading package standard
16# -- Loading package std_logic_1164
17# -- Compiling package mlite_pack
18# -- Compiling package body mlite_pack
19# -- Loading package mlite_pack
20# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
21# -- Loading package standard
22# -- Loading package std_logic_1164
23# -- Loading package mlite_pack
24# -- Compiling entity plasma
25# -- Compiling architecture logic of plasma
26# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
27# -- Loading package standard
28# -- Loading package std_logic_1164
29# -- Loading package mlite_pack
30# -- Compiling entity alu
31# -- Compiling architecture logic of alu
32# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
33# -- Loading package standard
34# -- Loading package std_logic_1164
35# -- Loading package mlite_pack
36# -- Compiling entity control
37# -- Compiling architecture logic of control
38# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
39# -- Loading package standard
40# -- Loading package std_logic_1164
41# -- Loading package mlite_pack
42# -- Compiling entity mem_ctrl
43# -- Compiling architecture logic of mem_ctrl
44# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
45# -- Loading package standard
46# -- Loading package std_logic_1164
47# -- Loading package std_logic_arith
48# -- Loading package std_logic_unsigned
49# -- Loading package mlite_pack
50# -- Compiling entity mult
51# -- Compiling architecture logic of mult
52# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
53# -- Loading package standard
54# -- Loading package std_logic_1164
55# -- Loading package mlite_pack
56# -- Compiling entity shifter
57# -- Compiling architecture logic of shifter
58# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
59# -- Loading package standard
60# -- Loading package std_logic_1164
61# -- Loading package mlite_pack
62# -- Compiling entity bus_mux
63# -- Compiling architecture logic of bus_mux
64# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
65# -- Loading package standard
66# -- Loading package std_logic_1164
67# -- Loading package std_logic_arith
68# -- Loading package std_logic_unsigned
69# -- Loading package mlite_pack
70# -- Compiling entity ddr_ctrl
71# -- Compiling architecture logic of ddr_ctrl
72# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
73# -- Loading package standard
74# -- Loading package std_logic_1164
75# -- Loading package mlite_pack
76# -- Loading package std_logic_arith
77# -- Loading package std_logic_unsigned
78# -- Compiling entity mlite_cpu
79# -- Compiling architecture logic of mlite_cpu
80# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
81# -- Loading package standard
82# -- Loading package std_logic_1164
83# -- Loading package mlite_pack
84# -- Compiling entity pc_next
85# -- Compiling architecture logic of pc_next
86# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
87# -- Loading package standard
88# -- Loading package std_logic_1164
89# -- Loading package std_logic_arith
90# -- Loading package std_logic_unsigned
91# -- Loading package vcomponents
92# -- Loading package mlite_pack
93# -- Compiling entity cache
94# -- Compiling architecture logic of cache
95# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
96# -- Loading package standard
97# -- Loading package std_logic_1164
98# -- Loading package std_logic_arith
99# -- Loading package std_logic_unsigned
100# -- Loading package mlite_pack
101# -- Compiling entity eth_dma
102# -- Compiling architecture logic of eth_dma
103# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
104# -- Loading package standard
105# -- Loading package std_logic_1164
106# -- Loading package mlite_pack
107# -- Compiling entity pipeline
108# -- Compiling architecture logic of pipeline
109# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
110# -- Loading package standard
111# -- Loading package std_logic_1164
112# -- Loading package std_logic_arith
113# -- Loading package std_logic_unsigned
114# -- Loading package mlite_pack
115# -- Compiling entity reg_bank
116# -- Compiling architecture ram_block of reg_bank
117# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
118# -- Loading package standard
119# -- Loading package std_logic_1164
120# -- Loading package attributes
121# -- Loading package std_logic_misc
122# -- Loading package std_logic_arith
123# -- Loading package textio
124# -- Loading package std_logic_textio
125# -- Loading package std_logic_unsigned
126# -- Loading package mlite_pack
127# -- Compiling entity uart
128# -- Compiling architecture logic of uart
129# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
130# -- Loading package standard
131# -- Loading package std_logic_1164
132# -- Loading package std_logic_arith
133# -- Loading package std_logic_unsigned
134# -- Compiling entity plasma_3e
135# -- Compiling architecture logic of plasma_3e
136# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
137# -- Loading package standard
138# -- Loading package std_logic_1164
139# -- Loading package attributes
140# -- Loading package std_logic_misc
141# -- Loading package std_logic_arith
142# -- Loading package std_logic_unsigned
143# -- Loading package mlite_pack
144# -- Loading package vcomponents
145# -- Compiling entity ram
146# -- Compiling architecture logic of ram
147# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
148# -- Loading package standard
149# -- Loading package std_logic_1164
150# -- Loading package mlite_pack
151# -- Loading package std_logic_arith
152# -- Loading package std_logic_unsigned
153# -- Compiling entity tbench
154# -- Compiling architecture logic of tbench
155# vsim -t 1ps tbench
156# Loading /home/opt/cad/modeltech/linux/../std.standard
157# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_1164(body)
158# Loading work.mlite_pack(body)
159# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_arith(body)
160# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_unsigned(body)
161# Loading work.tbench(logic)
162# Loading work.plasma(logic)
163# Loading work.mlite_cpu(logic)
164# Loading work.pc_next(logic)
165# Loading work.mem_ctrl(logic)
166# Loading work.control(logic)
167# Loading work.reg_bank(ram_block)
168# Loading work.bus_mux(logic)
169# Loading work.alu(logic)
170# Loading work.shifter(logic)
171# Loading work.mult(logic)
172# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vcomponents
173# Loading work.cache(logic)
174# Loading /home/opt/cad/modeltech/linux/../synopsys.attributes
175# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_misc(body)
176# Loading work.ram(logic)
177# Loading /home/opt/cad/modeltech/linux/../std.textio(body)
178# Loading /home/opt/cad/modeltech/linux/../ieee.vital_timing(body)
179# Loading /home/opt/cad/modeltech/linux/../ieee.vital_primitives(body)
180# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vpkg(body)
181# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.ramb16_s9(ramb16_s9_v)
182# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_textio(body)
183# Loading work.uart(logic)
184# Loading work.eth_dma(logic)
185# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
186# .main_pane.workspace
187# .main_pane.signals.interior.cs
188# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
189# Time: 0 ps Iteration: 0 Instance: /tbench
190# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
191# Time: 0 ps Iteration: 0 Instance: /tbench
192# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
193# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/dma_gen2/u4_eth
194# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
195# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/dma_gen2/u4_eth
196# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
197# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u3_uart
198# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
199# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
200# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
201# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
202# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
203# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
204# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
205# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
206# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
207# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
208# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
209# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
210# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
211# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
212# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
213# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
214# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
215# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
216# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
217# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
218# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
219# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
220# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
221# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
222# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
223# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
224# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
225# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
226# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
227# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
228# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
229# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
230# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
231# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
232# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
233# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu
234# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
235# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
236# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
237# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
238# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
239# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
240# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
241# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
242# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
243# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/opt_cache2/u_cache
244# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
245# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
246# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
247# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
248# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
249# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
250# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
251# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
252# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
253# Time: 0 ps Iteration: 1 Instance: /tbench
254# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
255# Time: 0 ps Iteration: 1 Instance: /tbench
256# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
257# Time: 0 ps Iteration: 2 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
258# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
259# Time: 0 ps Iteration: 2 Instance: /tbench
260# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
261# Time: 0 ps Iteration: 2 Instance: /tbench
262# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
263# Time: 0 ps Iteration: 2 Instance: /tbench/u1_plasma/opt_cache2/u_cache
264# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
265# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
266# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
267# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
268# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
269# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
270# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
271# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
272# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
273# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/opt_cache2/u_cache
274# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
275# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
276# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
277# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
278# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
279# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
280# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
281# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
282# Break key hit
283# Simulation stop requested.
plasma/logic/tbench.vhd
1library ieee;
2use ieee.std_logic_1164.all;
3use work.mlite_pack.all;
4use ieee.std_logic_unsigned.all;
5
6entity tbench is
7end; --entity tbench
8
9architecture logic of tbench is
10   constant memory_type : string :=
11   "TRI_PORT_X";
12
13   constant log_file : string :=
14   "output.txt";
15
16   signal clk : std_logic := '1';
17   signal reset : std_logic := '1';
18   signal interrupt : std_logic := '0';
19   signal mem_write : std_logic;
20   signal address : std_logic_vector(31 downto 2);
21   signal data_write : std_logic_vector(31 downto 0);
22   signal data_read : std_logic_vector(31 downto 0);
23   signal pause1 : std_logic := '0';
24   signal pause2 : std_logic := '0';
25   signal pause : std_logic;
26   signal no_ddr_start: std_logic;
27   signal no_ddr_stop : std_logic;
28   signal byte_we : std_logic_vector(3 downto 0);
29   signal uart_write : std_logic;
30   signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
31begin --architecture
32   --Uncomment the line below to test interrupts
33   interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
34
35   clk <= not clk after 50 ns;
36   reset <= '0' after 500 ns;
37   pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
38   pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
39   pause <= pause1 or pause2;
40   gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
41   gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
42   gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
43   gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
44
45   u1_plasma: plasma
46      generic map (memory_type => memory_type,
47                   ethernet => '1',
48                   use_cache => '1',
49                   log_file => log_file)
50      PORT MAP (
51         clk => clk,
52         reset => reset,
53         uart_read => uart_write,
54         uart_write => uart_write,
55
56         address => address,
57         byte_we => byte_we,
58         data_write => data_write,
59         data_read => data_read,
60         mem_pause_in => pause,
61         no_ddr_start => no_ddr_start,
62         no_ddr_stop => no_ddr_stop,
63
64         gpio0_out => open,
65         gpioA_in => gpioA_in);
66
67   dram_proc: process(clk, address, byte_we, data_write, pause)
68      constant ADDRESS_WIDTH : natural := 16;
69      type storage_array is
70         array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
71         std_logic_vector(31 downto 0);
72      variable storage : storage_array;
73      variable data : std_logic_vector(31 downto 0);
74      variable index : natural := 0;
75   begin
76      index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
77      data := storage(index);
78
79      if byte_we(0) = '1' then
80         data(7 downto 0) := data_write(7 downto 0);
81      end if;
82      if byte_we(1) = '1' then
83         data(15 downto 8) := data_write(15 downto 8);
84      end if;
85      if byte_we(2) = '1' then
86         data(23 downto 16) := data_write(23 downto 16);
87      end if;
88      if byte_we(3) = '1' then
89         data(31 downto 24) := data_write(31 downto 24);
90      end if;
91
92      if rising_edge(clk) then
93         if address(30 downto 28) = "001" and byte_we /= "0000" then
94            storage(index) := data;
95         end if;
96      end if;
97
98      if pause = '0' then
99         data_read <= data;
100      end if;
101   end process;
102
103
104end; --architecture logic

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