Date:2010-05-10 21:56:51 (10 years 2 months ago)
Author:Carlos Camargo
Commit:717c35e2389243414c45cbefd3f3ed2162dda6cd
Message:Adding post route simulation to FPGA examples

Files: Examples/blink/logic/Makefile (2 diffs)
Examples/blink/logic/simulation/blink_TB.do (1 diff)
Examples/blink/logic/simulation/blink_TIMING_TB.do (1 diff)
Examples/sram/logic/Makefile (2 diffs)
Examples/sram/logic/simulation/glbl.v (1 diff)
Examples/sram/logic/simulation/sram_bus_TB.do (1 diff)
Examples/sram/logic/simulation/sram_bus_TIMING_TB.do (1 diff)
Examples/sram/logic/simulation/transcript (1 diff)
Examples/sram/logic/simulation/vsim.wlf (0 diffs)
Examples/sram/logic/simulation/wave.do (1 diff)
Examples/sram/logic/simulation/work/_info (1 diff)
Examples/sram/logic/simulation/work/glbl/_primary.dat (0 diffs)
Examples/sram/logic/simulation/work/glbl/_primary.vhd (1 diff)
Examples/sram/logic/simulation/work/glbl/verilog.asm (0 diffs)
Examples/sram/logic/simulation/work/sram_bus/_primary.dat (0 diffs)
Examples/sram/logic/simulation/work/sram_bus/_primary.vhd (1 diff)
Examples/sram/logic/simulation/work/sram_bus/verilog.asm (0 diffs)
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.dat (0 diffs)
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.vhd (1 diff)
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/verilog.asm (0 diffs)
Examples/sram/logic/sram_bus_TB.v (1 diff)
plasma/logic/Makefile (2 diffs)
plasma/logic/simulation/plasma_TIMING_TB.do (1 diff)

Change Details

Examples/blink/logic/Makefile
1616remake: clean-build all
1717
1818clean:
19    rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
19    rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
2020    rm -f *.bit
2121
2222cleanall: clean
...... 
6363$(DESIGN).bit: build/project_r.ncd build/project_r.twr
6464    cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
6565    @mv -f build/project_r.bit $@
66
67build/project_r.v: build/project_r.ncd
68    cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
69
6670sim:
67    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
71    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
72
73timesim: build/project_r.v
74    cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
6875
6976upload: $(DESIGN).bit
7077    scp $(DESIGN).bit root@$(SAKC_IP):
Examples/blink/logic/simulation/blink_TB.do
11vlib work
2vlog +acc "../blink.v"
3vlog +acc "../blink_TB.v"
4vlog +acc "glbl.v"
5vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver blink_TB_v glbl
2vlog -incr +libext+.v \
3            "../blink.v" \
4            "../blink_TB.v" \
5            "glbl.v"
6
7vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver blink_TB_v glbl
68view wave
7do wave.do
8#add wave *
9#do wave.do
10add wave *
911add wave /glbl/GSR
1012view structure
1113view signals
Examples/blink/logic/simulation/blink_TIMING_TB.do
1vlib work
2vlog -incr "../build/project.v" "../blink_TB.v" "glbl.v"
3vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver blink_TB_v glbl
4view wave
5#do wave.do
6add wave *
7add wave /glbl/GSR
8view structure
9view signals
10run 15ms
Examples/sram/logic/Makefile
66
77SIM_CMD = /opt/cad/modeltech/bin/vsim
88SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
9#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
109SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
1110SAKC_IP = 192.168.254.101
1211
...... 
6766$(DESIGN).bit: build/project_r.ncd build/project_r.twr
6867    cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
6968    @mv -f build/project_r.bit $@
69
70build/project_r.v: build/project_r.ncd
71    cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
72
7073sim:
71    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
74    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
75
76timesim: build/project_r.v
77    cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
7278
7379upload: $(DESIGN).bit
7480    scp $(DESIGN).bit root@$(SAKC_IP):
Examples/sram/logic/simulation/glbl.v
1// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.11.156.1 2007/03/09 18:12:55 patrickp Exp $
2
3`timescale 1 ps / 1 ps
4
5module glbl ();
6
7    parameter ROC_WIDTH = 100000;
8    parameter TOC_WIDTH = 0;
9
10    wire GSR;
11    wire GTS;
12    wire PRLD;
13
14    reg GSR_int;
15    reg GTS_int;
16    reg PRLD_int;
17
18//-------- JTAG Globals --------------
19    wire JTAG_TDO_GLBL;
20    wire JTAG_TCK_GLBL;
21    wire JTAG_TDI_GLBL;
22    wire JTAG_TMS_GLBL;
23    wire JTAG_TRST_GLBL;
24
25    reg JTAG_CAPTURE_GLBL;
26    reg JTAG_RESET_GLBL;
27    reg JTAG_SHIFT_GLBL;
28    reg JTAG_UPDATE_GLBL;
29
30    reg JTAG_SEL1_GLBL = 0;
31    reg JTAG_SEL2_GLBL = 0 ;
32    reg JTAG_SEL3_GLBL = 0;
33    reg JTAG_SEL4_GLBL = 0;
34
35    reg JTAG_USER_TDO1_GLBL = 1'bz;
36    reg JTAG_USER_TDO2_GLBL = 1'bz;
37    reg JTAG_USER_TDO3_GLBL = 1'bz;
38    reg JTAG_USER_TDO4_GLBL = 1'bz;
39
40    assign (weak1, weak0) GSR = GSR_int;
41    assign (weak1, weak0) GTS = GTS_int;
42    assign (weak1, weak0) PRLD = PRLD_int;
43
44    initial begin
45    GSR_int = 1'b1;
46    PRLD_int = 1'b1;
47    #(ROC_WIDTH)
48    GSR_int = 1'b0;
49    PRLD_int = 1'b0;
50    end
51
52    initial begin
53    GTS_int = 1'b1;
54    #(TOC_WIDTH)
55    GTS_int = 1'b0;
56    end
57
58endmodule
Examples/sram/logic/simulation/sram_bus_TB.do
1vlib work
2vlog -incr +libext+.v \
3            "../sram_bus.v" \
4            "../sram_bus_TB.v" \
5            "glbl.v"
6vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
7view wave
8#do wave.do
9add wave *
10view structure
11view signals
12run 5us
Examples/sram/logic/simulation/sram_bus_TIMING_TB.do
1vlib work
2vlog -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
3vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
4view wave
5#do wave.do
6add wave *
7view structure
8view signals
9run 5us
Examples/sram/logic/simulation/transcript
1# // ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-22-generic
2# //
3# // Copyright Mentor Graphics Corporation 2005
4# // All Rights Reserved.
5# //
6# // THIS WORK CONTAINS TRADE SECRET AND
7# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
8# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
9# // AND IS SUBJECT TO LICENSE TERMS.
10# //
11# do sram_bus_TIMING_TB.do
12# ** Warning: (vlib-34) Library already exists at "work".
13# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
14# -- Compiling module sram_bus
15# -- Compiling module glbl
16# -- Compiling module sram_bus_TB_v
17# ** Warning: glbl.v(5): 'glbl' already exists.
18# -- Compiling module glbl
19#
20# Top level modules:
21# glbl
22# sram_bus_TB_v
23# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl
24# Loading work.sram_bus_TB_v
25# Loading work.sram_bus
26# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
27# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
28# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF
29# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF
30# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2
31# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2
32# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2
33# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
34# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
35# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
36# Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
37# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
38# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
39# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
40# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD
41# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF
42# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT
43# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
44# Loading work.glbl
45# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
46# Region: /sram_bus_TB_v/uut
47# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
48# Region: /sram_bus_TB_v/uut
49# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
50# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
51# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
52# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux
53# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4
54# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4
55# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
56# .main_pane.workspace
57# .main_pane.signals.interior.cs
58
59
60
61
62
63exit
Examples/sram/logic/simulation/vsim.wlf
Examples/sram/logic/simulation/wave.do
1onerror {resume}
2quietly WaveActivateNextPane {} 0
3add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/clk
4add wave -noupdate -format Literal -radix hexadecimal /sram_bus_TB_v/addr
5add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/nwe
6add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/ncs
7add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/noe
8add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/reset
9add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/led
10add wave -noupdate -format Literal -radix hexadecimal {/sram_bus_TB_v/sram_data$inout$reg}
11add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/sram_data
12add wave -noupdate -format Literal -radix hexadecimal /sram_bus_TB_v/data_tx
13add wave -noupdate -format Logic -radix hexadecimal /glbl/GSR
14TreeUpdate [SetDefaultTree]
15WaveRestoreCursors {{Cursor 1} {154070 ps} 0}
16configure wave -namecolwidth 323
17configure wave -valuecolwidth 100
18configure wave -justifyvalue left
19configure wave -signalnamewidth 0
20configure wave -snapdistance 10
21configure wave -datasetprefix 0
22configure wave -rowmargin 4
23configure wave -childrowmargin 2
24configure wave -gridoffset 0
25configure wave -gridperiod 1
26configure wave -griddelta 40
27configure wave -timeline 0
28update
29WaveRestoreZoom {0 ps} {656250 ps}
Examples/sram/logic/simulation/work/_info
1m255
213
3cModel Technology
4d/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/Examples/sram/logic/simulation
5vglbl
6IT?5S;>bN`@zG_25]R_4A33
7VnN]4Gon>inod6>M^M2[SV1
8w1273510321
9Fglbl.v
10L0 5
11OE;L;6.0d;29
12r1
1331
14vsram_bus
15IYS7oKaz71LdIhQ>[[g2fo3
16V7bnNHP1kz?3UaZfjPj4WE1
17w1273511584
18F../build/project.v
19L0 37
20OE;L;6.0d;29
21r1
2231
23vsram_bus_TB_v
24IA=m;kT@<eh:`ekMlOPXX@0
25VQ[@Nfjd=de;Dc[[gj0bf41
26w1273511227
27F../sram_bus_TB.v
28L0 3
29OE;L;6.0d;29
30r1
3131
32nsram_bus_@t@b_v
Examples/sram/logic/simulation/work/glbl/_primary.dat
Examples/sram/logic/simulation/work/glbl/_primary.vhd
1library verilog;
2use verilog.vl_types.all;
3entity glbl is
4    generic(
5        ROC_WIDTH : integer := 100000;
6        TOC_WIDTH : integer := 0
7    );
8end glbl;
Examples/sram/logic/simulation/work/glbl/verilog.asm
Examples/sram/logic/simulation/work/sram_bus/_primary.dat
Examples/sram/logic/simulation/work/sram_bus/_primary.vhd
1library verilog;
2use verilog.vl_types.all;
3entity sram_bus is
4    port(
5        clk : in vl_logic;
6        reset : in vl_logic;
7        ncs : in vl_logic;
8        noe : in vl_logic;
9        nwe : in vl_logic;
10        led : out vl_logic;
11        sram_data : inout vl_logic_vector(7 downto 0);
12        addr : in vl_logic_vector(12 downto 0)
13    );
14end sram_bus;
Examples/sram/logic/simulation/work/sram_bus/verilog.asm
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.dat
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.vhd
1library verilog;
2use verilog.vl_types.all;
3entity sram_bus_TB_v is
4    generic(
5        PERIOD : integer := 20;
6        DUTY_CYCLE : real := 0.500000;
7        OFFSET : integer := 0;
8        TSET : integer := 3;
9        THLD : integer := 3;
10        NWS : integer := 3;
11        CAM_OFF : integer := 4000
12    );
13end sram_bus_TB_v;
Examples/sram/logic/simulation/work/sram_bus_@t@b_v/verilog.asm
Examples/sram/logic/sram_bus_TB.v
1`timescale 1ns / 1ps
2
3module sram_bus_TB_v;
4
5   // inputs
6   reg clk;
7   reg [12:0] addr;
8   reg nwe;
9   reg ncs;
10   reg noe;
11   reg reset;
12   // leds
13   reg led;
14   // Bidirs
15   reg [7:0] sram_data$inout$reg ;
16
17   // Instantiate the Unit Under Test (UUT)
18   sram_bus uut ( .clk(clk), .reset(reset),
19       .sram_data(sram_data), .addr(addr), .nwe(nwe),
20       .ncs(ncs), .noe(noe)
21   );
22   parameter PERIOD = 20;
23   parameter real DUTY_CYCLE = 0.5;
24   parameter OFFSET = 0;
25   parameter TSET = 3;
26   parameter THLD = 3;
27   parameter NWS = 3;
28   parameter CAM_OFF = 4000;
29
30     reg [15:0] i;
31     reg [15:0] j;
32     reg [15:0] k;
33     reg [15:0] data_tx;
34
35
36    event reset_trigger;
37    event reset_done_trigger;
38
39    initial begin // Reset the system, Start the image capture process
40      forever begin
41        @ (reset_trigger);
42        @ (negedge clk);
43        reset = 1;
44        @ (negedge clk);
45        reset = 0;
46        -> reset_done_trigger;
47      end
48    end
49
50    initial begin // Initialize Inputs
51      clk = 0; addr = 0; nwe = 1; ncs = 1; noe = 1;
52    end
53
54   initial begin // Process for clk
55     #OFFSET;
56     forever
57     begin
58       clk = 1'b0;
59       #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
60       #(PERIOD*DUTY_CYCLE);
61     end
62   end
63
64 initial begin: TEST_CASE
65     #10 -> reset_trigger;
66     @ (reset_done_trigger);
67     // Write data to SRAM
68   for(i=0; i<10; i=i+1) begin
69     @ (posedge clk);
70     ncs <= 0;
71     addr <= i[9:0];
72     repeat (TSET) begin
73       @ (posedge clk);
74     end
75     nwe <= 0;
76     sram_data$inout$reg <= i*2;
77     repeat (NWS) begin
78       @ (posedge clk);
79     end
80     nwe <= 1;
81     repeat (THLD) begin
82       @ (posedge clk);
83     end
84     ncs <= 1;
85     sram_data$inout$reg = {16{1'bz}};
86   end
87   nwe = 1;
88
89   //Read Data
90   for(i=0; i<10; i=i+1) begin
91     @ (posedge clk);
92     ncs <= 0;
93     addr <= i[9:0];
94     repeat (TSET) begin
95       @ (posedge clk);
96     end
97     noe <= 0;
98     sram_data$inout$reg <= i;
99     repeat (NWS) begin
100       @ (posedge clk);
101     end
102     noe <= 1;
103     repeat (THLD) begin
104      @ (posedge clk);
105     end
106     ncs <= 1;
107     sram_data$inout$reg = {16{1'bz}};
108   end
109 end
110
111
112endmodule
113
plasma/logic/Makefile
33DEVICE = xc3s500e-fg320-4
44BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
55                  -g CRC:enable -g StartUpClk:CCLK
6
7
86SIM_CMD = /opt/cad/modeltech/bin/vsim
97SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
10#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
118SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
129
1310SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd ram_image.vhd
...... 
6865$(DESIGN).bit: build/project_r.ncd build/project_r.twr
6966    cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
7067    @mv -f build/project_r.bit $@
71upload: $(DESIGN).bit
72    LD_PRELOAD=/usr/lib/libusb-driver.so impact -batch prog.cmd
68
69build/project_r.v: build/project_r.ncd
70    cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
71
72sim:
73    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
74
75timesim: build/project_r.v
76    cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
7377
7478sim:
7579    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
plasma/logic/simulation/plasma_TIMING_TB.do
1vlib work
2vlog -incr "../build/project.v" "../plasma_TB.v" "glbl.v"
3vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver plasma_TB_v glbl
4view wave
5do wave1.do
6#add wave *
7view structure
8view signals
9run 16us

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