Hardware Design: SIE
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Hardware Design: SIE Commit Details
Date: | 2010-08-09 15:10:02 (13 years 7 months ago) |
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Author: | Carlos Camargo |
Commit: | 933fa4c286cb988ca7a7c5b55502078996e92c1a |
Message: | Adding usbtool configuration file |
Files: |
binaries/usbboot_2gb_nand.cfg (1 diff) |
Change Details
binaries/usbboot_2gb_nand.cfg | ||
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1 | # | |
2 | # usbboot configuration file | |
3 | # | |
4 | # Utility to respond to the Ingenic XBurst USB boot protocol, provide | |
5 | # initial boot stages and ability to access NAND on device. | |
6 | # | |
7 | # Authors: Ingenic Semiconductor, Inc. | |
8 | # Xiangfu Liu <xiangfu@qi-hardware.com> | |
9 | # Marek Lindner <lindner_marek@yahoo.de> | |
10 | # Wolfgang Spraul <wolfgang@qi-hardware.com> | |
11 | # | |
12 | # This program is free software: you can redistribute it and/or modify | |
13 | # it under the terms of the GNU General Public License as published by | |
14 | # the Free Software Foundation, either version 3 of the License, or | |
15 | # (at your option) any later version. | |
16 | # | |
17 | # This program is distributed in the hope that it will be useful, | |
18 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | # GNU General Public License for more details. | |
21 | # | |
22 | # You should have received a copy of the GNU General Public License | |
23 | # along with this program. If not, see <http://www.gnu.org/licenses/>. | |
24 | ||
25 | # [PLL] | |
26 | EXTCLK = 12 #Define the external crystal in MHz | |
27 | CPUSPEED = 252 #Define the PLL output frequency | |
28 | PHMDIV = 3 #Define the frequency divider ratio of PLL=CCLK:PCLK=HCLK=MCLK | |
29 | BOUDRATE = 57600 #Define the uart boudrate | |
30 | USEUART = 0 #Use which uart, 0/1 for jz4740,0/1/2/3 for jz4750 | |
31 | ||
32 | # [SDRAM] | |
33 | BUSWIDTH = 16 #The bus width of the SDRAM in bits (16|32) | |
34 | BANKS = 4 #The bank number (2|4) | |
35 | ROWADDR = 13 #Row address width in bits (11-13) | |
36 | COLADDR = 9 #Column address width in bits (8-12) | |
37 | ISMOBILE = 0 #Define whether SDRAM is mobile SDRAM, this only valid for Jz4750 ,1:yes 0:no | |
38 | ISBUSSHARE = 1 #Define whether SDRAM bus share with NAND 1:shared 0:unshared | |
39 | DEBUGOPS = 0 | |
40 | ||
41 | # [NAND] | |
42 | NAND_BUSWIDTH = 8 #The width of the NAND flash chip in bits (8|16|32) | |
43 | NAND_ROWCYCLES = 3 #The row address cycles (2|3) | |
44 | NAND_PAGESIZE = 4096 #The page size of the NAND chip in bytes(512|2048|4096) | |
45 | NAND_PAGEPERBLOCK = 128 #The page number per block | |
46 | NAND_FORCEERASE = 1 #The force to erase flag (0|1) | |
47 | NAND_OOBSIZE = 128 #oob size in byte | |
48 | NAND_ECCPOS = 12 #Specify the ECC offset inside the oob data (0-[oobsize-1]) | |
49 | NAND_BADBLOCKPOS = 0 #Specify the badblock flag offset inside the oob (0-[oobsize-1]) | |
50 | NAND_BADBLOCKPAGE = 127 #Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1]) | |
51 | NAND_PLANENUM = 1 #The planes number of target nand flash | |
52 | NAND_BCHBIT = 4 #Specify the hardware BCH algorithm for 4750 (4|8) | |
53 | NAND_WPPIN = 0 #Specify the write protect pin number | |
54 | NAND_BLOCKPERCHIP = 0 #Specify the block number per chip,0 means ignore | |
55 | ||
56 | #The program will calculate the total SDRAM size by : size = 2^(ROWADDR + COLADDR) * BANKNUM * (SDRAMWIDTH / 4) | |
57 | #The CPUSPEED has restriction as: ( CPUSPEED % EXTCLK == 0 ) && ( CPUSPEED % 12 == 0 ) | |
58 | #For jz4750, the program just init BANK0(DSC0). | |
59 | #Beware all variables must be set correct! |
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