Date:2010-10-12 16:05:52 (12 years 11 months ago)
Author:Carlos Camargo
Commit:9b75552c8365d3aab7c0eb280d554a2cec9fab34
Message:Adding bootloader for lm32
Files: KICAD_design_files/SAKC_PCB_v2/SAKC.pro (4 diffs)
lm32/logic/sakc/firmware/boot0-serial/crt0ram.d (1 diff)
lm32/logic/sakc/firmware/boot0-serial/crt0ram.o (0 diffs)
lm32/logic/sakc/firmware/boot0-serial/image (0 diffs)
lm32/logic/sakc/firmware/boot0-serial/image.map (1 diff)
lm32/logic/sakc/firmware/boot0-serial/main.d (1 diff)
lm32/logic/sakc/firmware/boot0-serial/main.o (0 diffs)
lm32/logic/sakc/firmware/boot0-serial/soc-hw.d (1 diff)
lm32/logic/sakc/firmware/boot0-serial/soc-hw.o (0 diffs)
lm32/logic/sakc/firmware/loader_cain/Makefile (1 diff)
lm32/logic/sakc/firmware/loader_cain/crt0ram.S (1 diff)
lm32/logic/sakc/firmware/loader_cain/linker.ld (1 diff)
lm32/logic/sakc/firmware/loader_cain/main.c (1 diff)
lm32/logic/sakc/firmware/loader_cain/soc-hw.c (1 diff)
lm32/logic/sakc/firmware/loader_cain/soc-hw.h (1 diff)
lm32/logic/sakc/firmware/loader_cain/xmodem.c (1 diff)
lm32/logic/sakc/system.v (1 diff)

Change Details

KICAD_design_files/SAKC_PCB_v2/SAKC.pro
1update=Sat 09 Oct 2010 05:15:55 PM COT
2last_client=cvpcb
1update=Mon 11 Oct 2010 12:34:05 PM COT
2last_client=pcbnew
33[general]
44version=1
55RootSch=SAKC.sch
...... 
7373LibName31=Design files/o_analog
7474LibName32=Design files/tm2301n
7575LibName33=Design files/tl780-05ckttr
76[cvpcb]
77version=1
78NetIExt=net
79[cvpcb/libraries]
80EquName1=devcms
7681[pcbnew]
7782version=1
7883PadDrlX=0
...... 
9297MSegLar=79
9398LastNetListRead=
9499[pcbnew/libraries]
100LibDir=./N_MODELS/
95101LibName1=./N_MODELS/D8
96102LibName2=./N_MODELS/R36
97103LibName3=./N_MODELS/R35
...... 
268274LibName174=./N_MODELS/Y3
269275LibName175=v-reg-2
270276LibName176=ref-packages
271LibDir=./N_MODELS/
272[cvpcb]
273version=1
274NetIExt=net
275[cvpcb/libraries]
276EquName1=devcms
277277
lm32/logic/sakc/firmware/boot0-serial/crt0ram.d
1crt0ram.o: crt0ram.S
lm32/logic/sakc/firmware/boot0-serial/crt0ram.o
lm32/logic/sakc/firmware/boot0-serial/image
lm32/logic/sakc/firmware/boot0-serial/image.map
1
2Memory Configuration
3
4Name Origin Length Attributes
5bram 0x00000000 0x00001000
6*default* 0x00000000 0xffffffff
7
8Linker script and memory map
9
10                0x00000000 __DYNAMIC = 0x0
11                0x00000000 _BRAM_START = 0x0
12                0x00001000 _BRAM_SIZE = 0x1000
13                0x00001000 _BRAM_END = (_BRAM_START + _BRAM_SIZE)
14
15.text 0x00000000 0x270
16                0x00000000 _ftext = .
17 *(.text .stub .text.* .gnu.linkonce.t.*)
18 .text 0x00000000 0x8c crt0ram.o
19                0x00000000 _start
20                0x00000060 irq_enable
21                0x0000006c irq_mask
22                0x00000078 irq_disable
23                0x00000084 jump
24                0x00000088 halt
25 .text 0x0000008c 0x104 main.o
26                0x0000008c read_uint32
27                0x000000d0 main
28 .text 0x00000190 0xe0 soc-hw.o
29                0x00000190 sleep
30                0x000001c8 tic_init
31                0x000001f0 uart_init
32                0x000001f4 uart_getchar
33                0x00000218 uart_putchar
34                0x0000023c uart_putstr
35                0x00000270 _etext = .
36
37.rodata 0x00000270 0x1c
38                0x00000270 . = ALIGN (0x4)
39                0x00000270 _frodata = .
40 *(.rodata .rodata.* .gnu.linkonce.r.*)
41 .rodata.str1.4
42                0x00000270 0x1c main.o
43 *(.rodata1)
44                0x0000028c _erodata = .
45
46.data 0x0000028c 0xc
47                0x0000028c . = ALIGN (0x4)
48                0x0000028c _fdata = .
49 *(.data .data.* .gnu.linkonce.d.*)
50 .data 0x0000028c 0x0 crt0ram.o
51 .data 0x0000028c 0x0 main.o
52 .data 0x0000028c 0xc soc-hw.o
53                0x0000028c uart0
54                0x00000290 timer0
55                0x00000294 gpio0
56 *(.data1)
57                0x000002a0 _gp = ALIGN (0x10)
58 *(.sdata .sdata.* .gnu.linkonce.s.*)
59                0x00000298 _edata = .
60
61.bss 0x00000298 0x4
62                0x00000298 . = ALIGN (0x4)
63                0x00000298 _fbss = .
64 *(.dynsbss)
65 *(.sbss .sbss.* .gnu.linkonce.sb.*)
66 *(.scommon)
67 *(.dynbss)
68 *(.bss .bss.* .gnu.linkonce.b.*)
69 .bss 0x00000298 0x0 crt0ram.o
70 .bss 0x00000298 0x0 main.o
71 .bss 0x00000298 0x4 soc-hw.o
72                0x00000298 msec
73 *(COMMON)
74                0x0000029c _ebss = .
75                0x0000029c _end = .
76                0x00000ffc PROVIDE (_fstack, 0xffc)
77LOAD crt0ram.o
78LOAD main.o
79LOAD soc-hw.o
80OUTPUT(image elf32-lm32)
81
82.debug_abbrev 0x00000000 0x219
83 .debug_abbrev 0x00000000 0xcd main.o
84 .debug_abbrev 0x000000cd 0x14c soc-hw.o
85
86.debug_info 0x00000000 0x3d0
87 .debug_info 0x00000000 0x121 main.o
88 .debug_info 0x00000121 0x2af soc-hw.o
89
90.debug_line 0x00000000 0x2d8
91 .debug_line 0x00000000 0x18f main.o
92 .debug_line 0x0000018f 0x149 soc-hw.o
93
94.debug_frame 0x00000000 0xa0
95 .debug_frame 0x00000000 0x30 main.o
96 .debug_frame 0x00000030 0x70 soc-hw.o
97
98.debug_loc 0x00000000 0xfb
99 .debug_loc 0x00000000 0xb7 main.o
100 .debug_loc 0x000000b7 0x44 soc-hw.o
101
102.debug_pubnames
103                0x00000000 0xbc
104 .debug_pubnames
105                0x00000000 0x2b main.o
106 .debug_pubnames
107                0x0000002b 0x91 soc-hw.o
108
109.debug_aranges 0x00000000 0x40
110 .debug_aranges
111                0x00000000 0x20 main.o
112 .debug_aranges
113                0x00000020 0x20 soc-hw.o
114
115.debug_ranges 0x00000000 0x18
116 .debug_ranges 0x00000000 0x18 main.o
117
118.debug_str 0x00000000 0x17b
119 .debug_str 0x00000000 0xb8 main.o
120                                 0xd0 (size before relaxing)
121 .debug_str 0x000000b8 0xc3 soc-hw.o
122                                0x157 (size before relaxing)
123
124.comment 0x00000000 0x11
125 .comment 0x00000000 0x11 main.o
126                                 0x12 (size before relaxing)
127 .comment 0x00000000 0x12 soc-hw.o
lm32/logic/sakc/firmware/boot0-serial/main.d
1main.o: main.c soc-hw.h
lm32/logic/sakc/firmware/boot0-serial/main.o
lm32/logic/sakc/firmware/boot0-serial/soc-hw.d
1soc-hw.o: soc-hw.c soc-hw.h
lm32/logic/sakc/firmware/boot0-serial/soc-hw.o
lm32/logic/sakc/firmware/loader_cain/Makefile
1LM32_CC=lm32-elf-gcc
2LM32_LD=lm32-elf-ld
3LM32_OBJCOPY=lm32-elf-objcopy
4LM32_OBJDUMP=lm32-elf-objdump
5
6SREC2VRAM ?= ../../tools/srec2vram/srec2vram
7VRAMFILE=image.ram
8
9CFLAGS=-MMD -O2 -Wall -g -s -fomit-frame-pointer -mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled
10LDFLAGS=-nostdlib -nodefaultlibs -Tlinker.ld
11SEGMENTS = -j .text -j .rodata -j .data
12
13all: image.srec $(VRAMFILE)
14
15crt0ram.o: crt0ram.S
16    $(LM32_CC) $(CFLAGS) -c crt0ram.S
17
18main.o: main.c
19    $(LM32_CC) $(CFLAGS) -c main.c
20
21soc-hw.o: soc-hw.c
22    $(LM32_CC) $(CFLAGS) -c soc-hw.c
23
24
25xmodem.o: xmodem.c
26    $(LM32_CC) $(CFLAGS) -c xmodem.c
27
28
29image: crt0ram.o main.o soc-hw.o xmodem.o linker.ld Makefile
30    $(LM32_LD) $(LDFLAGS) -Map image.map -N -o image crt0ram.o main.o soc-hw.o xmodem.o
31
32image.lst: image
33    $(LM32_OBJDUMP) -h -S $< > $@
34
35image.bin: image
36    $(LM32_OBJCOPY) $(SEGMENTS) -O binary image image.bin
37
38image.srec: image image.lst
39    $(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.srec
40
41$(VRAMFILE): image.srec
42    $(SREC2VRAM) image.srec 0x0000000 0x1000 > $(VRAMFILE)
43
44clean:
45    rm -f image image.lst image.bin image.srec image.map image.ram *.o *.d
46
47DEPS := $(wildcard *.d)
48ifneq ($(DEPS),)
49include $(DEPS)
50endif
51
lm32/logic/sakc/firmware/loader_cain/crt0ram.S
1/*
2 * LatticeMico32 C startup code.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26/* Exception handlers - Must be 32 bytes long. */
27    .section .text, "ax", @progbits
28    .global _start
29    .global irq_enable, irq_disable, irq_set_mask, irq_get_mask
30    .global jump, halt
31    .global get_sp, get_gp
32
33_start:
34_reset_handler:
35    xor r0, r0, r0
36    wcsr IE, r0
37    mvhi r1, hi(_reset_handler)
38    ori r1, r1, lo(_reset_handler)
39    wcsr EBA, r1
40    calli _crt0
41    nop
42    nop
43
44_breakpoint_handler:
45    nop
46    nop
47    nop
48    nop
49    nop
50    nop
51    nop
52    nop
53
54_ibuserror_handler:
55    nop
56    nop
57    nop
58    nop
59    nop
60    nop
61    nop
62    nop
63
64_watchpoint_handler:
65    nop
66    nop
67    nop
68    nop
69    nop
70    nop
71    nop
72    nop
73
74_dbuserror_handler:
75    nop
76    nop
77    nop
78    nop
79    nop
80    nop
81    nop
82    nop
83
84_divzero_handler:
85    nop
86    nop
87    nop
88    nop
89    nop
90    nop
91    nop
92    nop
93
94_interrupt_handler:
95    sw (sp+0), ra
96    calli _save_all
97    rcsr r1, IP
98    calli irq_handler
99    mvhi r1, 0xffff
100    ori r1, r1, 0xffff
101    wcsr IP, r1
102    bi _restore_all_and_eret
103
104_scall_handler:
105    nop
106    nop
107    nop
108    nop
109    nop
110    nop
111    nop
112    nop
113
114_crt0:
115    /* Setup stack and global pointer */
116    mvhi sp, hi(_fstack)
117    ori sp, sp, lo(_fstack)
118    mvhi gp, hi(_gp)
119    ori gp, gp, lo(_gp)
120
121    /* Clear BSS */
122    mvhi r1, hi(_fbss)
123    ori r1, r1, lo(_fbss)
124    mvhi r3, hi(_ebss)
125    ori r3, r3, lo(_ebss)
126.clearBSS:
127    be r1, r3, .callMain
128    sw (r1+0), r0
129    addi r1, r1, 4
130    bi .clearBSS
131
132.callMain:
133    mvi r1, 0
134    mvi r2, 0
135    mvi r3, 0
136    calli main
137
138irq_enable:
139    mvi r1, 1
140    wcsr IE, r1
141    ret
142
143irq_disable:
144    mvi r1, 0
145    wcsr IE, r1
146    ret
147
148irq_set_mask:
149    wcsr IM, r1
150    ret
151
152irq_get_mask:
153    rcsr r1, IM
154    ret
155
156jump:
157    b r1
158
159halt:
160    bi halt
161
162    /* Save all registers onto the stack */
163_save_all:
164    addi sp, sp, -128
165    sw (sp+4), r1
166    sw (sp+8), r2
167    sw (sp+12), r3
168    sw (sp+16), r4
169    sw (sp+20), r5
170    sw (sp+24), r6
171    sw (sp+28), r7
172    sw (sp+32), r8
173    sw (sp+36), r9
174    sw (sp+40), r10
175#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
176    sw (sp+44), r11
177    sw (sp+48), r12
178    sw (sp+52), r13
179    sw (sp+56), r14
180    sw (sp+60), r15
181    sw (sp+64), r16
182    sw (sp+68), r17
183    sw (sp+72), r18
184    sw (sp+76), r19
185    sw (sp+80), r20
186    sw (sp+84), r21
187    sw (sp+88), r22
188    sw (sp+92), r23
189    sw (sp+96), r24
190    sw (sp+100), r25
191    sw (sp+104), r26
192    sw (sp+108), r27
193#endif
194    sw (sp+120), ea
195    sw (sp+124), ba
196    /* ra and sp need special handling, as they have been modified */
197    lw r1, (sp+128)
198    sw (sp+116), r1
199    mv r1, sp
200    addi r1, r1, 128
201    sw (sp+112), r1
202    ret
203
204        /* Restore all registers and return from exception */
205_restore_all_and_eret:
206        lw r1, (sp+4)
207        lw r2, (sp+8)
208        lw r3, (sp+12)
209        lw r4, (sp+16)
210        lw r5, (sp+20)
211        lw r6, (sp+24)
212        lw r7, (sp+28)
213        lw r8, (sp+32)
214        lw r9, (sp+36)
215        lw r10, (sp+40)
216#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
217        lw r11, (sp+44)
218        lw r12, (sp+48)
219        lw r13, (sp+52)
220        lw r14, (sp+56)
221        lw r15, (sp+60)
222        lw r16, (sp+64)
223        lw r17, (sp+68)
224        lw r18, (sp+72)
225        lw r19, (sp+76)
226        lw r20, (sp+80)
227        lw r21, (sp+84)
228        lw r22, (sp+88)
229        lw r23, (sp+92)
230        lw r24, (sp+96)
231        lw r25, (sp+100)
232        lw r26, (sp+104)
233        lw r27, (sp+108)
234#endif
235        lw ra, (sp+116)
236        lw ea, (sp+120)
237        lw ba, (sp+124)
238        /* Stack pointer must be restored last, in case it has been updated */
239        lw sp, (sp+112)
240        eret
241
242get_sp:
243    mv r1, sp
244    ret
245
246get_gp:
247    mv r1, gp
248    ret
249
lm32/logic/sakc/firmware/loader_cain/linker.ld
1OUTPUT_FORMAT("elf32-lm32")
2ENTRY(_start)
3
4__DYNAMIC = 0;
5
6
7_RAM_START = 0x0000000;
8_RAM_SIZE = 0x1000;
9_RAM_END = _RAM_START + _RAM_SIZE;
10
11MEMORY {
12  ram : ORIGIN = 0x0000000, LENGTH = 0x1000 /* 4k */
13}
14
15SECTIONS
16{
17  .text :
18  {
19    _ftext = .;
20    *(.text .stub .text.* .gnu.linkonce.t.*)
21    _etext = .;
22  } > ram
23
24  .rodata :
25  {
26    . = ALIGN(4);
27    _frodata = .;
28    *(.rodata .rodata.* .gnu.linkonce.r.*)
29    *(.rodata1)
30    _erodata = .;
31  } > ram
32
33  .data :
34  {
35    . = ALIGN(4);
36    _fdata = .;
37    *(.data .data.* .gnu.linkonce.d.*)
38    *(.data1)
39    _gp = ALIGN(16);
40    *(.sdata .sdata.* .gnu.linkonce.s.*)
41    _edata = .;
42  } > ram
43
44  .bss :
45  {
46    . = ALIGN(4);
47    _fbss = .;
48    *(.dynsbss)
49    *(.sbss .sbss.* .gnu.linkonce.sb.*)
50    *(.scommon)
51    *(.dynbss)
52    *(.bss .bss.* .gnu.linkonce.b.*)
53    *(COMMON)
54    _ebss = .;
55    _end = .;
56  } > ram
57}
58
59PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);
lm32/logic/sakc/firmware/loader_cain/main.c
1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2
3 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
4
5
6#include "soc-hw.h"
7#define RAM_BASE 0x1000
8
9unsigned int i, j,k; // Loop counter.
10
11
12int main() {
13    int key, len, autoboot = 1, dispmenu = 1;
14
15   uart_init();
16   uart_putstr("Cain's bootloader!!! \n");
17
18  while(1){ /* loop forever until u-boot gets booted or the board is reset */
19    if(dispmenu){
20     uart_putstr("\n1: Upload program to RAM\n");
21// uart_putstr("2: Upload u-boot to Dataflash\n");
22// uart_putstr("3: Upload Kernel to Dataflash\n");
23// uart_putstr("4: Start u-boot\n");
24// uart_putstr("5: Upload Filesystem image\n");
25// uart_putstr("6: Memory test\n");
26      dispmenu = 0;
27    }
28      key = uart_getchar();
29      autoboot = 0;
30
31    if(key == '1'){
32      len = rxmodem((char *)0x1000);
33      uart_putstr("Received ");
34      hexprint(len);
35      uart_putstr(" bytes\n");
36      jump(RAM_BASE);
37// dispmenu = 1;
38    }
39    else if(key == '2'){
40      dispmenu = 1;
41    }
42    else{
43      uart_putstr("Invalid input\n");
44      dispmenu = 1;
45    }
46  }
47
48
49    while(1){ asm("nop;"); }
50
51
52   return (0);
53
54
55}
lm32/logic/sakc/firmware/loader_cain/soc-hw.c
1#include "soc-hw.h"
2
3uart_t *uart0 = (uart_t *) 0xf0000000;
4timer_t *timer0 = (timer_t *) 0xf0010000;
5gpio_t *gpio0 = (gpio_t *) 0xF0020000;
6
7isr_ptr_t isr_table[32];
8
9
10void tic_isr();
11/***************************************************************************
12 * IRQ handling
13 */
14void isr_null()
15{
16}
17
18void irq_handler(uint32_t pending)
19{
20    int i;
21
22    for(i=0; i<32; i++) {
23        if (pending & 0x01) (*isr_table[i])();
24        pending >>= 1;
25    }
26}
27
28void isr_init()
29{
30    int i;
31    for(i=0; i<32; i++)
32        isr_table[i] = &isr_null;
33}
34
35void isr_register(int irq, isr_ptr_t isr)
36{
37    isr_table[irq] = isr;
38}
39
40void isr_unregister(int irq)
41{
42    isr_table[irq] = &isr_null;
43}
44
45/***************************************************************************
46 * TIMER Functions
47 */
48void msleep(uint32_t msec)
49{
50    uint32_t tcr;
51
52    // Use timer0.1
53    timer0->compare1 = (FCPU/1000)*msec;
54    timer0->counter1 = 0;
55    timer0->tcr1 = TIMER_EN;
56
57    do {
58        //halt();
59         tcr = timer0->tcr1;
60     } while ( ! (tcr & TIMER_TRIG) );
61}
62
63void nsleep(uint32_t nsec)
64{
65    uint32_t tcr;
66
67    // Use timer0.1
68    timer0->compare1 = (FCPU/1000000)*nsec;
69    timer0->counter1 = 0;
70    timer0->tcr1 = TIMER_EN;
71
72    do {
73        //halt();
74         tcr = timer0->tcr1;
75     } while ( ! (tcr & TIMER_TRIG) );
76}
77
78
79uint32_t tic_msec;
80
81void tic_isr()
82{
83    tic_msec++;
84    timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
85}
86
87void tic_init()
88{
89    tic_msec = 0;
90
91    // Setup timer0.0
92    timer0->compare0 = (FCPU/10000);
93    timer0->counter0 = 0;
94    timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
95
96    isr_register(1, &tic_isr);
97}
98
99
100/***************************************************************************
101 * UART Functions
102 */
103void uart_init()
104{
105    //uart0->ier = 0x00; // Interrupt Enable Register
106    //uart0->lcr = 0x03; // Line Control Register: 8N1
107    //uart0->mcr = 0x00; // Modem Control Register
108
109    // Setup Divisor register (Fclk / Baud)
110    //uart0->div = (FCPU/(57600*16));
111}
112
113char uart_getchar()
114{
115    while (! (uart0->ucr & UART_DR)) ;
116    return uart0->rxtx;
117}
118
119void uart_putchar(char c)
120{
121    while (uart0->ucr & UART_BUSY) ;
122    uart0->rxtx = c;
123}
124
125void uart_putstr(char *str)
126{
127    char *c = str;
128    while(*c) {
129        uart_putchar(*c);
130        c++;
131    }
132}
133
134void hexprint(unsigned int hexval)
135{
136  int digit[8], pos;
137  uart_putstr("0x");
138  for(pos = 0; pos < 8; pos++)
139    {
140      digit[pos] = (hexval & 0xF); /* last hexit */
141      hexval = hexval >> 4;
142    }
143  for(pos = 7; pos > -1; pos--)
144    {
145      if(digit[pos] < 0xA)
146        uart_putstr(digit[pos] + '0');
147      else
148        uart_putstr(digit[pos] + 'A' - 10);
149    }
150  uart_putchar(' ');
151}
152
153
lm32/logic/sakc/firmware/loader_cain/soc-hw.h
1#ifndef SPIKEHW_H
2#define SPIKEHW_H
3
4#define PROMSTART 0x00000000
5#define RAMSTART 0x00000800
6#define RAMSIZE 0x400
7#define RAMEND (RAMSTART + RAMSIZE)
8
9#define RAM_START 0x40000000
10#define RAM_SIZE 0x04000000
11
12#define FCPU 50000000
13
14#define UART_RXBUFSIZE 32
15
16/****************************************************************************
17 * Types
18 */
19typedef unsigned int uint32_t; // 32 Bit
20typedef signed int int32_t; // 32 Bit
21
22typedef unsigned char uint8_t; // 8 Bit
23typedef signed char int8_t; // 8 Bit
24
25/****************************************************************************
26 * Interrupt handling
27 */
28typedef void(*isr_ptr_t)(void);
29
30void irq_enable();
31void irq_disable();
32void irq_set_mask(uint32_t mask);
33uint32_t irq_get_mak();
34
35void isr_init();
36void isr_register(int irq, isr_ptr_t isr);
37void isr_unregister(int irq);
38
39/****************************************************************************
40 * General Stuff
41 */
42void halt();
43void jump(uint32_t addr);
44
45
46/****************************************************************************
47 * Timer
48 */
49#define TIMER_EN 0x08 // Enable Timer
50#define TIMER_AR 0x04 // Auto-Reload
51#define TIMER_IRQEN 0x02 // IRQ Enable
52#define TIMER_TRIG 0x01 // Triggered (reset when writing to TCR)
53
54typedef struct {
55    volatile uint32_t tcr0;
56    volatile uint32_t compare0;
57    volatile uint32_t counter0;
58    volatile uint32_t tcr1;
59    volatile uint32_t compare1;
60    volatile uint32_t counter1;
61} timer_t;
62
63void msleep(uint32_t msec);
64void nsleep(uint32_t nsec);
65
66void tic_init();
67
68
69/***************************************************************************
70 * GPIO0
71 */
72typedef struct {
73    volatile uint32_t ctrl;
74    volatile uint32_t dummy1;
75    volatile uint32_t dummy2;
76    volatile uint32_t dummy3;
77    volatile uint32_t in;
78    volatile uint32_t out;
79    volatile uint32_t oe;
80} gpio_t;
81
82/***************************************************************************
83 * UART0
84 */
85#define UART_DR 0x01 // RX Data Ready
86#define UART_ERR 0x02 // RX Error
87#define UART_BUSY 0x10 // TX Busy
88
89typedef struct {
90   volatile uint32_t ucr;
91   volatile uint32_t rxtx;
92} uart_t;
93
94void uart_init();
95void uart_putchar(char c);
96void uart_putstr(char *str);
97char uart_getchar();
98void hexprint(unsigned int hexval);
99
100
101/***************************************************************************
102 * Pointer to actual components
103 */
104extern timer_t *timer0;
105extern uart_t *uart0;
106extern gpio_t *gpio0;
107extern uint32_t *sram0;
108
109
110int rxmodem(unsigned char *dest);
111
112#endif // SPIKEHW_H
lm32/logic/sakc/firmware/loader_cain/xmodem.c
1/*
2    Copyright 2001, 2002 Georges Menie (www.menie.org)
3    Copyright 2004 Darrell Harmon modified to work in a bootloader
4
5    This program is free software; you can redistribute it and/or modify
6    it under the terms of the GNU Lesser General Public License as published by
7    the Free Software Foundation; either version 2 of the License, or
8    (at your option) any later version.
9
10    This program is distributed in the hope that it will be useful,
11    but WITHOUT ANY WARRANTY; without even the implied warranty of
12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13    GNU Lesser General Public License for more details.
14
15    You should have received a copy of the GNU Lesser General Public License
16    along with this program; if not, write to the Free Software
17    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18*/
19
20#include "soc-hw.h"
21#define SOH 0x01
22#define EOT 0x04
23#define ACK 0x06
24#define NAK 0x15
25
26
27/* CRC16 implementation acording to CCITT standards */
28
29static const unsigned short crc16tab[256]= {
30    0x0000,0x1021,0x2042,0x3063,0x4084,0x50a5,0x60c6,0x70e7,
31    0x8108,0x9129,0xa14a,0xb16b,0xc18c,0xd1ad,0xe1ce,0xf1ef,
32    0x1231,0x0210,0x3273,0x2252,0x52b5,0x4294,0x72f7,0x62d6,
33    0x9339,0x8318,0xb37b,0xa35a,0xd3bd,0xc39c,0xf3ff,0xe3de,
34    0x2462,0x3443,0x0420,0x1401,0x64e6,0x74c7,0x44a4,0x5485,
35    0xa56a,0xb54b,0x8528,0x9509,0xe5ee,0xf5cf,0xc5ac,0xd58d,
36    0x3653,0x2672,0x1611,0x0630,0x76d7,0x66f6,0x5695,0x46b4,
37    0xb75b,0xa77a,0x9719,0x8738,0xf7df,0xe7fe,0xd79d,0xc7bc,
38    0x48c4,0x58e5,0x6886,0x78a7,0x0840,0x1861,0x2802,0x3823,
39    0xc9cc,0xd9ed,0xe98e,0xf9af,0x8948,0x9969,0xa90a,0xb92b,
40    0x5af5,0x4ad4,0x7ab7,0x6a96,0x1a71,0x0a50,0x3a33,0x2a12,
41    0xdbfd,0xcbdc,0xfbbf,0xeb9e,0x9b79,0x8b58,0xbb3b,0xab1a,
42    0x6ca6,0x7c87,0x4ce4,0x5cc5,0x2c22,0x3c03,0x0c60,0x1c41,
43    0xedae,0xfd8f,0xcdec,0xddcd,0xad2a,0xbd0b,0x8d68,0x9d49,
44    0x7e97,0x6eb6,0x5ed5,0x4ef4,0x3e13,0x2e32,0x1e51,0x0e70,
45    0xff9f,0xefbe,0xdfdd,0xcffc,0xbf1b,0xaf3a,0x9f59,0x8f78,
46    0x9188,0x81a9,0xb1ca,0xa1eb,0xd10c,0xc12d,0xf14e,0xe16f,
47    0x1080,0x00a1,0x30c2,0x20e3,0x5004,0x4025,0x7046,0x6067,
48    0x83b9,0x9398,0xa3fb,0xb3da,0xc33d,0xd31c,0xe37f,0xf35e,
49    0x02b1,0x1290,0x22f3,0x32d2,0x4235,0x5214,0x6277,0x7256,
50    0xb5ea,0xa5cb,0x95a8,0x8589,0xf56e,0xe54f,0xd52c,0xc50d,
51    0x34e2,0x24c3,0x14a0,0x0481,0x7466,0x6447,0x5424,0x4405,
52    0xa7db,0xb7fa,0x8799,0x97b8,0xe75f,0xf77e,0xc71d,0xd73c,
53    0x26d3,0x36f2,0x0691,0x16b0,0x6657,0x7676,0x4615,0x5634,
54    0xd94c,0xc96d,0xf90e,0xe92f,0x99c8,0x89e9,0xb98a,0xa9ab,
55    0x5844,0x4865,0x7806,0x6827,0x18c0,0x08e1,0x3882,0x28a3,
56    0xcb7d,0xdb5c,0xeb3f,0xfb1e,0x8bf9,0x9bd8,0xabbb,0xbb9a,
57    0x4a75,0x5a54,0x6a37,0x7a16,0x0af1,0x1ad0,0x2ab3,0x3a92,
58    0xfd2e,0xed0f,0xdd6c,0xcd4d,0xbdaa,0xad8b,0x9de8,0x8dc9,
59    0x7c26,0x6c07,0x5c64,0x4c45,0x3ca2,0x2c83,0x1ce0,0x0cc1,
60    0xef1f,0xff3e,0xcf5d,0xdf7c,0xaf9b,0xbfba,0x8fd9,0x9ff8,
61    0x6e17,0x7e36,0x4e55,0x5e74,0x2e93,0x3eb2,0x0ed1,0x1ef0
62};
63
64unsigned short crc16_ccitt(const void *buf, int len)
65{
66    int counter;
67    unsigned short crc = 0;
68    for( counter = 0; counter < len; counter++)
69        crc = (crc<<8) ^ crc16tab[((crc>>8) ^ *(char *)buf++)&0x00FF];
70    return crc;
71}
72
73int rxmodem(unsigned char *dest)
74{
75    unsigned long *ptr = (unsigned long *) 0x0;
76    unsigned short crc, tcrc;
77    int i, pid = 1, len = 0;
78
79    for (i = 0; i < 0x100000; i++)
80    {
81        *ptr = 0;
82        ptr++;
83    }
84
85
86    uart_putstr("Receiving Xmodem transfer\n");
87    uart_getchar ();
88        for(i = 0; i < 0x20000000; i++) { asm("nop;"); }
89    uart_putchar ('C');
90
91    while(1)
92    {
93        int c, pid1, pid2;
94
95        c = uart_getchar ();
96        if (c != SOH)
97        {
98            if (c == EOT)
99            {
100                uart_putchar (ACK);
101                return len;
102            }
103            else
104                return 0;
105        }
106
107        pid1 = uart_getchar ();
108        pid2 = uart_getchar ();
109
110        if ((pid1 & 0xFF) != (~pid2 & 0xFF))
111            return 0;
112
113        if (pid1 != pid)
114            return 0;
115
116        for (i = 0; i < 130; i++)
117            *dest++ = uart_getchar ();
118
119        crc = crc16_ccitt (dest - 130, 128);
120        tcrc = (*(dest - 2)<<8) + *(dest - 1);
121        if (crc != tcrc)
122            return 0;
123        else
124        {
125            pid = (pid + 1) & 0xFF;
126            dest -= 2;
127            len += 128;
128            uart_putchar (ACK);
129        }
130    }
131}
132
lm32/logic/sakc/system.v
66
77module system
88#(
9    parameter bootram_file = "../firmware/boot0-serial/image.ram",
9    parameter bootram_file = "../firmware/loader_cain/image.ram",
1010    parameter clk_freq = 50000000,
1111    parameter uart_baud_rate = 57600
1212) (

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