Date:2010-05-04 18:17:38 (10 years 4 months ago)
Author:Carlos Camargo
Commit:de9acb468ba15672f9af810c4282f5f9b5ded833
Message:Adding write funtions to blink driver sample

Files: Examples/drivers/blink/blinker.c (2 diffs)
plasma/gpio/gpio.c (1 diff)
plasma/logic/Makefile (2 diffs)
plasma/logic/mlite_pack.vhd (1 diff)
plasma/logic/plasma.vhd (7 diffs)
plasma/logic/ram_image.vhd (4 diffs)

Change Details

Examples/drivers/blink/blinker.c
6161  return SUCCESS;
6262}
6363
64static ssize_t
65device_write(struct file *filp, const char *buff, size_t count, loff_t * off)
66{
67  const char cmd = buff[0];
68
69  if(cmd=='Q')
70  {
71    printk(KERN_INFO "Q...\n");
72    gpio_set_value(LED_PIN, 1);
73  }
74  else
75    if(cmd=='S'){
76      printk(KERN_INFO "S...\n");
77      gpio_set_value(LED_PIN, 0);
78    }
79
80  return 1;
81}
82
83
6484static int device_release(struct inode *inode, struct file *file)
6585{
6686  is_device_open = 0;
6787
68  gpio_set_value(LED_PIN, 0);
69
7088  module_put(THIS_MODULE);
7189
7290  printk( KERN_INFO "Close BLINKER\n" );
...... 
7694
7795struct file_operations fops = {
7896  .open = device_open,
97  .write = device_write,
7998  .release = device_release,
8099};
81100
plasma/gpio/gpio.c
3939  data16++;
4040
4141  *data32 = 0x30303030;
42  data32++;
43  *data32 = 0x31313131;
44
4245
4346  test8 = *data8;
4447  test16 = *data16;
plasma/logic/Makefile
1010#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
1111SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
1212
13SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd plasma_3e.vhd ram_image.vhd
13SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd ram_image.vhd
1414
1515all: bits
1616
...... 
5353build/project.ngc: build/project.xst $(SRC)
5454    cd build && xst -ifn project.xst -ofn project.log
5555
56build/project.ngd: build/project.ngc $(PINS)
57    cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
56build/project.ngd: build/project.ngc #$(PINS)
57    cd build && ngdbuild -p $(DEVICE) project.ngc #-uc ../$(PINS)
5858
5959build/project.ncd: build/project.ngd
6060    cd build && map -pr b -p $(DEVICE) project
plasma/logic/mlite_pack.vhd
414414
415415   component plasma
416416      generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
417              log_file : string := "UNUSED";
418              use_cache : std_logic := '0');
417              log_file : string := "UNUSED");
419418      port(clk : in std_logic;
420419           reset : in std_logic;
421420           uart_write : out std_logic;
422421           uart_read : in std_logic;
423422
424           address : out std_logic_vector(31 downto 2);
425           byte_we : out std_logic_vector(3 downto 0);
426           data_write : out std_logic_vector(31 downto 0);
427423           data_read : in std_logic_vector(31 downto 0);
428           mem_pause_in : in std_logic;
429
430           gpio0_out : out std_logic_vector(31 downto 0);
431           gpioA_in : in std_logic_vector(31 downto 0));
424           mem_pause_in : in std_logic
425      );
432426   end component; --plasma
433427
434428   component ddr_ctrl
plasma/logic/plasma.vhd
2020-- 0x20000030 GPIO0 Out Set bits
2121-- 0x20000040 GPIO0 Out Clear bits
2222-- 0x20000050 GPIOA In
2323---------------------------------------------------------------------
2424library ieee;
2525use ieee.std_logic_1164.all;
...... 
3527
3628entity plasma is
3729   generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
38           log_file : string := "UNUSED";
39           use_cache : std_logic := '0');
30           log_file : string := "UNUSED");
4031   port(clk : in std_logic;
4132        reset : in std_logic;
4233
4334        uart_write : out std_logic;
4435        uart_read : in std_logic;
4536
46        address : out std_logic_vector(31 downto 2);
47        byte_we : out std_logic_vector(3 downto 0);
48        data_write : out std_logic_vector(31 downto 0);
4937        data_read : in std_logic_vector(31 downto 0);
50        mem_pause_in : in std_logic;
51        gpio0_out : out std_logic_vector(31 downto 0);
52        gpioA_in : in std_logic_vector(31 downto 0));
38        mem_pause_in : in std_logic
39   );
5340end; --entity plasma
5441
5542architecture logic of plasma is
...... 
7057   signal enable_uart_read : std_logic;
7158   signal enable_uart_write : std_logic;
7259
73   signal gpio0_reg : std_logic_vector(31 downto 0);
7460   signal uart_write_busy : std_logic;
7561   signal uart_data_avail : std_logic;
7662   signal irq_mask_reg : std_logic_vector(7 downto 0);
7763   signal irq_status : std_logic_vector(7 downto 0);
7864   signal irq : std_logic;
79   signal counter_reg : std_logic_vector(31 downto 0);
8065
8166   signal ram_enable : std_logic;
8267   signal ram_byte_we : std_logic_vector(3 downto 0);
...... 
8469   signal ram_data_w : std_logic_vector(31 downto 0);
8570   signal ram_data_r : std_logic_vector(31 downto 0);
8671
87   signal cache_check : std_logic;
88   signal cache_checking : std_logic;
89   signal cache_miss : std_logic;
90   signal cache_hit : std_logic;
91
9272begin --architecture
93   write_enable <= '1' when cpu_byte_we /= "0000" else '0';
94   mem_busy <= mem_pause_in;
95   cache_hit <= cache_checking and not cache_miss;
96   cpu_pause <= '0'; --(uart_write_busy and enable_uart and write_enable) or --UART busy
97
98   enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
99   enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
100   enable_uart_read <= enable_uart and not write_enable;
101   enable_uart_write <= enable_uart and write_enable;
102   cpu_address(1 downto 0) <= "00";
103
73--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
74-- PROCESSOR
75--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
10476   u1_cpu: mlite_cpu
10577      generic map (memory_type => memory_type)
10678      PORT MAP (
...... 
12189         data_r => cpu_data_r,
12290         mem_pause => cpu_pause);
12391
124   opt_cache: if use_cache = '0' generate
125      cache_check <= '0';
126      cache_checking <= '0';
127      cache_miss <= '0';
128   end generate;
129
130   opt_cache2: if use_cache = '1' generate
131   --Control 4KB unified cache that uses the upper 4KB of the 8KB
132   --internal RAM. Only lowest 2MB of DDR is cached.
133   u_cache: cache
134      generic map (memory_type => memory_type)
135      PORT MAP (
136         clk => clk,
137         reset => reset,
138         address_next => address_next,
139         byte_we_next => byte_we_next,
140         cpu_address => cpu_address(31 downto 2),
141         mem_busy => mem_busy,
142
143         cache_check => cache_check, --Stage1: address_next in first 2MB DDR
144         cache_checking => cache_checking, --Stage2
145         cache_miss => cache_miss); --Stage3
146   end generate; --opt_cache2
92--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
93-- ADDRESS DECODER
94--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
95   write_enable <= '1' when cpu_byte_we /= "0000" else '0';
96   mem_busy <= mem_pause_in;
97   cpu_pause <= '0'; --(uart_write_busy and enable_uart and write_enable) or --UART busy
98-- (cpu_address(28) and mem_busy); --DDR or flash
99
100   enable_uart <= '1' when cpu_address(30 downto 28) = "010" and cpu_address(7 downto 4) = "0000" else '0';
101   enable_uart_read <= enable_uart and not write_enable;
102   enable_uart_write <= enable_uart and write_enable;
103   cpu_address(1 downto 0) <= "00";
104   ram_enable <= '1' when address_next(30 downto 28) = "000" else '0';
105   ram_byte_we <= byte_we_next;
106   ram_address(31 downto 13) <= ZERO(31 downto 13);
107   ram_address(12 downto 2) <= (address_next(12)) & address_next(11 downto 2);
108   ram_data_w <= cpu_data_w;
109
147110
148111   misc_proc: process(clk, reset, cpu_address, enable_misc,
149112      ram_data_r, data_read, data_read_uart, cpu_pause,
150      irq_mask_reg, irq_status, gpio0_reg, write_enable,
151      cache_checking,
152      gpioA_in, counter_reg, cpu_data_w)
113      irq_mask_reg, irq_status, write_enable,
114      cpu_data_w)
153115   begin
154116      case cpu_address(30 downto 28) is
155117      when "000" => --internal RAM
156118         cpu_data_r <= ram_data_r;
157119      when "001" => --external RAM
158         if cache_checking = '1' then
159            cpu_data_r <= ram_data_r; --cache
160         else
161120            cpu_data_r <= data_read; --DDR
162         end if;
163121      when "010" => --misc
164122         case cpu_address(6 downto 4) is
165123         when "000" => --uart
...... 
168126            cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
169127         when "010" => --irq_status
170128            cpu_data_r <= ZERO(31 downto 8) & irq_status;
171         when "011" => --gpio0
172            cpu_data_r <= gpio0_reg;
173         when "101" => --gpioA
174            cpu_data_r <= gpioA_in;
175         when "110" => --counter
176            cpu_data_r <= counter_reg;
177129         when others =>
178            cpu_data_r <= gpioA_in;
130            cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
179131         end case;
180132      when "011" => --flash
181133         cpu_data_r <= data_read;
182134      when others =>
183135         cpu_data_r <= ZERO;
184136      end case;
185
186      if reset = '1' then
187         irq_mask_reg <= ZERO(7 downto 0);
188         gpio0_reg <= ZERO;
189         counter_reg <= ZERO;
190      elsif rising_edge(clk) then
191         if cpu_pause = '0' then
192            if enable_misc = '1' and write_enable = '1' then
193               if cpu_address(6 downto 4) = "001" then
194                  irq_mask_reg <= cpu_data_w(7 downto 0);
195               elsif cpu_address(6 downto 4) = "011" then
196                  gpio0_reg <= gpio0_reg or cpu_data_w;
197               elsif cpu_address(6 downto 4) = "100" then
198                  gpio0_reg <= gpio0_reg and not cpu_data_w;
199               end if;
200            end if;
201         end if;
202         counter_reg <= bv_inc(counter_reg);
203      end if;
204   end process;
205
206   ram_enable <= '1' when address_next(30 downto 28) = "000" or cache_check = '1' or cache_miss = '1' else '0';
207   ram_byte_we <= byte_we_next when cache_miss = '0' else "1111";
208   ram_address(31 downto 13) <= ZERO(31 downto 13);
209   ram_address(12 downto 2) <= (address_next(12) or cache_check) & address_next(11 downto 2)
210            when cache_miss = '0' else
211            '1' & cpu_address(11 downto 2); --Update cache after cache miss
212   ram_data_w <= cpu_data_w when cache_miss = '0' else data_read;
137    end process;
213138
214139   u2_ram: ram
215140      generic map (memory_type => memory_type)
...... 
235160         busy_write => uart_write_busy,
236161         data_avail => uart_data_avail);
237162
238      address <= cpu_address(31 downto 2);
239      byte_we <= cpu_byte_we;
240      data_write <= cpu_data_w;
241      gpio0_out(28 downto 24) <= ZERO(28 downto 24);
242163
243164end; --architecture logic
244165
plasma/logic/ram_image.vhd
4545INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
4646INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
4747INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
48INIT_04 => X"913434ada5342434343ca5a5242434a134a1242434a034a024243434a024343c",
49INIT_05 => X"240800100080afafaf270003ac001030008c343c0003ac8c34943c908d349434",
50INIT_06 => X"2400afafafaf272703008f8f8f00140082000c2682000c241400100082260c00",
51INIT_07 => X"8f8c3c10000caf2730038c343c240827038f8f8f8f0216260c2424142c300224",
52INIT_08 => X"00000000000000000000000000000024038c0014ac00248c3c24243c3c270300",
48INIT_04 => X"ad343434343c3ca5a5242434a534a1242434a134a0242434a034a0242434343c",
49INIT_05 => X"0080afafaf270003ac001030008c343c0003ac8c34943c908d349434913434ad",
50INIT_06 => X"afaf272703008f8f8f00140082000c2682000c241400100082260c0024080010",
51INIT_07 => X"000caf2730038c343c240827038f8f8f8f0216260c2424142c3002242400afaf",
52INIT_08 => X"000000000000000000000024038c0014ac00248c3c24243c3c2703008f8c3c10",
5353INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
5454INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
5555INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
...... 
122122INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
123123INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
124124INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
125INIT_04 => X"868283a26342038b8d02422302038a828903020388e28cc302038786a2028504",
126INIT_05 => X"110080400082b1bfb0bd00e0a40040420062a30500e0a2a342860262a6844785",
127INIT_06 => X"1080bfb0b1b2bdbde000b0b1bf00400002400010020000045100400002100040",
128INIT_07 => X"bf6203400000bfbd42e06263030400bde0b0b1b2bf1211100064644062431211",
129INIT_08 => X"00000000000000040000802400800042e0a20083404584820563440302bde000",
125INIT_04 => X"8263428c8e0302634203028b238aa2030289038de2030288c387a20302868504",
126INIT_05 => X"0082b1bfb0bd00e0a40040420062a30500e0a2a342860262c6844785a68382c3",
127INIT_06 => X"b1b2bdbde000b0b1bf0040000240001002000004510040000210004011008040",
128INIT_07 => X"0000bfbd42e06263030400bde0b0b1b2bf12111000646440624312111080bfb0",
129INIT_08 => X"000000040000802400800042e0a20083404584820563440302bde000bf620340",
130130INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
131131INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
132132INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
...... 
199199INIT_01 => X"000000000000000000000000000000000000002000002000d800d800ff700000",
200200INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
201201INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
202INIT_04 => X"0020100000302220303000002120200020000000100010000000101000001020",
203INIT_05 => X"000080000000000000ff00000010ff000000002010000000aa00aa0000200030",
204INIT_06 => X"009000000000ff00001000000000ff000020000000000000ff00000000000020",
205INIT_07 => X"000020ff000000ff0000000020000000000000000010ffff00000000000010ff",
206INIT_08 => X"00000000000000200000002028000000000000ff001000001004040000000000",
202INIT_04 => X"0031303030313000002221200020002000200010000000100010000000101020",
203INIT_05 => X"0000000000ff00000010ff000000002010000000aa00aa000020003000102000",
204INIT_06 => X"0000ff00001000000000ff000020000000000000ff0000000000002000008000",
205INIT_07 => X"000000ff0000000020000000000000000010ffff00000000000010ff00900000",
206INIT_08 => X"000000200000002028000000000000ff001000001004040000000000000020ff",
207207INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
208208INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
209209INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
...... 
272272
273273   RAMB16_S9_inst3 : RAMB16_S9
274274   generic map (
275INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a005800700064006001",
276INIT_01 => X"504c4844403c3834302c2824201c18141000f12410200060125c1058fc005450",
275INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a006800800074007001",
276INIT_01 => X"504c4844403c3834302c2824201c18141000f52410200060125c1058fc005450",
277277INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
278278INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
279INIT_04 => X"0006080000302204003000002120020000001413030004001211020100100000",
280INIT_05 => X"0ac721160000141810e000080021fc020000200021080000aa00aa0000080004",
281INIT_06 => X"1c211c101418e020082110141800f5000021ac010000ac0df8000d000001ac21",
282INIT_07 => X"100000fd00f310e8010800200049ac20081014181c06f8fcac5730020a0f06fc",
283INIT_08 => X"00000000000000001010200000207084080000fb002104000064440000180800",
279INIT_04 => X"0031300004313000002221040002002014000004001312030002001110010000",
280INIT_05 => X"0000141810e000080021fc020000200021080000aa00aa000008000800080600",
281INIT_06 => X"1418e020082110141800f5000021b0010000b00df8000d000001b0210acb2116",
282INIT_07 => X"00f710e8010800200049b020081014181c06f8fcb05730020a0f06fc1c211c10",
283INIT_08 => X"000000001010200000207084080000fb002104000074540000180800100000fd",
284284INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
285285INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
286286INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",

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