Hardware Design: SIE
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Hardware Design: SIE Commit Details
Date: | 2010-04-01 07:58:08 (13 years 11 months ago) |
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Author: | Carlos Camargo |
Commit: | e68b12514372eae539cfed5fef282391c5222ce2 |
Message: | Adding new Example PIC |
Files: |
Examples/PIC/logic/Makefile (1 diff) Examples/PIC/logic/PIC.ucf (1 diff) Examples/PIC/logic/PIC.v (1 diff) docs/wiki/PIC.odg (0 diffs) docs/wiki/sw_hw_fpga_arch_sram.odg (0 diffs) |
Change Details
Examples/PIC/logic/Makefile | ||
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1 | DESIGN = PIC | |
2 | PINS = PIC.ucf | |
3 | DEVICE = xc3s250e-VQ100-4 | |
4 | BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \ | |
5 | -g CRC:enable -g StartUpClk:CCLK | |
6 | ||
7 | SIM_CMD = /opt/cad/modeltech/bin/vsim | |
8 | SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do | |
9 | #SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do | |
10 | SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) | |
11 | SAKC_IP = 192.168.254.101 | |
12 | ||
13 | SRC = PIC.v | |
14 | ||
15 | all: bits | |
16 | ||
17 | remake: clean-build all | |
18 | ||
19 | clean: | |
20 | rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat | |
21 | rm *.bit | |
22 | ||
23 | clean-build: clean | |
24 | rm -rf build | |
25 | ||
26 | cleanall: clean | |
27 | rm -rf build $(DESIGN).bit | |
28 | ||
29 | bits: $(DESIGN).bit | |
30 | ||
31 | # | |
32 | # Synthesis | |
33 | # | |
34 | build/project.src: | |
35 | @[ -d build ] || mkdir build | |
36 | @rm -f $@ | |
37 | for i in $(SRC); do echo verilog work ../$$i >> $@; done | |
38 | for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done | |
39 | ||
40 | build/project.xst: build/project.src | |
41 | echo "run" > $@ | |
42 | echo "-top $(DESIGN) " >> $@ | |
43 | echo "-p $(DEVICE)" >> $@ | |
44 | echo "-opt_mode Area" >> $@ | |
45 | echo "-opt_level 1" >> $@ | |
46 | echo "-ifn project.src" >> $@ | |
47 | echo "-ifmt mixed" >> $@ | |
48 | echo "-ofn project.ngc" >> $@ | |
49 | echo "-ofmt NGC" >> $@ | |
50 | echo "-rtlview yes" >> $@ | |
51 | ||
52 | build/project.ngc: build/project.xst $(SRC) | |
53 | cd build && xst -ifn project.xst -ofn project.log | |
54 | ||
55 | build/project.ngd: build/project.ngc $(PINS) | |
56 | cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS) | |
57 | ||
58 | build/project.ncd: build/project.ngd | |
59 | cd build && map -pr b -p $(DEVICE) project | |
60 | ||
61 | build/project_r.ncd: build/project.ncd | |
62 | cd build && par -w project project_r.ncd | |
63 | ||
64 | build/project_r.twr: build/project_r.ncd | |
65 | cd build && trce -v 25 project_r.ncd project.pcf | |
66 | ||
67 | $(DESIGN).bit: build/project_r.ncd build/project_r.twr | |
68 | cd build && bitgen project_r.ncd -l -w $(BGFLAGS) | |
69 | @mv -f build/project_r.bit $@ | |
70 | sim: | |
71 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do | |
72 | ||
73 | upload: $(DESIGN).bit | |
74 | scp $(DESIGN).bit root@$(SAKC_IP): |
Examples/PIC/logic/PIC.ucf | ||
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1 | NET clk LOC = "P38"; | |
2 | NET reset LOC = "P71"; | |
3 | NET led LOC = "P44"; | |
4 | ||
5 | #ADDRESS BUS | |
6 | NET "addr<12>" LOC = "P90"; | |
7 | NET "addr<11>" LOC = "P91"; | |
8 | NET "addr<10>" LOC = "P85"; | |
9 | NET "addr<9>" LOC = "P92"; | |
10 | NET "addr<8>" LOC = "P94"; | |
11 | NET "addr<7>" LOC = "P95"; | |
12 | NET "addr<6>" LOC = "P98"; | |
13 | NET "addr<5>" LOC = "P3"; | |
14 | NET "addr<4>" LOC = "P2"; | |
15 | NET "addr<3>" LOC = "P78"; | |
16 | NET "addr<2>" LOC = "P79"; | |
17 | NET "addr<1>" LOC = "P83"; | |
18 | NET "addr<0>" LOC = "P84"; | |
19 | ||
20 | #DATA BUS | |
21 | NET "sram_data<7>" LOC = "P4"; | |
22 | NET "sram_data<6>" LOC = "P5"; | |
23 | NET "sram_data<5>" LOC = "P9"; | |
24 | NET "sram_data<4>" LOC = "P10"; | |
25 | NET "sram_data<3>" LOC = "P11"; | |
26 | NET "sram_data<2>" LOC = "P12"; | |
27 | NET "sram_data<1>" LOC = "P15"; | |
28 | NET "sram_data<0>" LOC = "P16"; | |
29 | ||
30 | #CONTROL BUS | |
31 | NET "nwe" LOC = "P88"; | |
32 | NET "noe" LOC = "P86"; | |
33 | NET "ncs" LOC = "P69"; | |
34 | ||
35 | #ADC | |
36 | #NET "ADC_EOC" LOC = "P17"; | |
37 | #NET "ADC_SCLK" LOC = "P18"; | |
38 | #NET "ADC_SDIN" LOC = "P22"; | |
39 | #NET "ADC_SDOUT" LOC = "P23"; | |
40 | #NET "ADC_CS" LOC = "P24"; | |
41 | #NET "ADC_CSTART" LOC = "P26"; | |
42 | ||
43 |
Examples/PIC/logic/PIC.v | ||
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1 | module PIC ( DI, DO, addr, | |
2 | ISRC_LP, nIRQ, | |
3 | CS, nwe, noe, | |
4 | MCLK, | |
5 | RESET); | |
6 | ||
7 | input [7:0] DI; | |
8 | output [7:0] DO; | |
9 | input [6:0] addr; | |
10 | input [6:0] ISRC_LP; | |
11 | output nIRQ; | |
12 | input CS, nwe, noe; | |
13 | input MCLK, RESET; | |
14 | ||
15 | //------------------------------ | |
16 | // registros internos | |
17 | ||
18 | ||
19 | reg nIRQ; | |
20 | ||
21 | reg [7:0] DO; //Registro de salida. | |
22 | ||
23 | ||
24 | reg [7:0] IRQEnable; //Interrupt Mask | |
25 | reg IRQSoft; //Soft interrupt flag | |
26 | ||
27 | ||
28 | wire [7:0] ISRCF, IREG_LP; | |
29 | ||
30 | assign ISRCF = {ISRC_LP, IRQSoft}; // | |
31 | assign IREG_LP = ( ISRCF & IRQEnable); // | |
32 | ||
33 | ||
34 | always @(posedge MCLK) | |
35 | begin | |
36 | nIRQ <= ~(|IREG_LP); | |
37 | end | |
38 | ||
39 | ||
40 | always @(CS or addr or noe or IREG_LP or ISRCF or IRQEnable) | |
41 | begin | |
42 | if (~CS & noe) | |
43 | begin | |
44 | case (addr) | |
45 | 7'b0000000: DO<=IREG_LP; //IRQStatus | |
46 | 7'b0000001: DO<=ISRCF; //IRQRawStatus | |
47 | 7'b0000010: DO<=IRQEnable; //IRQEnable | |
48 | default: DO<=8'b0; | |
49 | endcase | |
50 | end | |
51 | else DO<=8'b0; | |
52 | end | |
53 | ||
54 | ||
55 | always @(posedge MCLK or posedge RESET) | |
56 | begin | |
57 | if (RESET) | |
58 | begin | |
59 | IRQEnable <= 8'b0; | |
60 | IRQSoft <= 1'b0; | |
61 | end | |
62 | else | |
63 | begin | |
64 | if (~CS & nwe) | |
65 | begin | |
66 | case (addr) | |
67 | 7'b0000010: IRQEnable <= ( DI | IRQEnable); //EnableSet | |
68 | 7'b0000011: IRQEnable <= (~DI & IRQEnable); //EnableClear | |
69 | 7'b0000100: IRQSoft <= DI[1]; //Programmed IRQ | |
70 | default: ; | |
71 | endcase | |
72 | end | |
73 | end | |
74 | end | |
75 | ||
76 | ||
77 | ||
78 | ||
79 | endmodule |
docs/wiki/PIC.odg |
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docs/wiki/sw_hw_fpga_arch_sram.odg |
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