Date:2010-10-12 17:23:50 (12 years 11 months ago)
Author:César Pedraza
Commit:ece832aa3a3866378a14232abb21e6adc498f9ab
Message:logic fixed
Files: Examples/ehw4/logic/ehw.v (8 diffs)

Change Details

Examples/ehw4/logic/ehw.v
1
2// REG OFFSET 1000h
3//reg0(32bit)W 0h
4//reg1(32bit)W 4h
5//reg2(32bit)W 8h
6//reg3(32bit)W Ch
7//reg4(32bit)W 10h
8//error(16bit)R 14h
9//status(16bit)R 16h
10//mt_rnd(32bit)R 18h
11//max_lev(8bit)W 1Ch
12//control(8bit)W 1Dh
13//max_com(16bit)W 1Eh
14
15
116`timescale 1ns / 1ps
217module ehw(clk, sram_data, addr, nwe, ncs, noe, reset, led,
318                irq_pin);
...... 
1227    // synchronize signals
1328    reg sncs, snwe;
1429    reg [12:0] buffer_addr;
15    reg [B:0] buffer_data;
30    reg [B:0] buffer_data;
31     wire led;
1632
1733    // bram-cpu interfaz
1834    reg we;
1935    reg w_st=0;
2036    reg [B:0] wdBus;
21    wire [B:0] rdBus;
37    reg [B:0] rdBus;
2238    wire [12:0] addr;
2339    reg [7:0] bae;
2440
...... 
2743    wire we_eval, en_ev;
2844    wire [63:0] ev_do;
2945    wire [63:0] ev_di;
30
46    wire [63:0] ev_do_aux;
47    wire [63:0] ev_di_aux;
48
3149    // Interconnection
3250    wire [31:0] mt_rnd;
3351    wire [31:0] reg0;
...... 
3553    wire [31:0] reg2;
3654    wire [31:0] reg3;
3755    wire [31:0] reg4;
38    wire [7:0] status;
56    wire [15:0] status;
57     wire [15:0] status_aux;
3958    wire [15:0] error;
4059    wire [8:0] evalfit_addr;
4160
...... 
4463    wire [3:0] max_lev;
4564    wire [7:0] control;
4665
47     // Test : LED blinking
66    reg [7:0] reg_bank [31:0];
67    wire enReg;
68    wire [4:0] address;
69
70// Test : LED blinking
4871    reg [25:0] counter;
4972    always @(posedge clk) begin
5073        if (~reset)
...... 
5477    end
5578    assign led = counter[24];
5679
57    // Data Bus direction control
80// Data Bus direction control
5881    wire T = ~noe | ncs;
5982    assign sram_data = T?8'bZ:rdBus;
6083
61    // synchronize assignment
84// synchronize assignment
6285    always @(negedge clk)
6386    begin
6487        sncs <= ncs;
...... 
6790        buffer_addr <= addr;
6891    end
6992
70    // write access cpu to bram
93// write access cpu to bram
7194    always @(posedge clk)
7295    if(~reset) {w_st, we, wdBus} <= 0;
7396      else begin
...... 
110133     else
111134       bae <= 8'h00;
112135   end
136    wire en1, en2; // enable memory signals
137    assign en0 = bae[0] | bae[1] | bae[2] | bae[3];
138    assign en1 = bae[4] | bae[5] | bae[6] | bae[7];
113139
140    reg[31:0] DIA_Aux;
141    always @ (posedge clk) begin
142        if (bae[0]) DIA_Aux[7:0] = wdBus[7:0];
143        if (bae[1]) DIA_Aux[15:8] = wdBus[7:0];
144        if (bae[2]) DIA_Aux[23:16] = wdBus[7:0];
145        if (bae[3]) DIA_Aux[31:24] = wdBus[7:0];
146        if (bae[4]) DIA_Aux[7:0] = wdBus[7:0];
147        if (bae[5]) DIA_Aux[15:8] = wdBus[7:0];
148        if (bae[6]) DIA_Aux[23:16] = wdBus[7:0];
149        if (bae[7]) DIA_Aux[31:24] = wdBus[7:0];
150    end
114151
115 // Memories
116
117RAMB16_S4_S4 ba0( .CLKA(~clk), .ENA(bae[0]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
118                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[3:0]), .DOB(ev_di[3:0])); //D3-D0
119RAMB16_S4_S4 ba1( .CLKA(~clk), .ENA(bae[0]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
120                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[7:4]), .DOB(ev_di[7:4])); //D7-D4
121
122RAMB16_S4_S4 ba2( .CLKA(~clk), .ENA(bae[1]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
123                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[11:8]), .DOB(ev_di[11:8])); //D11-D8
124RAMB16_S4_S4 ba3( .CLKA(~clk), .ENA(bae[1]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
125                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[15:12]), .DOB(ev_di[15:12]));//D15-D12
152    reg [2:0] state, nextstate; //FSM for write in 32bit mode to memory
153    wire we0, we1;
154    wire nreset;
155    assign nreset = ~reset;
156    parameter S0 = 3'b000;
157    parameter S1 = 3'b001;
158    parameter S2 = 3'b010;
159
160    always @ (posedge clk, posedge nreset)
161    if (nreset) state <= S0;
162    else state <= nextstate;
163    // next state logic
164    always@(*)
165        case (state)
166        S0:if (bae[3]&we) nextstate = S1;
167            else
168                if (bae[7]&we) nextstate = S2;
169                else nextstate = S0;
170        S1: nextstate = S0;
171        S2: nextstate = S0;
172        default: nextstate = S0;
173        endcase
174    // output logic
175    assign we0 = (state == S1);
176    assign we1 = (state == S2);
126177
127RAMB16_S4_S4 ba4( .CLKA(~clk), .ENA(bae[2]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
128                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[19:16]), .DOB(ev_di[19:16])); //D19-D16
129RAMB16_S4_S4 ba5( .CLKA(~clk), .ENA(bae[2]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
130                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[23:20]), .DOB(ev_di[23:20])); //D23-D20
131
132RAMB16_S4_S4 ba6( .CLKA(~clk), .ENA(bae[3]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
133                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[27:24]), .DOB(ev_di[27:24])); //D27-D24
134RAMB16_S4_S4 ba7( .CLKA(~clk), .ENA(bae[3]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
135                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[31:28]), .DOB(ev_di[31:28])); //D31-D28
178// Read control
179    reg [7:0] MemDOA;
180    wire [63:0] DOA_Aux;
181
182    always @(posedge clk)
183      if(~reset)begin
184         rdBus = 8'h00;
185            end
186      else begin
187            if(enReg)
188                rdBus = reg_bank[address];
189                else
190                    rdBus = MemDOA[7:0];
191      end
192// memory output mux
193    always @(buffer_addr[2:0])
194        case (buffer_addr[2:0])
195            0 : MemDOA = DOA_Aux[7:0];
196            1 : MemDOA = DOA_Aux[15:8];
197            2 : MemDOA = DOA_Aux[23:16];
198            3 : MemDOA = DOA_Aux[31:24];
199            4 : MemDOA = DOA_Aux[39:32];
200            5 : MemDOA = DOA_Aux[47:40];
201            6 : MemDOA = DOA_Aux[55:48];
202            7 : MemDOA = DOA_Aux[63:56];
203            default: MemDOA = 8'h00;
204        endcase
205
206// Store Inputs
207    always @(posedge clk)
208     begin
209      if(enReg) begin
210            reg_bank[0] = reg0[7:0];
211            reg_bank[1] = reg0[15:8];
212            reg_bank[2] = reg0[23:16];
213            reg_bank[3] = reg0[31:24];
214            reg_bank[4] = reg1[7:0];
215            reg_bank[5] = reg1[15:8];
216            reg_bank[6] = reg1[23:16];
217            reg_bank[7] = reg1[31:24];
218            reg_bank[8] = reg2[7:0];
219            reg_bank[9] = reg2[15:8];
220            reg_bank[10] = reg2[23:16];
221            reg_bank[11] = reg2[31:24];
222            reg_bank[12] = reg3[7:0];
223            reg_bank[13] = reg3[15:8];
224            reg_bank[14] = reg3[23:16];
225            reg_bank[15] = reg3[31:24];
226            reg_bank[16] = reg4[7:0];
227            reg_bank[17] = reg4[15:8];
228            reg_bank[18] = reg4[23:16];
229            reg_bank[19] = reg4[31:24];
230            reg_bank[20] = error[7:0];
231            reg_bank[21] = error[15:8];
232            reg_bank[22] = status[7:0];
233            reg_bank[23] = status[15:8];
234            reg_bank[24] = mt_rnd[7:0];
235            reg_bank[25] = mt_rnd[15:8];
236            reg_bank[26] = mt_rnd[23:16];
237            reg_bank[27] = mt_rnd[31:24];
238      end
239     end
136240
137RAMB16_S4_S4 ba8( .CLKA(~clk), .ENA(bae[4]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
138                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[35:32]), .DOB(ev_di[35:32])); //D35-D32
139RAMB16_S4_S4 ba9( .CLKA(~clk), .ENA(bae[4]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
140                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[39:36]), .DOB(ev_di[39:36])); //D39-D36
241    assign address[4:0] = buffer_addr[4:0];
242    assign enReg = buffer_addr[12];
243// assign reg0[7:0] = reg_bank[0];
244// assign reg0[15:8] = reg_bank[1];
245// assign reg0[23:16] = reg_bank[2];
246// assign reg0[31:24] = reg_bank[3];
247// assign reg1[7:0] = reg_bank[4];
248// assign reg1[15:8] = reg_bank[5];
249// assign reg1[23:16] = reg_bank[6];
250// assign reg1[31:24] = reg_bank[7];
251// assign reg2[7:0] = reg_bank[8];
252// assign reg2[15:8] = reg_bank[9];
253// assign reg2[23:16] = reg_bank[10];
254// assign reg2[31:24] = reg_bank[11];
255// assign reg3[7:0] = reg_bank[12];
256// assign reg3[15:8] = reg_bank[13];
257// assign reg3[23:16] = reg_bank[14];
258// assign reg3[31:24] = reg_bank[15];
259// assign reg4[7:0] = reg_bank[16];
260// assign reg4[15:8] = reg_bank[17];
261// assign reg4[23:16] = reg_bank[18];
262// assign reg4[31:24] = reg_bank[19];
263    assign max_lev[3:0] = reg_bank[28][3:0];
264    assign control[7:0] = reg_bank[29];
265    assign max_com[7:0] = reg_bank[30];
266    assign max_com[15:8] = reg_bank[31];
267    // Write control
268    always @(negedge clk)
269    if(we & enReg) begin
270      case (address)
271// 0: reg_bank[0] = wdBus;
272// 1: reg_bank[1] = wdBus;
273// 2: reg_bank[2] = wdBus;
274// 3: reg_bank[3] = wdBus;
275// 4: reg_bank[4] = wdBus;
276// 5: reg_bank[5] = wdBus;
277// 6: reg_bank[6] = wdBus;
278// 7: reg_bank[7] = wdBus;
279// 8: reg_bank[8] = wdBus;
280// 9: reg_bank[9] = wdBus;
281// 10: reg_bank[10] = wdBus;
282// 11: reg_bank[11] = wdBus;
283// 12: reg_bank[12] = wdBus;
284// 13: reg_bank[13] = wdBus;
285// 14: reg_bank[14] = wdBus;
286// 15: reg_bank[15] = wdBus;
287// 16: reg_bank[16] = wdBus;
288// 17: reg_bank[17] = wdBus;
289// 18: reg_bank[18] = wdBus;
290// 19: reg_bank[19] = wdBus;
291         28: reg_bank[28] = wdBus;
292         29: reg_bank[29] = wdBus;
293         30: reg_bank[30] = wdBus;
294         31: reg_bank[31] = wdBus;
295      endcase
296    end
297assign irq_pin = 0;
298//assign ev_do_aux = {ev_do[7:0], ev_do[15:8], ev_do[23:16], ev_do[31:24], ev_do[39:32], ev_do[47:40], ev_do[55:48], ev_do[63:56]};
299//assign ev_di = {ev_di_aux[7:0], ev_di_aux[15:8], ev_di_aux[23:16], ev_di_aux[31:24], ev_di_aux[39:32], ev_di_aux[47:40], ev_di_aux[55:48], ev_di_aux[63:56]};
300assign ev_do_aux[63:32] = ev_do[31:0];
301assign ev_do_aux[31:16] = ev_do[47:32];
302assign ev_do_aux[15:0] = ev_do[63:48];
141303
142RAMB16_S4_S4 ba10(.CLKA(~clk), .ENA(bae[5]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
143                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[43:40]), .DOB(ev_di[43:40])); //D43-D40
144RAMB16_S4_S4 ba11(.CLKA(~clk), .ENA(bae[5]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
145                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[47:44]), .DOB(ev_di[47:44])); //D47-D44
304assign ev_di[63:32] = ev_di_aux[31:0]; //Endianess adjust for 32-bit level data
305assign ev_di[31:16] = ev_di_aux[47:32]; //endianess adjust for 16-bit LUT
306assign ev_di[7:0] = ev_di_aux[63:56]; //endianess adjust for 8-bit VARS
307assign ev_di[15:8] = ev_di_aux[55:48]; //endianess adjust for 8-bit VARS
146308
147RAMB16_S4_S4 ba12(.CLKA(~clk), .ENA(bae[6]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
148                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[51:48]), .DOB(ev_di[51:48])); //D51-D48
149RAMB16_S4_S4 ba13(.CLKA(~clk), .ENA(bae[6]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
150                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[55:52]), .DOB(ev_di[55:52])); //D55-D52
151309
152RAMB16_S4_S4 ba14(.CLKA(~clk), .ENA(bae[7]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
153                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[59:56]), .DOB(ev_di[59:56])); //D59-D56
154RAMB16_S4_S4 ba15(.CLKA(~clk), .ENA(bae[7]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
155                  .CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[63:60]), .DOB(ev_di[63:60])); //D63-D60
310assign status[14:0] = status_aux[14:0];
156311
157 // evalfit_peripheral
158evalfit_peripheral evalfit( .clk(clk), .reset(reset), .habilita(control[0]), .maxcombs(max_com), .nivel_max(max_lev),
159                            .peripheral_mem_in(ev_di), .peripheral_mem_en(en_eval), .peripheral_mem_out(ev_do), .peripheral_mem_we(we_eval),
160                            .peripheral_mem_addr(evalfit_addr), .evalfit3_estado(status), .errores(error),
161                            .fin_ack(irq_pin), .reg0_s(reg0), .reg1_s(reg1), .reg2_s(reg2), .reg3_s(reg3), .reg4_s(reg4));
312RAMB16_S36_S36 #(.INIT_00(256'hABCDEF00_00000000_00000000_00000000_00000000_00000000_00000000_76543210) )
313                    mem0 ( .CLKA(clk), .ENA(en0), .SSRA(1'b0), .ADDRA(buffer_addr[11:3]), .WEA(we0), .DIA(DIA_Aux[31:0]), .DIPA(1'b0), .DOA(DOA_Aux[31:0]),
314                  .CLKB(clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval), .DIB(ev_do_aux[31:0]), .DIPB(1'b0), .DOB(ev_di_aux[31:0]));
315
316RAMB16_S36_S36 #(.INIT_00(256'hCE5A4000_00000000_00000000_00000000_00000000_00000000_00000000_78111300) )
317                    mem1( .CLKA(clk), .ENA(en1), .SSRA(1'b0), .ADDRA(buffer_addr[11:3]), .WEA(we1), .DIA(DIA_Aux[31:0]), .DIPA(0'b0), .DOA(DOA_Aux[63:32]),
318                  .CLKB(clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval), .DIB(ev_do_aux[63:32]), .DIPB(0'b0), .DOB(ev_di_aux[63:32]));
162319
163reg_bank RegBank( .clk(clk), .reset(reset), .en(buffer_addr[12]), .we(we), .wdBus(wdBus), .rdBus(rdBus), .address(buffer_addr[4:0]),
164                  .reg0(reg0), .reg1(reg1), .reg2(reg2), .reg3(reg3), .reg4(reg4), .error(error), .status(status),
165                  .max_com(max_com), .max_lev(max_lev), .control(control));
320// evalfit_peripheral
321evalfit_peripheral evalfit( .clk(clk), .reset(control[7]), .habilita(control[6]), .maxcombs(max_com), .nivel_max(max_lev),
322                            .peripheral_mem_in(ev_di), .peripheral_mem_en(en_ev), .peripheral_mem_out(ev_do), .peripheral_mem_we(we_eval),
323                            .peripheral_mem_addr(evalfit_addr), .evalfit3_estado(status_aux[15:0]), .errores(error),
324                            .fin_ack(status[15]), .reg0_s(reg0), .reg1_s(reg1), .reg2_s(reg2), .reg3_s(reg3), .reg4_s(reg4));
166325
167// mt_mem
168 mt_mem random( .clk(clk), .ena(1'b1), .resetn(~reset), .random(mt_rnd));
326// MersenneTwister
327 mt_mem random( .clk(clk), .ena(1'b1), .resetn(reset), .random(mt_rnd));
169328
170
171329endmodule
172330

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