Date:2010-05-10 22:08:00 (13 years 7 months ago)
Author:Carlos Camargo
Commit:fa1b48e1c220b1478ddc15cd2fca2faf3d076d32
Message:Adding plasma test_bench files
Files: plasma/logic/plasma_TB.v (1 diff)
plasma/logic/plasma_TB.vhd (1 diff)

Change Details

plasma/logic/plasma_TB.v
1`timescale 1ns / 1ps
2
3module plasma_TB_v;
4
5   reg clk;
6   reg reset;
7
8
9   plasma uut( .clk(clk), .reset(reset));
10
11
12   parameter PERIOD = 20;
13   parameter real DUTY_CYCLE = 0.5;
14   parameter OFFSET = 0;
15   parameter TSET = 3;
16   parameter THLD = 3;
17   parameter NWS = 3;
18   parameter CAM_OFF = 4000;
19
20     reg [15:0] data_tx;
21
22
23    event reset_trigger;
24    event reset_done_trigger;
25
26    initial begin // Reset the system, Start the image capture process
27      forever begin
28        @ (reset_trigger);
29        @ (negedge clk);
30        reset = 1;
31        @ (negedge clk);
32        reset = 0;
33        -> reset_done_trigger;
34      end
35    end
36
37
38    initial begin // Initialize Inputs
39      clk = 0;
40    end
41
42   initial begin // Process for clk
43     #OFFSET;
44     forever
45     begin
46       clk = 1'b0;
47       #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
48       #(PERIOD*DUTY_CYCLE);
49     end
50   end
51
52 initial begin: TEST_CASE
53     #10 -> reset_trigger;
54     @ (reset_done_trigger);
55     // Write data to SRAM
56 end
57endmodule
58
plasma/logic/plasma_TB.vhd
1---------------------------------------------------------------------
2-- TITLE: Test Bench
3-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
4-- DATE CREATED: 4/21/01
5-- FILENAME: tbench.vhd
6-- PROJECT: Plasma CPU core
7-- COPYRIGHT: Software placed into the public domain by the author.
8-- Software 'as is' without warranty. Author liable for nothing.
9-- DESCRIPTION:
10-- This entity provides a test bench for testing the Plasma CPU core.
11---------------------------------------------------------------------
12library ieee;
13use ieee.std_logic_1164.all;
14use work.mlite_pack.all;
15use ieee.std_logic_unsigned.all;
16
17entity tbench is
18end; --entity tbench
19
20architecture logic of tbench is
21   constant memory_type : string :=
22   "TRI_PORT_X";
23-- "DUAL_PORT_";
24-- "ALTERA_LPM";
25-- "XILINX_16X";
26
27   constant log_file : string :=
28-- "UNUSED";
29   "output.txt";
30
31   signal clk : std_logic := '1';
32   signal reset : std_logic := '1';
33   signal interrupt : std_logic := '0';
34   signal mem_write : std_logic;
35   signal address : std_logic_vector(31 downto 2);
36   signal data_write : std_logic_vector(31 downto 0);
37   signal data_read : std_logic_vector(31 downto 0);
38   signal pause1 : std_logic := '0';
39   signal pause2 : std_logic := '0';
40   signal pause : std_logic;
41   signal byte_we : std_logic_vector(3 downto 0);
42   signal uart_write : std_logic;
43   signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
44begin --architecture
45   --Uncomment the line below to test interrupts
46   --interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
47
48   clk <= not clk after 50 ns;
49   reset <= '0' after 500 ns;
50   pause <= '0';
51
52   u1_plasma: plasma
53      generic map (memory_type => memory_type,
54                   log_file => log_file)
55      PORT MAP (
56         clk => clk,
57         reset => reset,
58         uart_read => uart_write,
59         uart_write => uart_write,
60         data_read => data_read,
61         mem_pause_in => pause
62     );
63
64end; --architecture logic

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