Hardware Design: SIE
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Hardware Design: SIE Git Source Tree
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Source at commit 079d8042f6e48a7c0f86a7ef21c397248666706a created 13 years 10 months ago. By Carlos Camargo, Adding iverilog simulation support | |
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1 | m255 |
2 | 13 |
3 | cModel Technology |
4 | d/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/Examples/sram/logic/simulation |
5 | vglbl |
6 | IT?5S;>bN`@zG_25]R_4A33 |
7 | VnN]4Gon>inod6>M^M2[SV1 |
8 | w1273510321 |
9 | Fglbl.v |
10 | L0 5 |
11 | OE;L;6.0d;29 |
12 | r1 |
13 | 31 |
14 | vsram_bus |
15 | IhWan4YkPClmK5z;GkOZUS2 |
16 | V7bnNHP1kz?3UaZfjPj4WE1 |
17 | w1273543976 |
18 | F../build/project.v |
19 | L0 37 |
20 | OE;L;6.0d;29 |
21 | r1 |
22 | 31 |
23 | vsram_bus_TB |
24 | IeNSImUgW[X4l`QoUVUKI`3 |
25 | V<VFiY^801Z<UUJ?^z?JM20 |
26 | w1273543928 |
27 | F../sram_bus_TB.v |
28 | L0 3 |
29 | OE;L;6.0d;29 |
30 | r1 |
31 | 31 |
32 | nsram_bus_@t@b |
33 | vsram_bus_TB_v |
34 | IA=m;kT@<eh:`ekMlOPXX@0 |
35 | VQ[@Nfjd=de;Dc[[gj0bf41 |
36 | w1273541944 |
37 | F../sram_bus_TB.v |
38 | L0 3 |
39 | OE;L;6.0d;29 |
40 | r1 |
41 | 31 |
42 | o+libext+.v |
43 | nsram_bus_@t@b_v |
44 |
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master