Root/Examples/sram/logic/simulation/work/_info

Source at commit 079d8042f6e48a7c0f86a7ef21c397248666706a created 13 years 10 months ago.
By Carlos Camargo, Adding iverilog simulation support
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3cModel Technology
4d/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/Examples/sram/logic/simulation
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18F../build/project.v
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24IeNSImUgW[X4l`QoUVUKI`3
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37F../sram_bus_TB.v
38L0 3
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