Hardware Design: SIE
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Source at commit 079d8042f6e48a7c0f86a7ef21c397248666706a created 13 years 10 months ago. By Carlos Camargo, Adding iverilog simulation support | |
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1 | `timescale 1ns / 1ps |
2 | module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led); |
3 | parameter B = (7); |
4 | |
5 | input clk, nwe, ncs, noe, reset; |
6 | input [12:0] addr; |
7 | inout [B:0] sram_data; |
8 | output led; |
9 | |
10 | // synchronize signals |
11 | reg sncs, snwe; |
12 | reg [12:0] buffer_addr; |
13 | reg [B:0] buffer_data; |
14 | |
15 | // interfaz fpga signals |
16 | // wire [12:0] addr; |
17 | |
18 | // bram interfaz signals |
19 | reg we; |
20 | reg w_st; |
21 | |
22 | reg [B:0] wdBus; |
23 | wire [B:0] rdBus; |
24 | |
25 | // interefaz signals assignments |
26 | wire T = ~noe | ncs; |
27 | assign sram_data = T?8'bZ:rdBus; |
28 | |
29 | //-------------------------------------------------------------------------- |
30 | |
31 | // synchronize assignment |
32 | always @(negedge clk) |
33 | begin |
34 | sncs <= ncs; |
35 | snwe <= nwe; |
36 | buffer_data <= sram_data; |
37 | buffer_addr <= addr; |
38 | end |
39 | |
40 | // write access cpu to bram |
41 | always @(posedge clk) |
42 | if(reset) {w_st, we, wdBus} <= 0; |
43 | else begin |
44 | wdBus <= buffer_data; |
45 | case (w_st) |
46 | 0: begin |
47 | we <= 0; |
48 | if(sncs | snwe) w_st <= 1; |
49 | end |
50 | 1: begin |
51 | if(~(sncs | snwe)) begin |
52 | we <= 1; |
53 | w_st <= 0; |
54 | end |
55 | else we <= 0; |
56 | end |
57 | endcase |
58 | end |
59 | |
60 | RAMB16_S2 ba0( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr), |
61 | .WE(we), .DI(wdBus[1:0]), .DO(rdBus[1:0]) ); |
62 | |
63 | RAMB16_S2 ba1( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr), |
64 | .WE(we), .DI(wdBus[3:2]), .DO(rdBus[3:2]) ); |
65 | |
66 | RAMB16_S2 ba2( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr), |
67 | .WE(we), .DI(wdBus[5:4]), .DO(rdBus[5:4]) ); |
68 | |
69 | RAMB16_S2 ba3( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr), |
70 | .WE(we), .DI(wdBus[7:6]), .DO(rdBus[7:6]) ); |
71 | |
72 | reg [24:0] counter; |
73 | always @(posedge clk) begin |
74 | if (reset) |
75 | counter <= {25{1'b0}}; |
76 | else |
77 | counter <= counter + 1; |
78 | end |
79 | assign led = counter[24]; |
80 | |
81 | endmodule |
82 | |
83 |
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