Hardware Design: SIE
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Source at commit 43de1a582cae639ee5d44fafba2bccd110b9460f created 13 years 5 months ago. By Carlos Camargo, Fixing cai9n loader for lm32 errors | |
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1 | //--------------------------------------------------------------------------- |
2 | // LatticeMico32 System On A Chip |
3 | // |
4 | // Top Level Design for the Xilinx Spartan 3-200 Starter Kit |
5 | //--------------------------------------------------------------------------- |
6 | |
7 | module system |
8 | #( |
9 | parameter bootram_file = "../firmware/cain_loader/image.ram", |
10 | // parameter bootram_file = "../firmware/boot0-serial/image.ram", |
11 | parameter clk_freq = 50000000, |
12 | parameter uart_baud_rate = 57600 |
13 | ) ( |
14 | input clk, |
15 | // Debug |
16 | output led, |
17 | input rst, |
18 | // UART |
19 | input uart_rxd, |
20 | output uart_txd, |
21 | // CPU Interface |
22 | input [12:0] addr, |
23 | input [7:0] sram_data, |
24 | input nwe, |
25 | input noe, |
26 | input ncs |
27 | ); |
28 | |
29 | //------------------------------------------------------------------ |
30 | // Whishbone Wires |
31 | //------------------------------------------------------------------ |
32 | wire gnd = 1'b0; |
33 | wire [3:0] gnd4 = 4'h0; |
34 | wire [31:0] gnd32 = 32'h00000000; |
35 | |
36 | |
37 | wire [31:0] lm32i_adr, |
38 | lm32d_adr, |
39 | uart0_adr, |
40 | timer0_adr, |
41 | gpio0_adr, |
42 | bram0_adr, |
43 | sram0_adr; |
44 | |
45 | |
46 | wire [31:0] lm32i_dat_r, |
47 | lm32i_dat_w, |
48 | lm32d_dat_r, |
49 | lm32d_dat_w, |
50 | uart0_dat_r, |
51 | uart0_dat_w, |
52 | timer0_dat_r, |
53 | timer0_dat_w, |
54 | gpio0_dat_r, |
55 | gpio0_dat_w, |
56 | bram0_dat_r, |
57 | bram0_dat_w, |
58 | sram0_dat_w, |
59 | sram0_dat_r; |
60 | |
61 | wire [3:0] lm32i_sel, |
62 | lm32d_sel, |
63 | uart0_sel, |
64 | timer0_sel, |
65 | gpio0_sel, |
66 | bram0_sel, |
67 | sram0_sel; |
68 | |
69 | wire lm32i_we, |
70 | lm32d_we, |
71 | uart0_we, |
72 | timer0_we, |
73 | gpio0_we, |
74 | bram0_we, |
75 | sram0_we; |
76 | |
77 | wire lm32i_cyc, |
78 | lm32d_cyc, |
79 | uart0_cyc, |
80 | timer0_cyc, |
81 | gpio0_cyc, |
82 | bram0_cyc, |
83 | sram0_cyc; |
84 | |
85 | wire lm32i_stb, |
86 | lm32d_stb, |
87 | uart0_stb, |
88 | timer0_stb, |
89 | gpio0_stb, |
90 | bram0_stb, |
91 | sram0_stb; |
92 | |
93 | wire lm32i_ack, |
94 | lm32d_ack, |
95 | uart0_ack, |
96 | timer0_ack, |
97 | gpio0_ack, |
98 | bram0_ack, |
99 | sram0_ack; |
100 | |
101 | wire lm32i_rty, |
102 | lm32d_rty; |
103 | |
104 | wire lm32i_err, |
105 | lm32d_err; |
106 | |
107 | wire lm32i_lock, |
108 | lm32d_lock; |
109 | |
110 | wire [2:0] lm32i_cti, |
111 | lm32d_cti; |
112 | |
113 | wire [1:0] lm32i_bte, |
114 | lm32d_bte; |
115 | |
116 | //--------------------------------------------------------------------------- |
117 | // Interrupts |
118 | //--------------------------------------------------------------------------- |
119 | wire [31:0] intr_n; |
120 | wire uart0_intr = 0; |
121 | wire [1:0] timer0_intr; |
122 | wire gpio0_intr; |
123 | |
124 | assign intr_n = { 28'hFFFFFFF, ~timer0_intr[1], ~gpio0_intr, ~timer0_intr[0], ~uart0_intr }; |
125 | |
126 | //--------------------------------------------------------------------------- |
127 | // Wishbone Interconnect |
128 | //--------------------------------------------------------------------------- |
129 | wb_conbus_top #( |
130 | .s0_addr_w ( 3 ), |
131 | .s0_addr ( 3'h4 ), // sram0 |
132 | .s1_addr_w ( 3 ), |
133 | .s1_addr ( 3'h5 ), |
134 | .s27_addr_w( 15 ), |
135 | .s2_addr ( 15'h0000 ), // bram0 |
136 | .s3_addr ( 15'h7000 ), // uart0 |
137 | .s4_addr ( 15'h7001 ), // timer0 |
138 | .s5_addr ( 15'h7002 ), // gpio0 |
139 | .s6_addr ( 15'h7003 ), |
140 | .s7_addr ( 15'h7004 ) |
141 | ) conmax0 ( |
142 | .clk_i( clk ), |
143 | .rst_i( ~rst ), |
144 | // Master0 |
145 | .m0_dat_i( lm32i_dat_w ), |
146 | .m0_dat_o( lm32i_dat_r ), |
147 | .m0_adr_i( lm32i_adr ), |
148 | .m0_we_i ( lm32i_we ), |
149 | .m0_sel_i( lm32i_sel ), |
150 | .m0_cyc_i( lm32i_cyc ), |
151 | .m0_stb_i( lm32i_stb ), |
152 | .m0_ack_o( lm32i_ack ), |
153 | .m0_rty_o( lm32i_rty ), |
154 | .m0_err_o( lm32i_err ), |
155 | // Master1 |
156 | .m1_dat_i( lm32d_dat_w ), |
157 | .m1_dat_o( lm32d_dat_r ), |
158 | .m1_adr_i( lm32d_adr ), |
159 | .m1_we_i ( lm32d_we ), |
160 | .m1_sel_i( lm32d_sel ), |
161 | .m1_cyc_i( lm32d_cyc ), |
162 | .m1_stb_i( lm32d_stb ), |
163 | .m1_ack_o( lm32d_ack ), |
164 | .m1_rty_o( lm32d_rty ), |
165 | .m1_err_o( lm32d_err ), |
166 | // Master2 |
167 | .m2_dat_i( gnd32 ), |
168 | .m2_adr_i( gnd32 ), |
169 | .m2_sel_i( gnd4 ), |
170 | .m2_cyc_i( gnd ), |
171 | .m2_stb_i( gnd ), |
172 | // Master3 |
173 | .m3_dat_i( gnd32 ), |
174 | .m3_adr_i( gnd32 ), |
175 | .m3_sel_i( gnd4 ), |
176 | .m3_cyc_i( gnd ), |
177 | .m3_stb_i( gnd ), |
178 | // Master4 |
179 | .m4_dat_i( gnd32 ), |
180 | .m4_adr_i( gnd32 ), |
181 | .m4_sel_i( gnd4 ), |
182 | .m4_cyc_i( gnd ), |
183 | .m4_stb_i( gnd ), |
184 | // Master5 |
185 | .m5_dat_i( gnd32 ), |
186 | .m5_adr_i( gnd32 ), |
187 | .m5_sel_i( gnd4 ), |
188 | .m5_cyc_i( gnd ), |
189 | .m5_stb_i( gnd ), |
190 | // Master6 |
191 | .m6_dat_i( gnd32 ), |
192 | .m6_adr_i( gnd32 ), |
193 | .m6_sel_i( gnd4 ), |
194 | .m6_cyc_i( gnd ), |
195 | .m6_stb_i( gnd ), |
196 | // Master7 |
197 | .m7_dat_i( gnd32 ), |
198 | .m7_adr_i( gnd32 ), |
199 | .m7_sel_i( gnd4 ), |
200 | .m7_cyc_i( gnd ), |
201 | .m7_stb_i( gnd ), |
202 | |
203 | // Slave0 |
204 | .s0_dat_i( sram0_dat_r ), |
205 | .s0_dat_o( sram0_dat_w ), |
206 | .s0_adr_o( sram0_adr ), |
207 | .s0_sel_o( sram0_sel ), |
208 | .s0_we_o( sram0_we ), |
209 | .s0_cyc_o( sram0_cyc ), |
210 | .s0_stb_o( sram0_stb ), |
211 | .s0_ack_i( sram0_ack ), |
212 | .s0_err_i( gnd ), |
213 | .s0_rty_i( gnd ), |
214 | // Slave1 |
215 | .s1_dat_i( gnd32 ), |
216 | .s1_ack_i( gnd ), |
217 | .s1_err_i( gnd ), |
218 | .s1_rty_i( gnd ), |
219 | // Slave2 |
220 | .s2_dat_i( bram0_dat_r ), |
221 | .s2_dat_o( bram0_dat_w ), |
222 | .s2_adr_o( bram0_adr ), |
223 | .s2_sel_o( bram0_sel ), |
224 | .s2_we_o( bram0_we ), |
225 | .s2_cyc_o( bram0_cyc ), |
226 | .s2_stb_o( bram0_stb ), |
227 | .s2_ack_i( bram0_ack ), |
228 | .s2_err_i( gnd ), |
229 | .s2_rty_i( gnd ), |
230 | // Slave3 |
231 | .s3_dat_i( uart0_dat_r ), |
232 | .s3_dat_o( uart0_dat_w ), |
233 | .s3_adr_o( uart0_adr ), |
234 | .s3_sel_o( uart0_sel ), |
235 | .s3_we_o( uart0_we ), |
236 | .s3_cyc_o( uart0_cyc ), |
237 | .s3_stb_o( uart0_stb ), |
238 | .s3_ack_i( uart0_ack ), |
239 | .s3_err_i( gnd ), |
240 | .s3_rty_i( gnd ), |
241 | // Slave4 |
242 | .s4_dat_i( timer0_dat_r ), |
243 | .s4_dat_o( timer0_dat_w ), |
244 | .s4_adr_o( timer0_adr ), |
245 | .s4_sel_o( timer0_sel ), |
246 | .s4_we_o( timer0_we ), |
247 | .s4_cyc_o( timer0_cyc ), |
248 | .s4_stb_o( timer0_stb ), |
249 | .s4_ack_i( timer0_ack ), |
250 | .s4_err_i( gnd ), |
251 | .s4_rty_i( gnd ), |
252 | // Slave5 |
253 | .s5_dat_i( gpio0_dat_r ), |
254 | .s5_dat_o( gpio0_dat_w ), |
255 | .s5_adr_o( gpio0_adr ), |
256 | .s5_sel_o( gpio0_sel ), |
257 | .s5_we_o( gpio0_we ), |
258 | .s5_cyc_o( gpio0_cyc ), |
259 | .s5_stb_o( gpio0_stb ), |
260 | .s5_ack_i( gpio0_ack ), |
261 | .s5_err_i( gnd ), |
262 | .s5_rty_i( gnd ), |
263 | // Slave6 |
264 | .s6_dat_i( gnd32 ), |
265 | .s6_ack_i( gnd ), |
266 | .s6_err_i( gnd ), |
267 | .s6_rty_i( gnd ), |
268 | // Slave7 |
269 | .s7_dat_i( gnd32 ), |
270 | .s7_ack_i( gnd ), |
271 | .s7_err_i( gnd ), |
272 | .s7_rty_i( gnd ) |
273 | ); |
274 | |
275 | |
276 | //--------------------------------------------------------------------------- |
277 | // LM32 CPU |
278 | //--------------------------------------------------------------------------- |
279 | lm32_cpu lm0 ( |
280 | .clk_i( clk ), |
281 | .rst_i( ~rst ), |
282 | .interrupt_n( intr_n ), |
283 | // |
284 | .I_ADR_O( lm32i_adr ), |
285 | .I_DAT_I( lm32i_dat_r ), |
286 | .I_DAT_O( lm32i_dat_w ), |
287 | .I_SEL_O( lm32i_sel ), |
288 | .I_CYC_O( lm32i_cyc ), |
289 | .I_STB_O( lm32i_stb ), |
290 | .I_ACK_I( lm32i_ack ), |
291 | .I_WE_O ( lm32i_we ), |
292 | .I_CTI_O( lm32i_cti ), |
293 | .I_LOCK_O( lm32i_lock ), |
294 | .I_BTE_O( lm32i_bte ), |
295 | .I_ERR_I( lm32i_err ), |
296 | .I_RTY_I( lm32i_rty ), |
297 | // |
298 | .D_ADR_O( lm32d_adr ), |
299 | .D_DAT_I( lm32d_dat_r ), |
300 | .D_DAT_O( lm32d_dat_w ), |
301 | .D_SEL_O( lm32d_sel ), |
302 | .D_CYC_O( lm32d_cyc ), |
303 | .D_STB_O( lm32d_stb ), |
304 | .D_ACK_I( lm32d_ack ), |
305 | .D_WE_O ( lm32d_we ), |
306 | .D_CTI_O( lm32d_cti ), |
307 | .D_LOCK_O( lm32d_lock ), |
308 | .D_BTE_O( lm32d_bte ), |
309 | .D_ERR_I( lm32d_err ), |
310 | .D_RTY_I( lm32d_rty ) |
311 | ); |
312 | |
313 | //--------------------------------------------------------------------------- |
314 | // Block RAM |
315 | //--------------------------------------------------------------------------- |
316 | wb_bram #( |
317 | .adr_width( 12 ), |
318 | .mem_file_name( bootram_file ) |
319 | ) bram0 ( |
320 | .clk_i( clk ), |
321 | .rst_i( ~rst ), |
322 | // |
323 | .wb_adr_i( bram0_adr ), |
324 | .wb_dat_o( bram0_dat_r ), |
325 | .wb_dat_i( bram0_dat_w ), |
326 | .wb_sel_i( bram0_sel ), |
327 | .wb_stb_i( bram0_stb ), |
328 | .wb_cyc_i( bram0_cyc ), |
329 | .wb_ack_o( bram0_ack ), |
330 | .wb_we_i( bram0_we ) |
331 | ); |
332 | |
333 | //--------------------------------------------------------------------------- |
334 | // uart0 |
335 | //--------------------------------------------------------------------------- |
336 | wire uart0_rxd; |
337 | wire uart0_txd; |
338 | |
339 | wb_uart #( |
340 | .clk_freq( clk_freq ), |
341 | .baud( uart_baud_rate ) |
342 | ) uart0 ( |
343 | .clk( clk ), |
344 | .reset( ~rst ), |
345 | // |
346 | .wb_adr_i( uart0_adr ), |
347 | .wb_dat_i( uart0_dat_w ), |
348 | .wb_dat_o( uart0_dat_r ), |
349 | .wb_stb_i( uart0_stb ), |
350 | .wb_cyc_i( uart0_cyc ), |
351 | .wb_we_i( uart0_we ), |
352 | .wb_sel_i( uart0_sel ), |
353 | .wb_ack_o( uart0_ack ), |
354 | // .intr( uart0_intr ), |
355 | .uart_rxd( uart0_rxd ), |
356 | .uart_txd( uart0_txd ) |
357 | ); |
358 | |
359 | //--------------------------------------------------------------------------- |
360 | // timer0 |
361 | //--------------------------------------------------------------------------- |
362 | wb_timer #( |
363 | .clk_freq( clk_freq ) |
364 | ) timer0 ( |
365 | .clk( clk ), |
366 | .reset( ~rst ), |
367 | // |
368 | .wb_adr_i( timer0_adr ), |
369 | .wb_dat_i( timer0_dat_w ), |
370 | .wb_dat_o( timer0_dat_r ), |
371 | .wb_stb_i( timer0_stb ), |
372 | .wb_cyc_i( timer0_cyc ), |
373 | .wb_we_i( timer0_we ), |
374 | .wb_sel_i( timer0_sel ), |
375 | .wb_ack_o( timer0_ack ), |
376 | .intr( timer0_intr ) |
377 | ); |
378 | |
379 | //--------------------------------------------------------------------------- |
380 | // General Purpose IO |
381 | //--------------------------------------------------------------------------- |
382 | /* |
383 | wire [31:0] gpio0_in; |
384 | wire [31:0] gpio0_out; |
385 | wire [31:0] gpio0_oe; |
386 | |
387 | wb_gpio gpio0 ( |
388 | .clk( clk ), |
389 | .reset( rst ), |
390 | // |
391 | .wb_adr_i( gpio0_adr ), |
392 | .wb_dat_i( gpio0_dat_w ), |
393 | .wb_dat_o( gpio0_dat_r ), |
394 | .wb_stb_i( gpio0_stb ), |
395 | .wb_cyc_i( gpio0_cyc ), |
396 | .wb_we_i( gpio0_we ), |
397 | .wb_sel_i( gpio0_sel ), |
398 | .wb_ack_o( gpio0_ack ), |
399 | .intr( gpio0_intr ), |
400 | // GPIO |
401 | .gpio_in( gpio0_in ), |
402 | .gpio_out( gpio0_out ), |
403 | .gpio_oe( gpio0_oe ) |
404 | ); |
405 | */ |
406 | //---------------------------------------------------------------------------- |
407 | // Mux UART wires according to sw[0] |
408 | //---------------------------------------------------------------------------- |
409 | assign uart_txd = uart0_txd; |
410 | assign uart0_rxd = uart_rxd; |
411 | assign led = ~uart_txd; |
412 | endmodule |
413 |
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