Hardware Design: SIE
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Source at commit 47b7172e9896650584b804af3e984688abcd4c78 created 13 years 10 months ago. By Carlos Camargo, Fixing Makefile errors | |
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1 | # // ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-22-generic |
2 | # // |
3 | # // Copyright Mentor Graphics Corporation 2005 |
4 | # // All Rights Reserved. |
5 | # // |
6 | # // THIS WORK CONTAINS TRADE SECRET AND |
7 | # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY |
8 | # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS |
9 | # // AND IS SUBJECT TO LICENSE TERMS. |
10 | # // |
11 | # do sram_bus_TB.do |
12 | # ** Warning: (vlib-34) Library already exists at "work". |
13 | # Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005 |
14 | # -- Compiling module sram_bus |
15 | # -- Compiling module sram_bus_TB |
16 | # -- Compiling module glbl |
17 | # |
18 | # Top level modules: |
19 | # sram_bus_TB |
20 | # glbl |
21 | # vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl |
22 | # Loading work.sram_bus_TB |
23 | # Loading work.sram_bus |
24 | # Loading /opt/cad/modeltech/xilinx/verilog/unisims_ver.RAMB16_S2 |
25 | # Loading work.glbl |
26 | # ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7. |
27 | # Region: /sram_bus_TB/uut |
28 | # ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'. |
29 | # Region: /sram_bus_TB/uut |
30 | # ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'. |
31 | # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs |
32 | # .main_pane.workspace |
33 | # .main_pane.signals.interior.cs |
34 | quit |
35 |
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